]>
Commit | Line | Data |
---|---|---|
0d78f544 TS |
1 | /* |
2 | * Renesas SH7751R R2D-PLUS emulation | |
3 | * | |
4 | * Copyright (c) 2007 Magnus Damm | |
b319feb7 | 5 | * Copyright (c) 2008 Paul Mundt |
0d78f544 TS |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
9d4c9946 | 26 | #include "qemu/osdep.h" |
da34e65c | 27 | #include "qapi/error.h" |
83c9f4ca PB |
28 | #include "hw/sysbus.h" |
29 | #include "hw/hw.h" | |
0d09e41a | 30 | #include "hw/sh4/sh.h" |
bd2be150 | 31 | #include "hw/devices.h" |
9c17d615 | 32 | #include "sysemu/sysemu.h" |
83c9f4ca PB |
33 | #include "hw/boards.h" |
34 | #include "hw/pci/pci.h" | |
1422e32d | 35 | #include "net/net.h" |
47b43a1f | 36 | #include "sh7750_regs.h" |
83c9f4ca PB |
37 | #include "hw/ide.h" |
38 | #include "hw/loader.h" | |
39 | #include "hw/usb.h" | |
0d09e41a | 40 | #include "hw/block/flash.h" |
fa1d36df | 41 | #include "sysemu/block-backend.h" |
022c62cb | 42 | #include "exec/address-spaces.h" |
56839a19 AJ |
43 | |
44 | #define FLASH_BASE 0x00000000 | |
45 | #define FLASH_SIZE 0x02000000 | |
0d78f544 TS |
46 | |
47 | #define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */ | |
48 | #define SDRAM_SIZE 0x04000000 | |
49 | ||
ffd39257 BS |
50 | #define SM501_VRAM_SIZE 0x800000 |
51 | ||
73f19035 | 52 | #define BOOT_PARAMS_OFFSET 0x0010000 |
e8afa065 | 53 | /* CONFIG_BOOT_LINK_OFFSET of Linux kernel */ |
73f19035 AJ |
54 | #define LINUX_LOAD_OFFSET 0x0800000 |
55 | #define INITRD_LOAD_OFFSET 0x1800000 | |
e8afa065 | 56 | |
d47ede60 | 57 | #define PA_IRLMSK 0x00 |
b319feb7 AJ |
58 | #define PA_POWOFF 0x30 |
59 | #define PA_VERREG 0x32 | |
60 | #define PA_OUTPORT 0x36 | |
61 | ||
62 | typedef struct { | |
b319feb7 | 63 | uint16_t bcr; |
d47ede60 | 64 | uint16_t irlmsk; |
b319feb7 AJ |
65 | uint16_t irlmon; |
66 | uint16_t cfctl; | |
67 | uint16_t cfpow; | |
68 | uint16_t dispctl; | |
69 | uint16_t sdmpow; | |
70 | uint16_t rtcce; | |
71 | uint16_t pcicd; | |
72 | uint16_t voyagerrts; | |
73 | uint16_t cfrst; | |
74 | uint16_t admrts; | |
75 | uint16_t extrst; | |
76 | uint16_t cfcdintclr; | |
77 | uint16_t keyctlclr; | |
78 | uint16_t pad0; | |
79 | uint16_t pad1; | |
b319feb7 AJ |
80 | uint16_t verreg; |
81 | uint16_t inport; | |
82 | uint16_t outport; | |
83 | uint16_t bverreg; | |
d47ede60 AZ |
84 | |
85 | /* output pin */ | |
86 | qemu_irq irl; | |
5dea2efb | 87 | MemoryRegion iomem; |
c227f099 | 88 | } r2d_fpga_t; |
b319feb7 | 89 | |
d47ede60 AZ |
90 | enum r2d_fpga_irq { |
91 | PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T, | |
92 | SDCARD, PCI_INTA, PCI_INTB, EXT, TP, | |
93 | NR_IRQS | |
94 | }; | |
95 | ||
96 | static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = { | |
97 | [CF_IDE] = { 1, 1<<9 }, | |
98 | [CF_CD] = { 2, 1<<8 }, | |
99 | [PCI_INTA] = { 9, 1<<14 }, | |
100 | [PCI_INTB] = { 10, 1<<13 }, | |
101 | [PCI_INTC] = { 3, 1<<12 }, | |
102 | [PCI_INTD] = { 0, 1<<11 }, | |
103 | [SM501] = { 4, 1<<10 }, | |
104 | [KEY] = { 5, 1<<6 }, | |
105 | [RTC_A] = { 6, 1<<5 }, | |
106 | [RTC_T] = { 7, 1<<4 }, | |
107 | [SDCARD] = { 8, 1<<7 }, | |
108 | [EXT] = { 11, 1<<0 }, | |
109 | [TP] = { 12, 1<<15 }, | |
110 | }; | |
111 | ||
c227f099 | 112 | static void update_irl(r2d_fpga_t *fpga) |
d47ede60 AZ |
113 | { |
114 | int i, irl = 15; | |
115 | for (i = 0; i < NR_IRQS; i++) | |
116 | if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk) | |
117 | if (irqtab[i].irl < irl) | |
118 | irl = irqtab[i].irl; | |
119 | qemu_set_irq(fpga->irl, irl ^ 15); | |
120 | } | |
121 | ||
122 | static void r2d_fpga_irq_set(void *opaque, int n, int level) | |
123 | { | |
c227f099 | 124 | r2d_fpga_t *fpga = opaque; |
d47ede60 AZ |
125 | if (level) |
126 | fpga->irlmon |= irqtab[n].msk; | |
127 | else | |
128 | fpga->irlmon &= ~irqtab[n].msk; | |
129 | update_irl(fpga); | |
130 | } | |
131 | ||
56380752 | 132 | static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size) |
b319feb7 | 133 | { |
c227f099 | 134 | r2d_fpga_t *s = opaque; |
b319feb7 | 135 | |
b319feb7 | 136 | switch (addr) { |
d47ede60 AZ |
137 | case PA_IRLMSK: |
138 | return s->irlmsk; | |
b319feb7 AJ |
139 | case PA_OUTPORT: |
140 | return s->outport; | |
141 | case PA_POWOFF: | |
37cc0b44 | 142 | return 0x00; |
b319feb7 AJ |
143 | case PA_VERREG: |
144 | return 0x10; | |
145 | } | |
146 | ||
147 | return 0; | |
148 | } | |
149 | ||
150 | static void | |
56380752 | 151 | r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) |
b319feb7 | 152 | { |
c227f099 | 153 | r2d_fpga_t *s = opaque; |
b319feb7 | 154 | |
b319feb7 | 155 | switch (addr) { |
d47ede60 AZ |
156 | case PA_IRLMSK: |
157 | s->irlmsk = value; | |
158 | update_irl(s); | |
159 | break; | |
b319feb7 AJ |
160 | case PA_OUTPORT: |
161 | s->outport = value; | |
162 | break; | |
163 | case PA_POWOFF: | |
37cc0b44 AJ |
164 | if (value & 1) { |
165 | qemu_system_shutdown_request(); | |
166 | } | |
167 | break; | |
b319feb7 AJ |
168 | case PA_VERREG: |
169 | /* Discard writes */ | |
170 | break; | |
171 | } | |
172 | } | |
173 | ||
5dea2efb | 174 | static const MemoryRegionOps r2d_fpga_ops = { |
56380752 AJ |
175 | .read = r2d_fpga_read, |
176 | .write = r2d_fpga_write, | |
177 | .impl.min_access_size = 2, | |
178 | .impl.max_access_size = 2, | |
5dea2efb | 179 | .endianness = DEVICE_NATIVE_ENDIAN, |
b319feb7 AJ |
180 | }; |
181 | ||
5dea2efb | 182 | static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, |
a8170e5e | 183 | hwaddr base, qemu_irq irl) |
b319feb7 | 184 | { |
c227f099 | 185 | r2d_fpga_t *s; |
b319feb7 | 186 | |
7267c094 | 187 | s = g_malloc0(sizeof(r2d_fpga_t)); |
d47ede60 AZ |
188 | |
189 | s->irl = irl; | |
b319feb7 | 190 | |
2c9b15ca | 191 | memory_region_init_io(&s->iomem, NULL, &r2d_fpga_ops, s, "r2d-fpga", 0x40); |
5dea2efb | 192 | memory_region_add_subregion(sysmem, base, &s->iomem); |
d47ede60 | 193 | return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS); |
b319feb7 AJ |
194 | } |
195 | ||
4f6493ff | 196 | typedef struct ResetData { |
868bac81 | 197 | SuperHCPU *cpu; |
4f6493ff AJ |
198 | uint32_t vector; |
199 | } ResetData; | |
200 | ||
201 | static void main_cpu_reset(void *opaque) | |
202 | { | |
203 | ResetData *s = (ResetData *)opaque; | |
868bac81 | 204 | CPUSH4State *env = &s->cpu->env; |
4f6493ff | 205 | |
868bac81 | 206 | cpu_reset(CPU(s->cpu)); |
4f6493ff AJ |
207 | env->pc = s->vector; |
208 | } | |
209 | ||
541dc0d4 | 210 | static struct QEMU_PACKED |
73f19035 AJ |
211 | { |
212 | int mount_root_rdonly; | |
213 | int ramdisk_flags; | |
214 | int orig_root_dev; | |
215 | int loader_type; | |
216 | int initrd_start; | |
217 | int initrd_size; | |
218 | ||
219 | char pad[232]; | |
220 | ||
221 | char kernel_cmdline[256]; | |
222 | } boot_params; | |
223 | ||
3ef96221 | 224 | static void r2d_init(MachineState *machine) |
0d78f544 | 225 | { |
3ef96221 MA |
226 | const char *cpu_model = machine->cpu_model; |
227 | const char *kernel_filename = machine->kernel_filename; | |
228 | const char *kernel_cmdline = machine->kernel_cmdline; | |
229 | const char *initrd_filename = machine->initrd_filename; | |
fd2f410b | 230 | SuperHCPU *cpu; |
0b7ade1d | 231 | CPUSH4State *env; |
4f6493ff | 232 | ResetData *reset_info; |
0d78f544 | 233 | struct SH7750State *s; |
5dea2efb | 234 | MemoryRegion *sdram = g_new(MemoryRegion, 1); |
d47ede60 | 235 | qemu_irq *irq; |
751c6a17 | 236 | DriveInfo *dinfo; |
c2f01775 | 237 | int i; |
8c106233 BC |
238 | DeviceState *dev; |
239 | SysBusDevice *busdev; | |
27a9d2ea | 240 | MemoryRegion *address_space_mem = get_system_memory(); |
29b358f9 | 241 | PCIBus *pci_bus; |
0d78f544 | 242 | |
fd2f410b | 243 | if (cpu_model == NULL) { |
0fd3ca30 | 244 | cpu_model = "SH7751R"; |
fd2f410b | 245 | } |
aaed909a | 246 | |
fd2f410b AF |
247 | cpu = cpu_sh4_init(cpu_model); |
248 | if (cpu == NULL) { | |
aaed909a FB |
249 | fprintf(stderr, "Unable to find CPU definition\n"); |
250 | exit(1); | |
251 | } | |
fd2f410b AF |
252 | env = &cpu->env; |
253 | ||
7267c094 | 254 | reset_info = g_malloc0(sizeof(ResetData)); |
868bac81 | 255 | reset_info->cpu = cpu; |
4f6493ff AJ |
256 | reset_info->vector = env->pc; |
257 | qemu_register_reset(main_cpu_reset, reset_info); | |
0d78f544 TS |
258 | |
259 | /* Allocate memory space */ | |
f8ed85ac | 260 | memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal); |
c5705a77 | 261 | vmstate_register_ram_global(sdram); |
5dea2efb | 262 | memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); |
0d78f544 | 263 | /* Register peripherals */ |
2f493fee | 264 | s = sh7750_init(cpu, address_space_mem); |
5dea2efb | 265 | irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s)); |
8c106233 BC |
266 | |
267 | dev = qdev_create(NULL, "sh_pci"); | |
1356b98d | 268 | busdev = SYS_BUS_DEVICE(dev); |
8c106233 | 269 | qdev_init_nofail(dev); |
29b358f9 | 270 | pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci")); |
8c106233 BC |
271 | sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000)); |
272 | sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000)); | |
273 | sysbus_connect_irq(busdev, 0, irq[PCI_INTA]); | |
274 | sysbus_connect_irq(busdev, 1, irq[PCI_INTB]); | |
275 | sysbus_connect_irq(busdev, 2, irq[PCI_INTC]); | |
276 | sysbus_connect_irq(busdev, 3, irq[PCI_INTD]); | |
d47ede60 | 277 | |
27a9d2ea RH |
278 | sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE, |
279 | irq[SM501], serial_hds[2]); | |
a4a771c0 AZ |
280 | |
281 | /* onboard CF (True IDE mode, Master only). */ | |
612b2bd0 | 282 | dinfo = drive_get(IF_IDE, 0, 0); |
6b2578d6 AF |
283 | dev = qdev_create(NULL, "mmio-ide"); |
284 | busdev = SYS_BUS_DEVICE(dev); | |
285 | sysbus_connect_irq(busdev, 0, irq[CF_IDE]); | |
286 | qdev_prop_set_uint32(dev, "shift", 1); | |
287 | qdev_init_nofail(dev); | |
288 | sysbus_mmio_map(busdev, 0, 0x14001000); | |
289 | sysbus_mmio_map(busdev, 1, 0x1400080c); | |
290 | mmio_ide_init_drives(dev, dinfo, NULL); | |
a4a771c0 | 291 | |
56839a19 | 292 | /* onboard flash memory */ |
45e7e4bc | 293 | dinfo = drive_get(IF_PFLASH, 0, 0); |
cfe5f011 | 294 | pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE, |
4be74634 | 295 | dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, |
fa1d36df | 296 | (16 * 1024), FLASH_SIZE >> 16, |
612b2bd0 | 297 | 1, 4, 0x0000, 0x0000, 0x0000, 0x0000, |
01e0451a | 298 | 0x555, 0x2aa, 0); |
56839a19 | 299 | |
c2f01775 | 300 | /* NIC: rtl8139 on-board, and 2 slots. */ |
ab2da564 | 301 | for (i = 0; i < nb_nics; i++) |
29b358f9 DG |
302 | pci_nic_init_nofail(&nd_table[i], pci_bus, |
303 | "rtl8139", i==0 ? "2" : NULL); | |
c2f01775 | 304 | |
9caa3ec1 | 305 | /* USB keyboard */ |
456dcd8a | 306 | usb_create_simple(usb_bus_find(-1), "usb-kbd"); |
9caa3ec1 | 307 | |
0d78f544 | 308 | /* Todo: register on board registers */ |
73f19035 AJ |
309 | memset(&boot_params, 0, sizeof(boot_params)); |
310 | ||
e8afa065 | 311 | if (kernel_filename) { |
73f19035 AJ |
312 | int kernel_size; |
313 | ||
314 | kernel_size = load_image_targphys(kernel_filename, | |
315 | SDRAM_BASE + LINUX_LOAD_OFFSET, | |
316 | INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET); | |
317 | if (kernel_size < 0) { | |
318 | fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); | |
319 | exit(1); | |
320 | } | |
321 | ||
322 | /* initialization which should be done by firmware */ | |
42874d3a PM |
323 | address_space_stl(&address_space_memory, SH7750_BCR1, 1 << 3, |
324 | MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 SDRAM */ | |
325 | address_space_stw(&address_space_memory, SH7750_BCR2, 3 << (3 * 2), | |
326 | MEMTXATTRS_UNSPECIFIED, NULL); /* cs3 32bit */ | |
4f6493ff | 327 | reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */ |
0d78f544 | 328 | } |
73f19035 AJ |
329 | |
330 | if (initrd_filename) { | |
331 | int initrd_size; | |
332 | ||
333 | initrd_size = load_image_targphys(initrd_filename, | |
334 | SDRAM_BASE + INITRD_LOAD_OFFSET, | |
335 | SDRAM_SIZE - INITRD_LOAD_OFFSET); | |
336 | ||
337 | if (initrd_size < 0) { | |
338 | fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename); | |
339 | exit(1); | |
340 | } | |
341 | ||
342 | /* initialization which should be done by firmware */ | |
cdd14a8c GR |
343 | boot_params.loader_type = tswap32(1); |
344 | boot_params.initrd_start = tswap32(INITRD_LOAD_OFFSET); | |
345 | boot_params.initrd_size = tswap32(initrd_size); | |
73f19035 AJ |
346 | } |
347 | ||
348 | if (kernel_cmdline) { | |
9310b9be JM |
349 | /* I see no evidence that this .kernel_cmdline buffer requires |
350 | NUL-termination, so using strncpy should be ok. */ | |
73f19035 AJ |
351 | strncpy(boot_params.kernel_cmdline, kernel_cmdline, |
352 | sizeof(boot_params.kernel_cmdline)); | |
353 | } | |
354 | ||
355 | rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params), | |
356 | SDRAM_BASE + BOOT_PARAMS_OFFSET); | |
0d78f544 TS |
357 | } |
358 | ||
e264d29d | 359 | static void r2d_machine_init(MachineClass *mc) |
f80f9ec9 | 360 | { |
e264d29d EH |
361 | mc->desc = "r2d-plus board"; |
362 | mc->init = r2d_init; | |
f80f9ec9 AL |
363 | } |
364 | ||
e264d29d | 365 | DEFINE_MACHINE("r2d", r2d_machine_init) |