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Commit | Line | Data |
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27c7ca7e FB |
1 | /* |
2 | * SH7750 device | |
5fafdf24 | 3 | * |
80f515e6 | 4 | * Copyright (c) 2007 Magnus Damm |
27c7ca7e | 5 | * Copyright (c) 2005 Samuel Tardieu |
5fafdf24 | 6 | * |
27c7ca7e FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
9d4c9946 | 25 | #include "qemu/osdep.h" |
83c9f4ca | 26 | #include "hw/hw.h" |
0d09e41a | 27 | #include "hw/sh4/sh.h" |
9c17d615 | 28 | #include "sysemu/sysemu.h" |
47b43a1f PB |
29 | #include "sh7750_regs.h" |
30 | #include "sh7750_regnames.h" | |
0d09e41a | 31 | #include "hw/sh4/sh_intc.h" |
29e179bc | 32 | #include "cpu.h" |
63c91552 | 33 | #include "exec/exec-all.h" |
022c62cb | 34 | #include "exec/address-spaces.h" |
27c7ca7e | 35 | |
27c7ca7e FB |
36 | #define NB_DEVICES 4 |
37 | ||
38 | typedef struct SH7750State { | |
382863e2 BC |
39 | MemoryRegion iomem; |
40 | MemoryRegion iomem_1f0; | |
41 | MemoryRegion iomem_ff0; | |
42 | MemoryRegion iomem_1f8; | |
43 | MemoryRegion iomem_ff8; | |
44 | MemoryRegion iomem_1fc; | |
45 | MemoryRegion iomem_ffc; | |
1a4004c7 | 46 | MemoryRegion mmct_iomem; |
27c7ca7e | 47 | /* CPU */ |
2f493fee | 48 | SuperHCPU *cpu; |
27c7ca7e FB |
49 | /* Peripheral frequency in Hz */ |
50 | uint32_t periph_freq; | |
51 | /* SDRAM controller */ | |
c2f01775 | 52 | uint32_t bcr1; |
c2432a42 AJ |
53 | uint16_t bcr2; |
54 | uint16_t bcr3; | |
55 | uint32_t bcr4; | |
27c7ca7e | 56 | uint16_t rfcr; |
c2432a42 AJ |
57 | /* PCMCIA controller */ |
58 | uint16_t pcr; | |
27c7ca7e FB |
59 | /* IO ports */ |
60 | uint16_t gpioic; | |
61 | uint32_t pctra; | |
62 | uint32_t pctrb; | |
63 | uint16_t portdira; /* Cached */ | |
64 | uint16_t portpullupa; /* Cached */ | |
65 | uint16_t portdirb; /* Cached */ | |
66 | uint16_t portpullupb; /* Cached */ | |
67 | uint16_t pdtra; | |
68 | uint16_t pdtrb; | |
69 | uint16_t periph_pdtra; /* Imposed by the peripherals */ | |
70 | uint16_t periph_portdira; /* Direction seen from the peripherals */ | |
71 | uint16_t periph_pdtrb; /* Imposed by the peripherals */ | |
72 | uint16_t periph_portdirb; /* Direction seen from the peripherals */ | |
73 | sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ | |
3464c589 | 74 | |
27c7ca7e FB |
75 | /* Cache */ |
76 | uint32_t ccr; | |
27c7ca7e | 77 | |
80f515e6 | 78 | struct intc_desc intc; |
cd1a3f68 | 79 | } SH7750State; |
27c7ca7e | 80 | |
86178a57 | 81 | static inline int has_bcr3_and_bcr4(SH7750State * s) |
c2432a42 | 82 | { |
2f493fee | 83 | return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4; |
c2432a42 | 84 | } |
27c7ca7e FB |
85 | /********************************************************************** |
86 | I/O ports | |
87 | **********************************************************************/ | |
88 | ||
89 | int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) | |
90 | { | |
91 | int i; | |
92 | ||
93 | for (i = 0; i < NB_DEVICES; i++) { | |
94 | if (s->devices[i] == NULL) { | |
95 | s->devices[i] = device; | |
96 | return 0; | |
97 | } | |
98 | } | |
99 | return -1; | |
100 | } | |
101 | ||
102 | static uint16_t portdir(uint32_t v) | |
103 | { | |
104 | #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) | |
105 | return | |
106 | EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | | |
107 | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | | |
108 | EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | | |
109 | EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | | |
110 | EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | | |
111 | EVENPORTMASK(0); | |
112 | } | |
113 | ||
114 | static uint16_t portpullup(uint32_t v) | |
115 | { | |
116 | #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) | |
117 | return | |
118 | ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | | |
119 | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | | |
120 | ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | | |
121 | ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | | |
122 | ODDPORTMASK(1) | ODDPORTMASK(0); | |
123 | } | |
124 | ||
125 | static uint16_t porta_lines(SH7750State * s) | |
126 | { | |
127 | return (s->portdira & s->pdtra) | /* CPU */ | |
128 | (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ | |
129 | (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ | |
130 | } | |
131 | ||
132 | static uint16_t portb_lines(SH7750State * s) | |
133 | { | |
134 | return (s->portdirb & s->pdtrb) | /* CPU */ | |
135 | (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ | |
136 | (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ | |
137 | } | |
138 | ||
139 | static void gen_port_interrupts(SH7750State * s) | |
140 | { | |
141 | /* XXXXX interrupts not generated */ | |
142 | } | |
143 | ||
144 | static void porta_changed(SH7750State * s, uint16_t prev) | |
145 | { | |
146 | uint16_t currenta, changes; | |
147 | int i, r = 0; | |
148 | ||
149 | #if 0 | |
150 | fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n", | |
151 | prev, porta_lines(s)); | |
152 | fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); | |
153 | #endif | |
154 | currenta = porta_lines(s); | |
155 | if (currenta == prev) | |
156 | return; | |
157 | changes = currenta ^ prev; | |
158 | ||
159 | for (i = 0; i < NB_DEVICES; i++) { | |
160 | if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) { | |
161 | r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), | |
162 | &s->periph_pdtra, | |
163 | &s->periph_portdira, | |
164 | &s->periph_pdtrb, | |
165 | &s->periph_portdirb); | |
166 | } | |
167 | } | |
168 | ||
169 | if (r) | |
170 | gen_port_interrupts(s); | |
171 | } | |
172 | ||
173 | static void portb_changed(SH7750State * s, uint16_t prev) | |
174 | { | |
175 | uint16_t currentb, changes; | |
176 | int i, r = 0; | |
177 | ||
178 | currentb = portb_lines(s); | |
179 | if (currentb == prev) | |
180 | return; | |
181 | changes = currentb ^ prev; | |
182 | ||
183 | for (i = 0; i < NB_DEVICES; i++) { | |
184 | if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) { | |
185 | r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, | |
186 | &s->periph_pdtra, | |
187 | &s->periph_portdira, | |
188 | &s->periph_pdtrb, | |
189 | &s->periph_portdirb); | |
190 | } | |
191 | } | |
192 | ||
193 | if (r) | |
194 | gen_port_interrupts(s); | |
195 | } | |
196 | ||
197 | /********************************************************************** | |
198 | Memory | |
199 | **********************************************************************/ | |
200 | ||
a8170e5e | 201 | static void error_access(const char *kind, hwaddr addr) |
27c7ca7e | 202 | { |
526ccb7a | 203 | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", |
27c7ca7e FB |
204 | kind, regname(addr), addr); |
205 | } | |
206 | ||
a8170e5e | 207 | static void ignore_access(const char *kind, hwaddr addr) |
27c7ca7e | 208 | { |
526ccb7a | 209 | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", |
27c7ca7e FB |
210 | kind, regname(addr), addr); |
211 | } | |
212 | ||
a8170e5e | 213 | static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) |
27c7ca7e | 214 | { |
27c7ca7e | 215 | switch (addr) { |
27c7ca7e FB |
216 | default: |
217 | error_access("byte read", addr); | |
43dc2a64 | 218 | abort(); |
27c7ca7e FB |
219 | } |
220 | } | |
221 | ||
a8170e5e | 222 | static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) |
27c7ca7e FB |
223 | { |
224 | SH7750State *s = opaque; | |
27c7ca7e FB |
225 | |
226 | switch (addr) { | |
c2f01775 AZ |
227 | case SH7750_BCR2_A7: |
228 | return s->bcr2; | |
c2432a42 AJ |
229 | case SH7750_BCR3_A7: |
230 | if(!has_bcr3_and_bcr4(s)) | |
231 | error_access("word read", addr); | |
232 | return s->bcr3; | |
ed8e0a4d TS |
233 | case SH7750_FRQCR_A7: |
234 | return 0; | |
c2432a42 AJ |
235 | case SH7750_PCR_A7: |
236 | return s->pcr; | |
27c7ca7e FB |
237 | case SH7750_RFCR_A7: |
238 | fprintf(stderr, | |
239 | "Read access to refresh count register, incrementing\n"); | |
240 | return s->rfcr++; | |
27c7ca7e FB |
241 | case SH7750_PDTRA_A7: |
242 | return porta_lines(s); | |
243 | case SH7750_PDTRB_A7: | |
244 | return portb_lines(s); | |
c2432a42 AJ |
245 | case SH7750_RTCOR_A7: |
246 | case SH7750_RTCNT_A7: | |
247 | case SH7750_RTCSR_A7: | |
248 | ignore_access("word read", addr); | |
249 | return 0; | |
27c7ca7e FB |
250 | default: |
251 | error_access("word read", addr); | |
43dc2a64 | 252 | abort(); |
27c7ca7e FB |
253 | } |
254 | } | |
255 | ||
a8170e5e | 256 | static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) |
27c7ca7e FB |
257 | { |
258 | SH7750State *s = opaque; | |
b350ab75 | 259 | SuperHCPUClass *scc; |
27c7ca7e FB |
260 | |
261 | switch (addr) { | |
c2f01775 AZ |
262 | case SH7750_BCR1_A7: |
263 | return s->bcr1; | |
264 | case SH7750_BCR4_A7: | |
c2432a42 AJ |
265 | if(!has_bcr3_and_bcr4(s)) |
266 | error_access("long read", addr); | |
267 | return s->bcr4; | |
c2f01775 AZ |
268 | case SH7750_WCR1_A7: |
269 | case SH7750_WCR2_A7: | |
270 | case SH7750_WCR3_A7: | |
271 | case SH7750_MCR_A7: | |
272 | ignore_access("long read", addr); | |
273 | return 0; | |
27c7ca7e | 274 | case SH7750_MMUCR_A7: |
2f493fee | 275 | return s->cpu->env.mmucr; |
27c7ca7e | 276 | case SH7750_PTEH_A7: |
2f493fee | 277 | return s->cpu->env.pteh; |
27c7ca7e | 278 | case SH7750_PTEL_A7: |
2f493fee | 279 | return s->cpu->env.ptel; |
27c7ca7e | 280 | case SH7750_TTB_A7: |
2f493fee | 281 | return s->cpu->env.ttb; |
27c7ca7e | 282 | case SH7750_TEA_A7: |
2f493fee | 283 | return s->cpu->env.tea; |
27c7ca7e | 284 | case SH7750_TRA_A7: |
2f493fee | 285 | return s->cpu->env.tra; |
27c7ca7e | 286 | case SH7750_EXPEVT_A7: |
2f493fee | 287 | return s->cpu->env.expevt; |
27c7ca7e | 288 | case SH7750_INTEVT_A7: |
2f493fee | 289 | return s->cpu->env.intevt; |
27c7ca7e FB |
290 | case SH7750_CCR_A7: |
291 | return s->ccr; | |
0fd3ca30 | 292 | case 0x1f000030: /* Processor version */ |
b350ab75 AF |
293 | scc = SUPERH_CPU_GET_CLASS(s->cpu); |
294 | return scc->pvr; | |
0fd3ca30 | 295 | case 0x1f000040: /* Cache version */ |
b350ab75 AF |
296 | scc = SUPERH_CPU_GET_CLASS(s->cpu); |
297 | return scc->cvr; | |
0fd3ca30 | 298 | case 0x1f000044: /* Processor revision */ |
b350ab75 AF |
299 | scc = SUPERH_CPU_GET_CLASS(s->cpu); |
300 | return scc->prr; | |
27c7ca7e FB |
301 | default: |
302 | error_access("long read", addr); | |
43dc2a64 | 303 | abort(); |
27c7ca7e FB |
304 | } |
305 | } | |
306 | ||
c2432a42 AJ |
307 | #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ |
308 | && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) | |
a8170e5e | 309 | static void sh7750_mem_writeb(void *opaque, hwaddr addr, |
27c7ca7e FB |
310 | uint32_t mem_value) |
311 | { | |
c2432a42 AJ |
312 | |
313 | if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { | |
27c7ca7e FB |
314 | ignore_access("byte write", addr); |
315 | return; | |
27c7ca7e | 316 | } |
c2432a42 AJ |
317 | |
318 | error_access("byte write", addr); | |
43dc2a64 | 319 | abort(); |
27c7ca7e FB |
320 | } |
321 | ||
a8170e5e | 322 | static void sh7750_mem_writew(void *opaque, hwaddr addr, |
27c7ca7e FB |
323 | uint32_t mem_value) |
324 | { | |
325 | SH7750State *s = opaque; | |
326 | uint16_t temp; | |
327 | ||
328 | switch (addr) { | |
329 | /* SDRAM controller */ | |
27c7ca7e | 330 | case SH7750_BCR2_A7: |
c2f01775 AZ |
331 | s->bcr2 = mem_value; |
332 | return; | |
27c7ca7e | 333 | case SH7750_BCR3_A7: |
c2432a42 AJ |
334 | if(!has_bcr3_and_bcr4(s)) |
335 | error_access("word write", addr); | |
336 | s->bcr3 = mem_value; | |
337 | return; | |
338 | case SH7750_PCR_A7: | |
339 | s->pcr = mem_value; | |
340 | return; | |
27c7ca7e | 341 | case SH7750_RTCNT_A7: |
c2432a42 | 342 | case SH7750_RTCOR_A7: |
27c7ca7e FB |
343 | case SH7750_RTCSR_A7: |
344 | ignore_access("word write", addr); | |
345 | return; | |
346 | /* IO ports */ | |
347 | case SH7750_PDTRA_A7: | |
348 | temp = porta_lines(s); | |
349 | s->pdtra = mem_value; | |
350 | porta_changed(s, temp); | |
351 | return; | |
352 | case SH7750_PDTRB_A7: | |
353 | temp = portb_lines(s); | |
354 | s->pdtrb = mem_value; | |
355 | portb_changed(s, temp); | |
356 | return; | |
357 | case SH7750_RFCR_A7: | |
358 | fprintf(stderr, "Write access to refresh count register\n"); | |
359 | s->rfcr = mem_value; | |
360 | return; | |
27c7ca7e FB |
361 | case SH7750_GPIOIC_A7: |
362 | s->gpioic = mem_value; | |
363 | if (mem_value != 0) { | |
364 | fprintf(stderr, "I/O interrupts not implemented\n"); | |
43dc2a64 | 365 | abort(); |
27c7ca7e FB |
366 | } |
367 | return; | |
368 | default: | |
369 | error_access("word write", addr); | |
43dc2a64 | 370 | abort(); |
27c7ca7e FB |
371 | } |
372 | } | |
373 | ||
a8170e5e | 374 | static void sh7750_mem_writel(void *opaque, hwaddr addr, |
27c7ca7e FB |
375 | uint32_t mem_value) |
376 | { | |
377 | SH7750State *s = opaque; | |
378 | uint16_t temp; | |
379 | ||
380 | switch (addr) { | |
381 | /* SDRAM controller */ | |
382 | case SH7750_BCR1_A7: | |
c2f01775 AZ |
383 | s->bcr1 = mem_value; |
384 | return; | |
27c7ca7e | 385 | case SH7750_BCR4_A7: |
c2432a42 AJ |
386 | if(!has_bcr3_and_bcr4(s)) |
387 | error_access("long write", addr); | |
388 | s->bcr4 = mem_value; | |
389 | return; | |
27c7ca7e FB |
390 | case SH7750_WCR1_A7: |
391 | case SH7750_WCR2_A7: | |
392 | case SH7750_WCR3_A7: | |
393 | case SH7750_MCR_A7: | |
394 | ignore_access("long write", addr); | |
395 | return; | |
396 | /* IO ports */ | |
397 | case SH7750_PCTRA_A7: | |
398 | temp = porta_lines(s); | |
399 | s->pctra = mem_value; | |
400 | s->portdira = portdir(mem_value); | |
401 | s->portpullupa = portpullup(mem_value); | |
402 | porta_changed(s, temp); | |
403 | return; | |
404 | case SH7750_PCTRB_A7: | |
405 | temp = portb_lines(s); | |
406 | s->pctrb = mem_value; | |
407 | s->portdirb = portdir(mem_value); | |
408 | s->portpullupb = portpullup(mem_value); | |
409 | portb_changed(s, temp); | |
410 | return; | |
27c7ca7e | 411 | case SH7750_MMUCR_A7: |
e0bcb9ca | 412 | if (mem_value & MMUCR_TI) { |
2f493fee | 413 | cpu_sh4_invalidate_tlb(&s->cpu->env); |
e0bcb9ca | 414 | } |
2f493fee | 415 | s->cpu->env.mmucr = mem_value & ~MMUCR_TI; |
e0bcb9ca | 416 | return; |
27c7ca7e | 417 | case SH7750_PTEH_A7: |
06afe2c8 | 418 | /* If asid changes, clear all registered tlb entries. */ |
2f493fee | 419 | if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) { |
00c8cb0a | 420 | tlb_flush(CPU(s->cpu), 1); |
2f493fee AF |
421 | } |
422 | s->cpu->env.pteh = mem_value; | |
423 | return; | |
27c7ca7e | 424 | case SH7750_PTEL_A7: |
2f493fee AF |
425 | s->cpu->env.ptel = mem_value; |
426 | return; | |
ea2b542a | 427 | case SH7750_PTEA_A7: |
2f493fee AF |
428 | s->cpu->env.ptea = mem_value & 0x0000000f; |
429 | return; | |
27c7ca7e | 430 | case SH7750_TTB_A7: |
2f493fee AF |
431 | s->cpu->env.ttb = mem_value; |
432 | return; | |
27c7ca7e | 433 | case SH7750_TEA_A7: |
2f493fee AF |
434 | s->cpu->env.tea = mem_value; |
435 | return; | |
27c7ca7e | 436 | case SH7750_TRA_A7: |
2f493fee AF |
437 | s->cpu->env.tra = mem_value & 0x000007ff; |
438 | return; | |
27c7ca7e | 439 | case SH7750_EXPEVT_A7: |
2f493fee AF |
440 | s->cpu->env.expevt = mem_value & 0x000007ff; |
441 | return; | |
27c7ca7e | 442 | case SH7750_INTEVT_A7: |
2f493fee AF |
443 | s->cpu->env.intevt = mem_value & 0x000007ff; |
444 | return; | |
27c7ca7e FB |
445 | case SH7750_CCR_A7: |
446 | s->ccr = mem_value; | |
447 | return; | |
448 | default: | |
449 | error_access("long write", addr); | |
43dc2a64 | 450 | abort(); |
27c7ca7e FB |
451 | } |
452 | } | |
453 | ||
382863e2 BC |
454 | static const MemoryRegionOps sh7750_mem_ops = { |
455 | .old_mmio = { | |
456 | .read = {sh7750_mem_readb, | |
457 | sh7750_mem_readw, | |
458 | sh7750_mem_readl }, | |
459 | .write = {sh7750_mem_writeb, | |
460 | sh7750_mem_writew, | |
461 | sh7750_mem_writel }, | |
462 | }, | |
463 | .endianness = DEVICE_NATIVE_ENDIAN, | |
27c7ca7e FB |
464 | }; |
465 | ||
80f515e6 AZ |
466 | /* sh775x interrupt controller tables for sh_intc.c |
467 | * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |
468 | */ | |
469 | ||
470 | enum { | |
471 | UNUSED = 0, | |
472 | ||
473 | /* interrupt sources */ | |
c6d86a33 AZ |
474 | IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, |
475 | IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, | |
476 | IRL0, IRL1, IRL2, IRL3, | |
80f515e6 AZ |
477 | HUDI, GPIOI, |
478 | DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, | |
479 | DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, | |
480 | DMAC_DMAE, | |
481 | PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | |
482 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, | |
483 | TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, | |
484 | RTC_ATI, RTC_PRI, RTC_CUI, | |
485 | SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, | |
486 | SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, | |
487 | WDT, | |
488 | REF_RCMI, REF_ROVI, | |
489 | ||
490 | /* interrupt groups */ | |
491 | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, | |
c6d86a33 AZ |
492 | /* irl bundle */ |
493 | IRL, | |
80f515e6 AZ |
494 | |
495 | NR_SOURCES, | |
496 | }; | |
497 | ||
498 | static struct intc_vect vectors[] = { | |
499 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), | |
500 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | |
501 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), | |
502 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), | |
503 | INTC_VECT(RTC_CUI, 0x4c0), | |
504 | INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), | |
505 | INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), | |
506 | INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), | |
507 | INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), | |
508 | INTC_VECT(WDT, 0x560), | |
509 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), | |
510 | }; | |
511 | ||
512 | static struct intc_group groups[] = { | |
513 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), | |
514 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | |
515 | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), | |
516 | INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), | |
517 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | |
518 | }; | |
519 | ||
520 | static struct intc_prio_reg prio_registers[] = { | |
521 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | |
522 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, | |
523 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, | |
524 | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, | |
525 | { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, | |
526 | TMU4, TMU3, | |
527 | PCIC1, PCIC0_PCISERR } }, | |
528 | }; | |
529 | ||
530 | /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ | |
531 | ||
532 | static struct intc_vect vectors_dma4[] = { | |
533 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | |
534 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | |
535 | INTC_VECT(DMAC_DMAE, 0x6c0), | |
536 | }; | |
537 | ||
538 | static struct intc_group groups_dma4[] = { | |
539 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | |
540 | DMAC_DMTE3, DMAC_DMAE), | |
541 | }; | |
542 | ||
543 | /* SH7750R and SH7751R both have 8-channel DMA controllers */ | |
544 | ||
545 | static struct intc_vect vectors_dma8[] = { | |
546 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | |
547 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | |
548 | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), | |
549 | INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), | |
550 | INTC_VECT(DMAC_DMAE, 0x6c0), | |
551 | }; | |
552 | ||
553 | static struct intc_group groups_dma8[] = { | |
554 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | |
555 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, | |
556 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), | |
557 | }; | |
558 | ||
559 | /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ | |
560 | ||
561 | static struct intc_vect vectors_tmu34[] = { | |
562 | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), | |
563 | }; | |
564 | ||
565 | static struct intc_mask_reg mask_registers[] = { | |
566 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ | |
567 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
568 | 0, 0, 0, 0, 0, 0, TMU4, TMU3, | |
569 | PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | |
570 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, | |
571 | PCIC1_PCIDMA3, PCIC0_PCISERR } }, | |
572 | }; | |
573 | ||
574 | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ | |
575 | ||
576 | static struct intc_vect vectors_irlm[] = { | |
577 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | |
578 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | |
579 | }; | |
580 | ||
581 | /* SH7751 and SH7751R both have PCI */ | |
582 | ||
583 | static struct intc_vect vectors_pci[] = { | |
584 | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), | |
585 | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), | |
586 | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), | |
587 | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), | |
588 | }; | |
589 | ||
590 | static struct intc_group groups_pci[] = { | |
591 | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | |
592 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), | |
593 | }; | |
594 | ||
c6d86a33 AZ |
595 | static struct intc_vect vectors_irl[] = { |
596 | INTC_VECT(IRL_0, 0x200), | |
597 | INTC_VECT(IRL_1, 0x220), | |
598 | INTC_VECT(IRL_2, 0x240), | |
599 | INTC_VECT(IRL_3, 0x260), | |
600 | INTC_VECT(IRL_4, 0x280), | |
601 | INTC_VECT(IRL_5, 0x2a0), | |
602 | INTC_VECT(IRL_6, 0x2c0), | |
603 | INTC_VECT(IRL_7, 0x2e0), | |
604 | INTC_VECT(IRL_8, 0x300), | |
605 | INTC_VECT(IRL_9, 0x320), | |
606 | INTC_VECT(IRL_A, 0x340), | |
607 | INTC_VECT(IRL_B, 0x360), | |
608 | INTC_VECT(IRL_C, 0x380), | |
609 | INTC_VECT(IRL_D, 0x3a0), | |
610 | INTC_VECT(IRL_E, 0x3c0), | |
611 | }; | |
612 | ||
613 | static struct intc_group groups_irl[] = { | |
614 | INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, | |
615 | IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), | |
616 | }; | |
617 | ||
29e179bc AJ |
618 | /********************************************************************** |
619 | Memory mapped cache and TLB | |
620 | **********************************************************************/ | |
621 | ||
622 | #define MM_REGION_MASK 0x07000000 | |
623 | #define MM_ICACHE_ADDR (0) | |
624 | #define MM_ICACHE_DATA (1) | |
625 | #define MM_ITLB_ADDR (2) | |
626 | #define MM_ITLB_DATA (3) | |
627 | #define MM_OCACHE_ADDR (4) | |
628 | #define MM_OCACHE_DATA (5) | |
629 | #define MM_UTLB_ADDR (6) | |
630 | #define MM_UTLB_DATA (7) | |
631 | #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) | |
632 | ||
a8170e5e | 633 | static uint64_t invalid_read(void *opaque, hwaddr addr) |
29e179bc | 634 | { |
43dc2a64 | 635 | abort(); |
29e179bc AJ |
636 | |
637 | return 0; | |
638 | } | |
639 | ||
a8170e5e | 640 | static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, |
1a4004c7 | 641 | unsigned size) |
29e179bc | 642 | { |
bc656a29 | 643 | SH7750State *s = opaque; |
29e179bc AJ |
644 | uint32_t ret = 0; |
645 | ||
1a4004c7 BC |
646 | if (size != 4) { |
647 | return invalid_read(opaque, addr); | |
648 | } | |
649 | ||
29e179bc AJ |
650 | switch (MM_REGION_TYPE(addr)) { |
651 | case MM_ICACHE_ADDR: | |
652 | case MM_ICACHE_DATA: | |
653 | /* do nothing */ | |
654 | break; | |
655 | case MM_ITLB_ADDR: | |
2f493fee | 656 | ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr); |
bc656a29 | 657 | break; |
29e179bc | 658 | case MM_ITLB_DATA: |
2f493fee | 659 | ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr); |
bc656a29 | 660 | break; |
29e179bc AJ |
661 | case MM_OCACHE_ADDR: |
662 | case MM_OCACHE_DATA: | |
663 | /* do nothing */ | |
664 | break; | |
665 | case MM_UTLB_ADDR: | |
2f493fee | 666 | ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr); |
bc656a29 | 667 | break; |
29e179bc | 668 | case MM_UTLB_DATA: |
2f493fee | 669 | ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr); |
bc656a29 | 670 | break; |
29e179bc | 671 | default: |
43dc2a64 | 672 | abort(); |
29e179bc AJ |
673 | } |
674 | ||
675 | return ret; | |
676 | } | |
677 | ||
a8170e5e | 678 | static void invalid_write(void *opaque, hwaddr addr, |
1a4004c7 | 679 | uint64_t mem_value) |
29e179bc | 680 | { |
43dc2a64 | 681 | abort(); |
29e179bc AJ |
682 | } |
683 | ||
a8170e5e | 684 | static void sh7750_mmct_write(void *opaque, hwaddr addr, |
1a4004c7 | 685 | uint64_t mem_value, unsigned size) |
29e179bc AJ |
686 | { |
687 | SH7750State *s = opaque; | |
688 | ||
1a4004c7 BC |
689 | if (size != 4) { |
690 | invalid_write(opaque, addr, mem_value); | |
691 | } | |
692 | ||
29e179bc AJ |
693 | switch (MM_REGION_TYPE(addr)) { |
694 | case MM_ICACHE_ADDR: | |
695 | case MM_ICACHE_DATA: | |
696 | /* do nothing */ | |
697 | break; | |
698 | case MM_ITLB_ADDR: | |
2f493fee | 699 | cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value); |
c0f809c4 | 700 | break; |
29e179bc | 701 | case MM_ITLB_DATA: |
2f493fee | 702 | cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value); |
43dc2a64 | 703 | abort(); |
29e179bc AJ |
704 | break; |
705 | case MM_OCACHE_ADDR: | |
706 | case MM_OCACHE_DATA: | |
707 | /* do nothing */ | |
708 | break; | |
709 | case MM_UTLB_ADDR: | |
2f493fee | 710 | cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value); |
29e179bc AJ |
711 | break; |
712 | case MM_UTLB_DATA: | |
2f493fee | 713 | cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value); |
29e179bc AJ |
714 | break; |
715 | default: | |
43dc2a64 | 716 | abort(); |
29e179bc AJ |
717 | break; |
718 | } | |
719 | } | |
720 | ||
12f30833 | 721 | static const MemoryRegionOps sh7750_mmct_ops = { |
1a4004c7 BC |
722 | .read = sh7750_mmct_read, |
723 | .write = sh7750_mmct_write, | |
724 | .endianness = DEVICE_NATIVE_ENDIAN, | |
29e179bc AJ |
725 | }; |
726 | ||
2f493fee | 727 | SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem) |
27c7ca7e FB |
728 | { |
729 | SH7750State *s; | |
27c7ca7e | 730 | |
7267c094 | 731 | s = g_malloc0(sizeof(SH7750State)); |
27c7ca7e FB |
732 | s->cpu = cpu; |
733 | s->periph_freq = 60000000; /* 60MHz */ | |
2c9b15ca | 734 | memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s, |
382863e2 BC |
735 | "memory", 0x1fc01000); |
736 | ||
2c9b15ca | 737 | memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0", |
382863e2 BC |
738 | &s->iomem, 0x1f000000, 0x1000); |
739 | memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0); | |
740 | ||
2c9b15ca | 741 | memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0", |
382863e2 BC |
742 | &s->iomem, 0x1f000000, 0x1000); |
743 | memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0); | |
744 | ||
2c9b15ca | 745 | memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8", |
382863e2 BC |
746 | &s->iomem, 0x1f800000, 0x1000); |
747 | memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8); | |
748 | ||
2c9b15ca | 749 | memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8", |
382863e2 BC |
750 | &s->iomem, 0x1f800000, 0x1000); |
751 | memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8); | |
752 | ||
2c9b15ca | 753 | memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc", |
382863e2 BC |
754 | &s->iomem, 0x1fc00000, 0x1000); |
755 | memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc); | |
756 | ||
2c9b15ca | 757 | memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc", |
382863e2 BC |
758 | &s->iomem, 0x1fc00000, 0x1000); |
759 | memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); | |
2f062c72 | 760 | |
2c9b15ca | 761 | memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s, |
1a4004c7 BC |
762 | "cache-and-tlb", 0x08000000); |
763 | memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); | |
29e179bc | 764 | |
b279e5ef | 765 | sh_intc_init(sysmem, &s->intc, NR_SOURCES, |
80f515e6 AZ |
766 | _INTC_ARRAY(mask_registers), |
767 | _INTC_ARRAY(prio_registers)); | |
768 | ||
0fd3ca30 | 769 | sh_intc_register_sources(&s->intc, |
80f515e6 AZ |
770 | _INTC_ARRAY(vectors), |
771 | _INTC_ARRAY(groups)); | |
772 | ||
2f493fee | 773 | cpu->env.intc_handle = &s->intc; |
e96e2044 | 774 | |
9a9d0b81 BC |
775 | sh_serial_init(sysmem, 0x1fe00000, |
776 | 0, s->periph_freq, serial_hds[0], | |
777 | s->intc.irqs[SCI1_ERI], | |
778 | s->intc.irqs[SCI1_RXI], | |
779 | s->intc.irqs[SCI1_TXI], | |
780 | s->intc.irqs[SCI1_TEI], | |
781 | NULL); | |
782 | sh_serial_init(sysmem, 0x1fe80000, | |
783 | SH_SERIAL_FEAT_SCIF, | |
784 | s->periph_freq, serial_hds[1], | |
785 | s->intc.irqs[SCIF_ERI], | |
786 | s->intc.irqs[SCIF_RXI], | |
787 | s->intc.irqs[SCIF_TXI], | |
788 | NULL, | |
789 | s->intc.irqs[SCIF_BRI]); | |
cd1a3f68 | 790 | |
89e29451 | 791 | tmu012_init(sysmem, 0x1fd80000, |
cd1a3f68 | 792 | TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
703243a0 | 793 | s->periph_freq, |
96e2fc41 AJ |
794 | s->intc.irqs[TMU0], |
795 | s->intc.irqs[TMU1], | |
796 | s->intc.irqs[TMU2_TUNI], | |
797 | s->intc.irqs[TMU2_TICPI]); | |
80f515e6 | 798 | |
2f493fee | 799 | if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { |
0fd3ca30 | 800 | sh_intc_register_sources(&s->intc, |
80f515e6 AZ |
801 | _INTC_ARRAY(vectors_dma4), |
802 | _INTC_ARRAY(groups_dma4)); | |
803 | } | |
804 | ||
2f493fee | 805 | if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { |
0fd3ca30 | 806 | sh_intc_register_sources(&s->intc, |
80f515e6 AZ |
807 | _INTC_ARRAY(vectors_dma8), |
808 | _INTC_ARRAY(groups_dma8)); | |
809 | } | |
810 | ||
2f493fee | 811 | if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { |
0fd3ca30 | 812 | sh_intc_register_sources(&s->intc, |
80f515e6 | 813 | _INTC_ARRAY(vectors_tmu34), |
f26ae302 | 814 | NULL, 0); |
89e29451 | 815 | tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, |
96e2fc41 AJ |
816 | s->intc.irqs[TMU3], |
817 | s->intc.irqs[TMU4], | |
703243a0 | 818 | NULL, NULL); |
80f515e6 AZ |
819 | } |
820 | ||
2f493fee | 821 | if (cpu->env.id & (SH_CPU_SH7751_ALL)) { |
0fd3ca30 | 822 | sh_intc_register_sources(&s->intc, |
80f515e6 AZ |
823 | _INTC_ARRAY(vectors_pci), |
824 | _INTC_ARRAY(groups_pci)); | |
825 | } | |
826 | ||
2f493fee | 827 | if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { |
0fd3ca30 | 828 | sh_intc_register_sources(&s->intc, |
80f515e6 | 829 | _INTC_ARRAY(vectors_irlm), |
f26ae302 | 830 | NULL, 0); |
80f515e6 AZ |
831 | } |
832 | ||
c6d86a33 AZ |
833 | sh_intc_register_sources(&s->intc, |
834 | _INTC_ARRAY(vectors_irl), | |
835 | _INTC_ARRAY(groups_irl)); | |
27c7ca7e FB |
836 | return s; |
837 | } | |
c6d86a33 AZ |
838 | |
839 | qemu_irq sh7750_irl(SH7750State *s) | |
840 | { | |
841 | sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ | |
f3c7d038 | 842 | return qemu_allocate_irq(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), 0); |
c6d86a33 | 843 | } |