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Commit | Line | Data |
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27c7ca7e FB |
1 | /* |
2 | * SH7750 device | |
5fafdf24 | 3 | * |
80f515e6 | 4 | * Copyright (c) 2007 Magnus Damm |
27c7ca7e | 5 | * Copyright (c) 2005 Samuel Tardieu |
5fafdf24 | 6 | * |
27c7ca7e FB |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | #include <stdio.h> | |
83c9f4ca | 26 | #include "hw/hw.h" |
0d09e41a | 27 | #include "hw/sh4/sh.h" |
9c17d615 | 28 | #include "sysemu/sysemu.h" |
47b43a1f PB |
29 | #include "sh7750_regs.h" |
30 | #include "sh7750_regnames.h" | |
0d09e41a | 31 | #include "hw/sh4/sh_intc.h" |
29e179bc | 32 | #include "cpu.h" |
022c62cb | 33 | #include "exec/address-spaces.h" |
27c7ca7e | 34 | |
27c7ca7e FB |
35 | #define NB_DEVICES 4 |
36 | ||
37 | typedef struct SH7750State { | |
382863e2 BC |
38 | MemoryRegion iomem; |
39 | MemoryRegion iomem_1f0; | |
40 | MemoryRegion iomem_ff0; | |
41 | MemoryRegion iomem_1f8; | |
42 | MemoryRegion iomem_ff8; | |
43 | MemoryRegion iomem_1fc; | |
44 | MemoryRegion iomem_ffc; | |
1a4004c7 | 45 | MemoryRegion mmct_iomem; |
27c7ca7e FB |
46 | /* CPU */ |
47 | CPUSH4State *cpu; | |
48 | /* Peripheral frequency in Hz */ | |
49 | uint32_t periph_freq; | |
50 | /* SDRAM controller */ | |
c2f01775 | 51 | uint32_t bcr1; |
c2432a42 AJ |
52 | uint16_t bcr2; |
53 | uint16_t bcr3; | |
54 | uint32_t bcr4; | |
27c7ca7e | 55 | uint16_t rfcr; |
c2432a42 AJ |
56 | /* PCMCIA controller */ |
57 | uint16_t pcr; | |
27c7ca7e FB |
58 | /* IO ports */ |
59 | uint16_t gpioic; | |
60 | uint32_t pctra; | |
61 | uint32_t pctrb; | |
62 | uint16_t portdira; /* Cached */ | |
63 | uint16_t portpullupa; /* Cached */ | |
64 | uint16_t portdirb; /* Cached */ | |
65 | uint16_t portpullupb; /* Cached */ | |
66 | uint16_t pdtra; | |
67 | uint16_t pdtrb; | |
68 | uint16_t periph_pdtra; /* Imposed by the peripherals */ | |
69 | uint16_t periph_portdira; /* Direction seen from the peripherals */ | |
70 | uint16_t periph_pdtrb; /* Imposed by the peripherals */ | |
71 | uint16_t periph_portdirb; /* Direction seen from the peripherals */ | |
72 | sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ | |
3464c589 | 73 | |
27c7ca7e FB |
74 | /* Cache */ |
75 | uint32_t ccr; | |
27c7ca7e | 76 | |
80f515e6 | 77 | struct intc_desc intc; |
cd1a3f68 | 78 | } SH7750State; |
27c7ca7e | 79 | |
86178a57 | 80 | static inline int has_bcr3_and_bcr4(SH7750State * s) |
c2432a42 AJ |
81 | { |
82 | return (s->cpu->features & SH_FEATURE_BCR3_AND_BCR4); | |
83 | } | |
27c7ca7e FB |
84 | /********************************************************************** |
85 | I/O ports | |
86 | **********************************************************************/ | |
87 | ||
88 | int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device) | |
89 | { | |
90 | int i; | |
91 | ||
92 | for (i = 0; i < NB_DEVICES; i++) { | |
93 | if (s->devices[i] == NULL) { | |
94 | s->devices[i] = device; | |
95 | return 0; | |
96 | } | |
97 | } | |
98 | return -1; | |
99 | } | |
100 | ||
101 | static uint16_t portdir(uint32_t v) | |
102 | { | |
103 | #define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n)) | |
104 | return | |
105 | EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) | | |
106 | EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) | | |
107 | EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) | | |
108 | EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) | | |
109 | EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) | | |
110 | EVENPORTMASK(0); | |
111 | } | |
112 | ||
113 | static uint16_t portpullup(uint32_t v) | |
114 | { | |
115 | #define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n)) | |
116 | return | |
117 | ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) | | |
118 | ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) | | |
119 | ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) | | |
120 | ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) | | |
121 | ODDPORTMASK(1) | ODDPORTMASK(0); | |
122 | } | |
123 | ||
124 | static uint16_t porta_lines(SH7750State * s) | |
125 | { | |
126 | return (s->portdira & s->pdtra) | /* CPU */ | |
127 | (s->periph_portdira & s->periph_pdtra) | /* Peripherals */ | |
128 | (~(s->portdira | s->periph_portdira) & s->portpullupa); /* Pullups */ | |
129 | } | |
130 | ||
131 | static uint16_t portb_lines(SH7750State * s) | |
132 | { | |
133 | return (s->portdirb & s->pdtrb) | /* CPU */ | |
134 | (s->periph_portdirb & s->periph_pdtrb) | /* Peripherals */ | |
135 | (~(s->portdirb | s->periph_portdirb) & s->portpullupb); /* Pullups */ | |
136 | } | |
137 | ||
138 | static void gen_port_interrupts(SH7750State * s) | |
139 | { | |
140 | /* XXXXX interrupts not generated */ | |
141 | } | |
142 | ||
143 | static void porta_changed(SH7750State * s, uint16_t prev) | |
144 | { | |
145 | uint16_t currenta, changes; | |
146 | int i, r = 0; | |
147 | ||
148 | #if 0 | |
149 | fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n", | |
150 | prev, porta_lines(s)); | |
151 | fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra); | |
152 | #endif | |
153 | currenta = porta_lines(s); | |
154 | if (currenta == prev) | |
155 | return; | |
156 | changes = currenta ^ prev; | |
157 | ||
158 | for (i = 0; i < NB_DEVICES; i++) { | |
159 | if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) { | |
160 | r |= s->devices[i]->port_change_cb(currenta, portb_lines(s), | |
161 | &s->periph_pdtra, | |
162 | &s->periph_portdira, | |
163 | &s->periph_pdtrb, | |
164 | &s->periph_portdirb); | |
165 | } | |
166 | } | |
167 | ||
168 | if (r) | |
169 | gen_port_interrupts(s); | |
170 | } | |
171 | ||
172 | static void portb_changed(SH7750State * s, uint16_t prev) | |
173 | { | |
174 | uint16_t currentb, changes; | |
175 | int i, r = 0; | |
176 | ||
177 | currentb = portb_lines(s); | |
178 | if (currentb == prev) | |
179 | return; | |
180 | changes = currentb ^ prev; | |
181 | ||
182 | for (i = 0; i < NB_DEVICES; i++) { | |
183 | if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) { | |
184 | r |= s->devices[i]->port_change_cb(portb_lines(s), currentb, | |
185 | &s->periph_pdtra, | |
186 | &s->periph_portdira, | |
187 | &s->periph_pdtrb, | |
188 | &s->periph_portdirb); | |
189 | } | |
190 | } | |
191 | ||
192 | if (r) | |
193 | gen_port_interrupts(s); | |
194 | } | |
195 | ||
196 | /********************************************************************** | |
197 | Memory | |
198 | **********************************************************************/ | |
199 | ||
a8170e5e | 200 | static void error_access(const char *kind, hwaddr addr) |
27c7ca7e | 201 | { |
526ccb7a | 202 | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n", |
27c7ca7e FB |
203 | kind, regname(addr), addr); |
204 | } | |
205 | ||
a8170e5e | 206 | static void ignore_access(const char *kind, hwaddr addr) |
27c7ca7e | 207 | { |
526ccb7a | 208 | fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n", |
27c7ca7e FB |
209 | kind, regname(addr), addr); |
210 | } | |
211 | ||
a8170e5e | 212 | static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr) |
27c7ca7e | 213 | { |
27c7ca7e | 214 | switch (addr) { |
27c7ca7e FB |
215 | default: |
216 | error_access("byte read", addr); | |
43dc2a64 | 217 | abort(); |
27c7ca7e FB |
218 | } |
219 | } | |
220 | ||
a8170e5e | 221 | static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr) |
27c7ca7e FB |
222 | { |
223 | SH7750State *s = opaque; | |
27c7ca7e FB |
224 | |
225 | switch (addr) { | |
c2f01775 AZ |
226 | case SH7750_BCR2_A7: |
227 | return s->bcr2; | |
c2432a42 AJ |
228 | case SH7750_BCR3_A7: |
229 | if(!has_bcr3_and_bcr4(s)) | |
230 | error_access("word read", addr); | |
231 | return s->bcr3; | |
ed8e0a4d TS |
232 | case SH7750_FRQCR_A7: |
233 | return 0; | |
c2432a42 AJ |
234 | case SH7750_PCR_A7: |
235 | return s->pcr; | |
27c7ca7e FB |
236 | case SH7750_RFCR_A7: |
237 | fprintf(stderr, | |
238 | "Read access to refresh count register, incrementing\n"); | |
239 | return s->rfcr++; | |
27c7ca7e FB |
240 | case SH7750_PDTRA_A7: |
241 | return porta_lines(s); | |
242 | case SH7750_PDTRB_A7: | |
243 | return portb_lines(s); | |
c2432a42 AJ |
244 | case SH7750_RTCOR_A7: |
245 | case SH7750_RTCNT_A7: | |
246 | case SH7750_RTCSR_A7: | |
247 | ignore_access("word read", addr); | |
248 | return 0; | |
27c7ca7e FB |
249 | default: |
250 | error_access("word read", addr); | |
43dc2a64 | 251 | abort(); |
27c7ca7e FB |
252 | } |
253 | } | |
254 | ||
a8170e5e | 255 | static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr) |
27c7ca7e FB |
256 | { |
257 | SH7750State *s = opaque; | |
b350ab75 | 258 | SuperHCPUClass *scc; |
27c7ca7e FB |
259 | |
260 | switch (addr) { | |
c2f01775 AZ |
261 | case SH7750_BCR1_A7: |
262 | return s->bcr1; | |
263 | case SH7750_BCR4_A7: | |
c2432a42 AJ |
264 | if(!has_bcr3_and_bcr4(s)) |
265 | error_access("long read", addr); | |
266 | return s->bcr4; | |
c2f01775 AZ |
267 | case SH7750_WCR1_A7: |
268 | case SH7750_WCR2_A7: | |
269 | case SH7750_WCR3_A7: | |
270 | case SH7750_MCR_A7: | |
271 | ignore_access("long read", addr); | |
272 | return 0; | |
27c7ca7e FB |
273 | case SH7750_MMUCR_A7: |
274 | return s->cpu->mmucr; | |
275 | case SH7750_PTEH_A7: | |
276 | return s->cpu->pteh; | |
277 | case SH7750_PTEL_A7: | |
278 | return s->cpu->ptel; | |
279 | case SH7750_TTB_A7: | |
280 | return s->cpu->ttb; | |
281 | case SH7750_TEA_A7: | |
282 | return s->cpu->tea; | |
283 | case SH7750_TRA_A7: | |
284 | return s->cpu->tra; | |
285 | case SH7750_EXPEVT_A7: | |
286 | return s->cpu->expevt; | |
287 | case SH7750_INTEVT_A7: | |
288 | return s->cpu->intevt; | |
289 | case SH7750_CCR_A7: | |
290 | return s->ccr; | |
0fd3ca30 | 291 | case 0x1f000030: /* Processor version */ |
b350ab75 AF |
292 | scc = SUPERH_CPU_GET_CLASS(s->cpu); |
293 | return scc->pvr; | |
0fd3ca30 | 294 | case 0x1f000040: /* Cache version */ |
b350ab75 AF |
295 | scc = SUPERH_CPU_GET_CLASS(s->cpu); |
296 | return scc->cvr; | |
0fd3ca30 | 297 | case 0x1f000044: /* Processor revision */ |
b350ab75 AF |
298 | scc = SUPERH_CPU_GET_CLASS(s->cpu); |
299 | return scc->prr; | |
27c7ca7e FB |
300 | default: |
301 | error_access("long read", addr); | |
43dc2a64 | 302 | abort(); |
27c7ca7e FB |
303 | } |
304 | } | |
305 | ||
c2432a42 AJ |
306 | #define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \ |
307 | && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB)) | |
a8170e5e | 308 | static void sh7750_mem_writeb(void *opaque, hwaddr addr, |
27c7ca7e FB |
309 | uint32_t mem_value) |
310 | { | |
c2432a42 AJ |
311 | |
312 | if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) { | |
27c7ca7e FB |
313 | ignore_access("byte write", addr); |
314 | return; | |
27c7ca7e | 315 | } |
c2432a42 AJ |
316 | |
317 | error_access("byte write", addr); | |
43dc2a64 | 318 | abort(); |
27c7ca7e FB |
319 | } |
320 | ||
a8170e5e | 321 | static void sh7750_mem_writew(void *opaque, hwaddr addr, |
27c7ca7e FB |
322 | uint32_t mem_value) |
323 | { | |
324 | SH7750State *s = opaque; | |
325 | uint16_t temp; | |
326 | ||
327 | switch (addr) { | |
328 | /* SDRAM controller */ | |
27c7ca7e | 329 | case SH7750_BCR2_A7: |
c2f01775 AZ |
330 | s->bcr2 = mem_value; |
331 | return; | |
27c7ca7e | 332 | case SH7750_BCR3_A7: |
c2432a42 AJ |
333 | if(!has_bcr3_and_bcr4(s)) |
334 | error_access("word write", addr); | |
335 | s->bcr3 = mem_value; | |
336 | return; | |
337 | case SH7750_PCR_A7: | |
338 | s->pcr = mem_value; | |
339 | return; | |
27c7ca7e | 340 | case SH7750_RTCNT_A7: |
c2432a42 | 341 | case SH7750_RTCOR_A7: |
27c7ca7e FB |
342 | case SH7750_RTCSR_A7: |
343 | ignore_access("word write", addr); | |
344 | return; | |
345 | /* IO ports */ | |
346 | case SH7750_PDTRA_A7: | |
347 | temp = porta_lines(s); | |
348 | s->pdtra = mem_value; | |
349 | porta_changed(s, temp); | |
350 | return; | |
351 | case SH7750_PDTRB_A7: | |
352 | temp = portb_lines(s); | |
353 | s->pdtrb = mem_value; | |
354 | portb_changed(s, temp); | |
355 | return; | |
356 | case SH7750_RFCR_A7: | |
357 | fprintf(stderr, "Write access to refresh count register\n"); | |
358 | s->rfcr = mem_value; | |
359 | return; | |
27c7ca7e FB |
360 | case SH7750_GPIOIC_A7: |
361 | s->gpioic = mem_value; | |
362 | if (mem_value != 0) { | |
363 | fprintf(stderr, "I/O interrupts not implemented\n"); | |
43dc2a64 | 364 | abort(); |
27c7ca7e FB |
365 | } |
366 | return; | |
367 | default: | |
368 | error_access("word write", addr); | |
43dc2a64 | 369 | abort(); |
27c7ca7e FB |
370 | } |
371 | } | |
372 | ||
a8170e5e | 373 | static void sh7750_mem_writel(void *opaque, hwaddr addr, |
27c7ca7e FB |
374 | uint32_t mem_value) |
375 | { | |
376 | SH7750State *s = opaque; | |
377 | uint16_t temp; | |
378 | ||
379 | switch (addr) { | |
380 | /* SDRAM controller */ | |
381 | case SH7750_BCR1_A7: | |
c2f01775 AZ |
382 | s->bcr1 = mem_value; |
383 | return; | |
27c7ca7e | 384 | case SH7750_BCR4_A7: |
c2432a42 AJ |
385 | if(!has_bcr3_and_bcr4(s)) |
386 | error_access("long write", addr); | |
387 | s->bcr4 = mem_value; | |
388 | return; | |
27c7ca7e FB |
389 | case SH7750_WCR1_A7: |
390 | case SH7750_WCR2_A7: | |
391 | case SH7750_WCR3_A7: | |
392 | case SH7750_MCR_A7: | |
393 | ignore_access("long write", addr); | |
394 | return; | |
395 | /* IO ports */ | |
396 | case SH7750_PCTRA_A7: | |
397 | temp = porta_lines(s); | |
398 | s->pctra = mem_value; | |
399 | s->portdira = portdir(mem_value); | |
400 | s->portpullupa = portpullup(mem_value); | |
401 | porta_changed(s, temp); | |
402 | return; | |
403 | case SH7750_PCTRB_A7: | |
404 | temp = portb_lines(s); | |
405 | s->pctrb = mem_value; | |
406 | s->portdirb = portdir(mem_value); | |
407 | s->portpullupb = portpullup(mem_value); | |
408 | portb_changed(s, temp); | |
409 | return; | |
27c7ca7e | 410 | case SH7750_MMUCR_A7: |
e0bcb9ca AJ |
411 | if (mem_value & MMUCR_TI) { |
412 | cpu_sh4_invalidate_tlb(s->cpu); | |
413 | } | |
414 | s->cpu->mmucr = mem_value & ~MMUCR_TI; | |
415 | return; | |
27c7ca7e | 416 | case SH7750_PTEH_A7: |
06afe2c8 AJ |
417 | /* If asid changes, clear all registered tlb entries. */ |
418 | if ((s->cpu->pteh & 0xff) != (mem_value & 0xff)) | |
419 | tlb_flush(s->cpu, 1); | |
27c7ca7e FB |
420 | s->cpu->pteh = mem_value; |
421 | return; | |
422 | case SH7750_PTEL_A7: | |
423 | s->cpu->ptel = mem_value; | |
424 | return; | |
ea2b542a AJ |
425 | case SH7750_PTEA_A7: |
426 | s->cpu->ptea = mem_value & 0x0000000f; | |
427 | return; | |
27c7ca7e FB |
428 | case SH7750_TTB_A7: |
429 | s->cpu->ttb = mem_value; | |
430 | return; | |
431 | case SH7750_TEA_A7: | |
432 | s->cpu->tea = mem_value; | |
433 | return; | |
434 | case SH7750_TRA_A7: | |
435 | s->cpu->tra = mem_value & 0x000007ff; | |
436 | return; | |
437 | case SH7750_EXPEVT_A7: | |
438 | s->cpu->expevt = mem_value & 0x000007ff; | |
439 | return; | |
440 | case SH7750_INTEVT_A7: | |
441 | s->cpu->intevt = mem_value & 0x000007ff; | |
442 | return; | |
443 | case SH7750_CCR_A7: | |
444 | s->ccr = mem_value; | |
445 | return; | |
446 | default: | |
447 | error_access("long write", addr); | |
43dc2a64 | 448 | abort(); |
27c7ca7e FB |
449 | } |
450 | } | |
451 | ||
382863e2 BC |
452 | static const MemoryRegionOps sh7750_mem_ops = { |
453 | .old_mmio = { | |
454 | .read = {sh7750_mem_readb, | |
455 | sh7750_mem_readw, | |
456 | sh7750_mem_readl }, | |
457 | .write = {sh7750_mem_writeb, | |
458 | sh7750_mem_writew, | |
459 | sh7750_mem_writel }, | |
460 | }, | |
461 | .endianness = DEVICE_NATIVE_ENDIAN, | |
27c7ca7e FB |
462 | }; |
463 | ||
80f515e6 AZ |
464 | /* sh775x interrupt controller tables for sh_intc.c |
465 | * stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c | |
466 | */ | |
467 | ||
468 | enum { | |
469 | UNUSED = 0, | |
470 | ||
471 | /* interrupt sources */ | |
c6d86a33 AZ |
472 | IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7, |
473 | IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E, | |
474 | IRL0, IRL1, IRL2, IRL3, | |
80f515e6 AZ |
475 | HUDI, GPIOI, |
476 | DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3, | |
477 | DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7, | |
478 | DMAC_DMAE, | |
479 | PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | |
480 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3, | |
481 | TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI, | |
482 | RTC_ATI, RTC_PRI, RTC_CUI, | |
483 | SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI, | |
484 | SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI, | |
485 | WDT, | |
486 | REF_RCMI, REF_ROVI, | |
487 | ||
488 | /* interrupt groups */ | |
489 | DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF, | |
c6d86a33 AZ |
490 | /* irl bundle */ |
491 | IRL, | |
80f515e6 AZ |
492 | |
493 | NR_SOURCES, | |
494 | }; | |
495 | ||
496 | static struct intc_vect vectors[] = { | |
497 | INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620), | |
498 | INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420), | |
499 | INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460), | |
500 | INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0), | |
501 | INTC_VECT(RTC_CUI, 0x4c0), | |
502 | INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500), | |
503 | INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540), | |
504 | INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720), | |
505 | INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760), | |
506 | INTC_VECT(WDT, 0x560), | |
507 | INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0), | |
508 | }; | |
509 | ||
510 | static struct intc_group groups[] = { | |
511 | INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI), | |
512 | INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI), | |
513 | INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI), | |
514 | INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI), | |
515 | INTC_GROUP(REF, REF_RCMI, REF_ROVI), | |
516 | }; | |
517 | ||
518 | static struct intc_prio_reg prio_registers[] = { | |
519 | { 0xffd00004, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } }, | |
520 | { 0xffd00008, 0, 16, 4, /* IPRB */ { WDT, REF, SCI1, 0 } }, | |
521 | { 0xffd0000c, 0, 16, 4, /* IPRC */ { GPIOI, DMAC, SCIF, HUDI } }, | |
522 | { 0xffd00010, 0, 16, 4, /* IPRD */ { IRL0, IRL1, IRL2, IRL3 } }, | |
523 | { 0xfe080000, 0, 32, 4, /* INTPRI00 */ { 0, 0, 0, 0, | |
524 | TMU4, TMU3, | |
525 | PCIC1, PCIC0_PCISERR } }, | |
526 | }; | |
527 | ||
528 | /* SH7750, SH7750S, SH7751 and SH7091 all have 4-channel DMA controllers */ | |
529 | ||
530 | static struct intc_vect vectors_dma4[] = { | |
531 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | |
532 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | |
533 | INTC_VECT(DMAC_DMAE, 0x6c0), | |
534 | }; | |
535 | ||
536 | static struct intc_group groups_dma4[] = { | |
537 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | |
538 | DMAC_DMTE3, DMAC_DMAE), | |
539 | }; | |
540 | ||
541 | /* SH7750R and SH7751R both have 8-channel DMA controllers */ | |
542 | ||
543 | static struct intc_vect vectors_dma8[] = { | |
544 | INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660), | |
545 | INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0), | |
546 | INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0), | |
547 | INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0), | |
548 | INTC_VECT(DMAC_DMAE, 0x6c0), | |
549 | }; | |
550 | ||
551 | static struct intc_group groups_dma8[] = { | |
552 | INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, | |
553 | DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5, | |
554 | DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE), | |
555 | }; | |
556 | ||
557 | /* SH7750R, SH7751 and SH7751R all have two extra timer channels */ | |
558 | ||
559 | static struct intc_vect vectors_tmu34[] = { | |
560 | INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80), | |
561 | }; | |
562 | ||
563 | static struct intc_mask_reg mask_registers[] = { | |
564 | { 0xfe080040, 0xfe080060, 32, /* INTMSK00 / INTMSKCLR00 */ | |
565 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, | |
566 | 0, 0, 0, 0, 0, 0, TMU4, TMU3, | |
567 | PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | |
568 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, | |
569 | PCIC1_PCIDMA3, PCIC0_PCISERR } }, | |
570 | }; | |
571 | ||
572 | /* SH7750S, SH7750R, SH7751 and SH7751R all have IRLM priority registers */ | |
573 | ||
574 | static struct intc_vect vectors_irlm[] = { | |
575 | INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0), | |
576 | INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360), | |
577 | }; | |
578 | ||
579 | /* SH7751 and SH7751R both have PCI */ | |
580 | ||
581 | static struct intc_vect vectors_pci[] = { | |
582 | INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0), | |
583 | INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0), | |
584 | INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60), | |
585 | INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20), | |
586 | }; | |
587 | ||
588 | static struct intc_group groups_pci[] = { | |
589 | INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON, | |
590 | PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3), | |
591 | }; | |
592 | ||
c6d86a33 AZ |
593 | static struct intc_vect vectors_irl[] = { |
594 | INTC_VECT(IRL_0, 0x200), | |
595 | INTC_VECT(IRL_1, 0x220), | |
596 | INTC_VECT(IRL_2, 0x240), | |
597 | INTC_VECT(IRL_3, 0x260), | |
598 | INTC_VECT(IRL_4, 0x280), | |
599 | INTC_VECT(IRL_5, 0x2a0), | |
600 | INTC_VECT(IRL_6, 0x2c0), | |
601 | INTC_VECT(IRL_7, 0x2e0), | |
602 | INTC_VECT(IRL_8, 0x300), | |
603 | INTC_VECT(IRL_9, 0x320), | |
604 | INTC_VECT(IRL_A, 0x340), | |
605 | INTC_VECT(IRL_B, 0x360), | |
606 | INTC_VECT(IRL_C, 0x380), | |
607 | INTC_VECT(IRL_D, 0x3a0), | |
608 | INTC_VECT(IRL_E, 0x3c0), | |
609 | }; | |
610 | ||
611 | static struct intc_group groups_irl[] = { | |
612 | INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, | |
613 | IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E), | |
614 | }; | |
615 | ||
29e179bc AJ |
616 | /********************************************************************** |
617 | Memory mapped cache and TLB | |
618 | **********************************************************************/ | |
619 | ||
620 | #define MM_REGION_MASK 0x07000000 | |
621 | #define MM_ICACHE_ADDR (0) | |
622 | #define MM_ICACHE_DATA (1) | |
623 | #define MM_ITLB_ADDR (2) | |
624 | #define MM_ITLB_DATA (3) | |
625 | #define MM_OCACHE_ADDR (4) | |
626 | #define MM_OCACHE_DATA (5) | |
627 | #define MM_UTLB_ADDR (6) | |
628 | #define MM_UTLB_DATA (7) | |
629 | #define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24) | |
630 | ||
a8170e5e | 631 | static uint64_t invalid_read(void *opaque, hwaddr addr) |
29e179bc | 632 | { |
43dc2a64 | 633 | abort(); |
29e179bc AJ |
634 | |
635 | return 0; | |
636 | } | |
637 | ||
a8170e5e | 638 | static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr, |
1a4004c7 | 639 | unsigned size) |
29e179bc | 640 | { |
bc656a29 | 641 | SH7750State *s = opaque; |
29e179bc AJ |
642 | uint32_t ret = 0; |
643 | ||
1a4004c7 BC |
644 | if (size != 4) { |
645 | return invalid_read(opaque, addr); | |
646 | } | |
647 | ||
29e179bc AJ |
648 | switch (MM_REGION_TYPE(addr)) { |
649 | case MM_ICACHE_ADDR: | |
650 | case MM_ICACHE_DATA: | |
651 | /* do nothing */ | |
652 | break; | |
653 | case MM_ITLB_ADDR: | |
bc656a29 AJ |
654 | ret = cpu_sh4_read_mmaped_itlb_addr(s->cpu, addr); |
655 | break; | |
29e179bc | 656 | case MM_ITLB_DATA: |
bc656a29 AJ |
657 | ret = cpu_sh4_read_mmaped_itlb_data(s->cpu, addr); |
658 | break; | |
29e179bc AJ |
659 | case MM_OCACHE_ADDR: |
660 | case MM_OCACHE_DATA: | |
661 | /* do nothing */ | |
662 | break; | |
663 | case MM_UTLB_ADDR: | |
bc656a29 AJ |
664 | ret = cpu_sh4_read_mmaped_utlb_addr(s->cpu, addr); |
665 | break; | |
29e179bc | 666 | case MM_UTLB_DATA: |
bc656a29 AJ |
667 | ret = cpu_sh4_read_mmaped_utlb_data(s->cpu, addr); |
668 | break; | |
29e179bc | 669 | default: |
43dc2a64 | 670 | abort(); |
29e179bc AJ |
671 | } |
672 | ||
673 | return ret; | |
674 | } | |
675 | ||
a8170e5e | 676 | static void invalid_write(void *opaque, hwaddr addr, |
1a4004c7 | 677 | uint64_t mem_value) |
29e179bc | 678 | { |
43dc2a64 | 679 | abort(); |
29e179bc AJ |
680 | } |
681 | ||
a8170e5e | 682 | static void sh7750_mmct_write(void *opaque, hwaddr addr, |
1a4004c7 | 683 | uint64_t mem_value, unsigned size) |
29e179bc AJ |
684 | { |
685 | SH7750State *s = opaque; | |
686 | ||
1a4004c7 BC |
687 | if (size != 4) { |
688 | invalid_write(opaque, addr, mem_value); | |
689 | } | |
690 | ||
29e179bc AJ |
691 | switch (MM_REGION_TYPE(addr)) { |
692 | case MM_ICACHE_ADDR: | |
693 | case MM_ICACHE_DATA: | |
694 | /* do nothing */ | |
695 | break; | |
696 | case MM_ITLB_ADDR: | |
c0f809c4 AJ |
697 | cpu_sh4_write_mmaped_itlb_addr(s->cpu, addr, mem_value); |
698 | break; | |
29e179bc | 699 | case MM_ITLB_DATA: |
9f97309a | 700 | cpu_sh4_write_mmaped_itlb_data(s->cpu, addr, mem_value); |
43dc2a64 | 701 | abort(); |
29e179bc AJ |
702 | break; |
703 | case MM_OCACHE_ADDR: | |
704 | case MM_OCACHE_DATA: | |
705 | /* do nothing */ | |
706 | break; | |
707 | case MM_UTLB_ADDR: | |
708 | cpu_sh4_write_mmaped_utlb_addr(s->cpu, addr, mem_value); | |
709 | break; | |
710 | case MM_UTLB_DATA: | |
9f97309a | 711 | cpu_sh4_write_mmaped_utlb_data(s->cpu, addr, mem_value); |
29e179bc AJ |
712 | break; |
713 | default: | |
43dc2a64 | 714 | abort(); |
29e179bc AJ |
715 | break; |
716 | } | |
717 | } | |
718 | ||
12f30833 | 719 | static const MemoryRegionOps sh7750_mmct_ops = { |
1a4004c7 BC |
720 | .read = sh7750_mmct_read, |
721 | .write = sh7750_mmct_write, | |
722 | .endianness = DEVICE_NATIVE_ENDIAN, | |
29e179bc AJ |
723 | }; |
724 | ||
382863e2 | 725 | SH7750State *sh7750_init(CPUSH4State * cpu, MemoryRegion *sysmem) |
27c7ca7e FB |
726 | { |
727 | SH7750State *s; | |
27c7ca7e | 728 | |
7267c094 | 729 | s = g_malloc0(sizeof(SH7750State)); |
27c7ca7e FB |
730 | s->cpu = cpu; |
731 | s->periph_freq = 60000000; /* 60MHz */ | |
382863e2 BC |
732 | memory_region_init_io(&s->iomem, &sh7750_mem_ops, s, |
733 | "memory", 0x1fc01000); | |
734 | ||
735 | memory_region_init_alias(&s->iomem_1f0, "memory-1f0", | |
736 | &s->iomem, 0x1f000000, 0x1000); | |
737 | memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0); | |
738 | ||
739 | memory_region_init_alias(&s->iomem_ff0, "memory-ff0", | |
740 | &s->iomem, 0x1f000000, 0x1000); | |
741 | memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0); | |
742 | ||
743 | memory_region_init_alias(&s->iomem_1f8, "memory-1f8", | |
744 | &s->iomem, 0x1f800000, 0x1000); | |
745 | memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8); | |
746 | ||
747 | memory_region_init_alias(&s->iomem_ff8, "memory-ff8", | |
748 | &s->iomem, 0x1f800000, 0x1000); | |
749 | memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8); | |
750 | ||
751 | memory_region_init_alias(&s->iomem_1fc, "memory-1fc", | |
752 | &s->iomem, 0x1fc00000, 0x1000); | |
753 | memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc); | |
754 | ||
755 | memory_region_init_alias(&s->iomem_ffc, "memory-ffc", | |
756 | &s->iomem, 0x1fc00000, 0x1000); | |
757 | memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc); | |
2f062c72 | 758 | |
1a4004c7 BC |
759 | memory_region_init_io(&s->mmct_iomem, &sh7750_mmct_ops, s, |
760 | "cache-and-tlb", 0x08000000); | |
761 | memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem); | |
29e179bc | 762 | |
b279e5ef | 763 | sh_intc_init(sysmem, &s->intc, NR_SOURCES, |
80f515e6 AZ |
764 | _INTC_ARRAY(mask_registers), |
765 | _INTC_ARRAY(prio_registers)); | |
766 | ||
0fd3ca30 | 767 | sh_intc_register_sources(&s->intc, |
80f515e6 AZ |
768 | _INTC_ARRAY(vectors), |
769 | _INTC_ARRAY(groups)); | |
770 | ||
e96e2044 TS |
771 | cpu->intc_handle = &s->intc; |
772 | ||
9a9d0b81 BC |
773 | sh_serial_init(sysmem, 0x1fe00000, |
774 | 0, s->periph_freq, serial_hds[0], | |
775 | s->intc.irqs[SCI1_ERI], | |
776 | s->intc.irqs[SCI1_RXI], | |
777 | s->intc.irqs[SCI1_TXI], | |
778 | s->intc.irqs[SCI1_TEI], | |
779 | NULL); | |
780 | sh_serial_init(sysmem, 0x1fe80000, | |
781 | SH_SERIAL_FEAT_SCIF, | |
782 | s->periph_freq, serial_hds[1], | |
783 | s->intc.irqs[SCIF_ERI], | |
784 | s->intc.irqs[SCIF_RXI], | |
785 | s->intc.irqs[SCIF_TXI], | |
786 | NULL, | |
787 | s->intc.irqs[SCIF_BRI]); | |
cd1a3f68 | 788 | |
89e29451 | 789 | tmu012_init(sysmem, 0x1fd80000, |
cd1a3f68 | 790 | TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK, |
703243a0 | 791 | s->periph_freq, |
96e2fc41 AJ |
792 | s->intc.irqs[TMU0], |
793 | s->intc.irqs[TMU1], | |
794 | s->intc.irqs[TMU2_TUNI], | |
795 | s->intc.irqs[TMU2_TICPI]); | |
80f515e6 | 796 | |
0fd3ca30 AJ |
797 | if (cpu->id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) { |
798 | sh_intc_register_sources(&s->intc, | |
80f515e6 AZ |
799 | _INTC_ARRAY(vectors_dma4), |
800 | _INTC_ARRAY(groups_dma4)); | |
801 | } | |
802 | ||
0fd3ca30 AJ |
803 | if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) { |
804 | sh_intc_register_sources(&s->intc, | |
80f515e6 AZ |
805 | _INTC_ARRAY(vectors_dma8), |
806 | _INTC_ARRAY(groups_dma8)); | |
807 | } | |
808 | ||
0fd3ca30 AJ |
809 | if (cpu->id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) { |
810 | sh_intc_register_sources(&s->intc, | |
80f515e6 | 811 | _INTC_ARRAY(vectors_tmu34), |
f26ae302 | 812 | NULL, 0); |
89e29451 | 813 | tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq, |
96e2fc41 AJ |
814 | s->intc.irqs[TMU3], |
815 | s->intc.irqs[TMU4], | |
703243a0 | 816 | NULL, NULL); |
80f515e6 AZ |
817 | } |
818 | ||
0fd3ca30 AJ |
819 | if (cpu->id & (SH_CPU_SH7751_ALL)) { |
820 | sh_intc_register_sources(&s->intc, | |
80f515e6 AZ |
821 | _INTC_ARRAY(vectors_pci), |
822 | _INTC_ARRAY(groups_pci)); | |
823 | } | |
824 | ||
0fd3ca30 AJ |
825 | if (cpu->id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) { |
826 | sh_intc_register_sources(&s->intc, | |
80f515e6 | 827 | _INTC_ARRAY(vectors_irlm), |
f26ae302 | 828 | NULL, 0); |
80f515e6 AZ |
829 | } |
830 | ||
c6d86a33 AZ |
831 | sh_intc_register_sources(&s->intc, |
832 | _INTC_ARRAY(vectors_irl), | |
833 | _INTC_ARRAY(groups_irl)); | |
27c7ca7e FB |
834 | return s; |
835 | } | |
c6d86a33 AZ |
836 | |
837 | qemu_irq sh7750_irl(SH7750State *s) | |
838 | { | |
839 | sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */ | |
840 | return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), | |
841 | 1)[0]; | |
842 | } |