[mirror_qemu.git] / hw / slavio_intctl.c

/*
 * QEMU Sparc SLAVIO interrupt controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"
//#define DEBUG_IRQ_COUNT
//#define DEBUG_IRQ

#ifdef DEBUG_IRQ
#define DPRINTF(fmt, args...) \
do { printf("IRQ: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of interrupt controller in sun4m.
 *
 * This is the interrupt controller part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * There is a system master controller and one for each cpu.
 *
 */

#define MAX_CPUS 16
#define MAX_PILS 16

typedef struct SLAVIO_INTCTLState {
    uint32_t intreg_pending[MAX_CPUS];
    uint32_t intregm_pending;
    uint32_t intregm_disabled;
    uint32_t target_cpu;
#ifdef DEBUG_IRQ_COUNT
    uint64_t irq_count[32];
#endif
    qemu_irq *cpu_irqs[MAX_CPUS];
    const uint32_t *intbit_to_level;
    uint32_t cputimer_bit;
    uint32_t pil_out[MAX_CPUS];
} SLAVIO_INTCTLState;

#define INTCTL_MAXADDR 0xf
#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
#define INTCTLM_MAXADDR 0x13
#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
#define INTCTLM_MASK 0x1f
static void slavio_check_interrupts(void *opaque);

// per-cpu interrupt controller
static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr, ret;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
        ret = s->intreg_pending[cpu];
        break;
    default:
        ret = 0;
        break;
    }
    DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);

    return ret;
}

static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;
    int cpu;

    cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
    saddr = (addr & INTCTL_MAXADDR) >> 2;
    DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
    switch (saddr) {
    case 1: // clear pending softints
	if (val & 0x4000)
	    val |= 80000000;
	val &= 0xfffe0000;
	s->intreg_pending[cpu] &= ~val;
        slavio_check_interrupts(s);
	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    case 2: // set softint
	val &= 0xfffe0000;
	s->intreg_pending[cpu] |= val;
        slavio_check_interrupts(s);
	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
    slavio_intctl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
    slavio_intctl_mem_writel,
};

// master system interrupt controller
static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr, ret;

    saddr = (addr & INTCTLM_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
        ret = s->intregm_pending & 0x7fffffff;
        break;
    case 1:
        ret = s->intregm_disabled;
        break;
    case 4:
        ret = s->target_cpu;
        break;
    default:
        ret = 0;
        break;
    }
    DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);

    return ret;
}

static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t saddr;

    saddr = (addr & INTCTLM_MASK) >> 2;
    DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
    switch (saddr) {
    case 2: // clear (enable)
	// Force clear unused bits
	val &= ~0x4fb2007f;
	s->intregm_disabled &= ~val;
	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	slavio_check_interrupts(s);
	break;
    case 3: // set (disable, clear pending)
	// Force clear unused bits
	val &= ~0x4fb2007f;
	s->intregm_disabled |= val;
	s->intregm_pending &= ~val;
        slavio_check_interrupts(s);
	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
	break;
    case 4:
	s->target_cpu = val & (MAX_CPUS - 1);
        slavio_check_interrupts(s);
	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
	break;
    default:
	break;
    }
}

static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
    slavio_intctlm_mem_readl,
};

static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
    slavio_intctlm_mem_writel,
};

void slavio_pic_info(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
    }
    term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
}

void slavio_irq_info(void *opaque)
{
#ifndef DEBUG_IRQ_COUNT
    term_printf("irq statistic code not compiled.\n");
#else
    SLAVIO_INTCTLState *s = opaque;
    int i;
    int64_t count;

    term_printf("IRQ statistics:\n");
    for (i = 0; i < 32; i++) {
        count = s->irq_count[i];
        if (count > 0)
            term_printf("%2d: %" PRId64 "\n", i, count);
    }
#endif
}

static void slavio_check_interrupts(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t pending = s->intregm_pending, pil_pending;
    unsigned int i, j;

    pending &= ~s->intregm_disabled;

    DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
    for (i = 0; i < MAX_CPUS; i++) {
        pil_pending = 0;
        if (pending && !(s->intregm_disabled & 0x80000000) &&
            (i == s->target_cpu)) {
            for (j = 0; j < 32; j++) {
                if (pending & (1 << j))
                    pil_pending |= 1 << s->intbit_to_level[j];
            }
        }
        pil_pending |= (s->intreg_pending[i] >> 16) & 0xfffe;

        for (j = 0; j < MAX_PILS; j++) {
            if (pil_pending & (1 << j)) {
                if (!(s->pil_out[i] & (1 << j)))
                    qemu_irq_raise(s->cpu_irqs[i][j]);
            } else {
                if (s->pil_out[i] & (1 << j))
                    qemu_irq_lower(s->cpu_irqs[i][j]);
            }
        }
        s->pil_out[i] = pil_pending;
    }
}

/*
 * "irq" here is the bit number in the system interrupt register to
 * separate serial and keyboard interrupts sharing a level.
 */
static void slavio_set_irq(void *opaque, int irq, int level)
{
    SLAVIO_INTCTLState *s = opaque;
    uint32_t mask = 1 << irq;
    uint32_t pil = s->intbit_to_level[irq];

    DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
            level);
    if (pil > 0) {
        if (level) {
#ifdef DEBUG_IRQ_COUNT
            s->irq_count[pil]++;
#endif
            s->intregm_pending |= mask;
            s->intreg_pending[s->target_cpu] |= 1 << pil;
        } else {
            s->intregm_pending &= ~mask;
            s->intreg_pending[s->target_cpu] &= ~(1 << pil);
        }
        slavio_check_interrupts(s);
    }
}

static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
{
    SLAVIO_INTCTLState *s = opaque;

    DPRINTF("Set cpu %d local timer level %d\n", cpu, level);

    if (level)
        s->intreg_pending[cpu] |= s->cputimer_bit;
    else
        s->intreg_pending[cpu] &= ~s->cputimer_bit;

    slavio_check_interrupts(s);
}

static void slavio_intctl_save(QEMUFile *f, void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;
   
    for (i = 0; i < MAX_CPUS; i++) {
	qemu_put_be32s(f, &s->intreg_pending[i]);
    }
    qemu_put_be32s(f, &s->intregm_pending);
    qemu_put_be32s(f, &s->intregm_disabled);
    qemu_put_be32s(f, &s->target_cpu);
}

static int slavio_intctl_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    if (version_id != 1)
        return -EINVAL;

    for (i = 0; i < MAX_CPUS; i++) {
	qemu_get_be32s(f, &s->intreg_pending[i]);
    }
    qemu_get_be32s(f, &s->intregm_pending);
    qemu_get_be32s(f, &s->intregm_disabled);
    qemu_get_be32s(f, &s->target_cpu);
    slavio_check_interrupts(s);
    return 0;
}

static void slavio_intctl_reset(void *opaque)
{
    SLAVIO_INTCTLState *s = opaque;
    int i;

    for (i = 0; i < MAX_CPUS; i++) {
	s->intreg_pending[i] = 0;
    }
    s->intregm_disabled = ~0xffb2007f;
    s->intregm_pending = 0;
    s->target_cpu = 0;
    slavio_check_interrupts(s);
}

void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
                         const uint32_t *intbit_to_level,
                         qemu_irq **irq, qemu_irq **cpu_irq,
                         qemu_irq **parent_irq, unsigned int cputimer)
{
    int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
    SLAVIO_INTCTLState *s;

    s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
    if (!s)
        return NULL;

    s->intbit_to_level = intbit_to_level;
    for (i = 0; i < MAX_CPUS; i++) {
	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
                                     slavio_intctl_io_memory);
        s->cpu_irqs[i] = parent_irq[i];
    }

    slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
    cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);

    register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
    qemu_register_reset(slavio_intctl_reset, s);
    *irq = qemu_allocate_irqs(slavio_set_irq, s, 32);

    *cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
    s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
    slavio_intctl_reset(s);
    return s;
}
Commit	Line	Data
e80cfcfc FB	1	/*
e80cfcfc FB	2	* QEMU Sparc SLAVIO interrupt controller emulation
5fafdf24	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25	//#define DEBUG_IRQ_COUNT
66321a11 FB	26	//#define DEBUG_IRQ
	27
	28	#ifdef DEBUG_IRQ
	29	#define DPRINTF(fmt, args...) \
	30	do { printf("IRQ: " fmt , ##args); } while (0)
	31	#else
	32	#define DPRINTF(fmt, args...)
	33	#endif
e80cfcfc FB	34
	35	/*
	36	* Registers of interrupt controller in sun4m.
	37	*
	38	* This is the interrupt controller part of chip STP2001 (Slave I/O), also
	39	* produced as NCR89C105. See
	40	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	41	*
	42	* There is a system master controller and one for each cpu.
5fafdf24	43	*
e80cfcfc FB	44	*/
	45
	46	#define MAX_CPUS 16
b3a23197	47	#define MAX_PILS 16
e80cfcfc FB	48
	49	typedef struct SLAVIO_INTCTLState {
	50	uint32_t intreg_pending[MAX_CPUS];
	51	uint32_t intregm_pending;
	52	uint32_t intregm_disabled;
	53	uint32_t target_cpu;
	54	#ifdef DEBUG_IRQ_COUNT
	55	uint64_t irq_count[32];
	56	#endif
b3a23197	57	qemu_irq *cpu_irqs[MAX_CPUS];
e0353fe2	58	const uint32_t *intbit_to_level;
d7edfd27	59	uint32_t cputimer_bit;
b3a23197	60	uint32_t pil_out[MAX_CPUS];
e80cfcfc FB	61	} SLAVIO_INTCTLState;
	62
	63	#define INTCTL_MAXADDR 0xf
5aca8c3b	64	#define INTCTL_SIZE (INTCTL_MAXADDR + 1)
c6fdf5fc	65	#define INTCTLM_MAXADDR 0x13
5aca8c3b	66	#define INTCTLM_SIZE (INTCTLM_MAXADDR + 1)
c6fdf5fc	67	#define INTCTLM_MASK 0x1f
66321a11	68	static void slavio_check_interrupts(void *opaque);
e80cfcfc FB	69
	70	// per-cpu interrupt controller
	71	static uint32_t slavio_intctl_mem_readl(void *opaque, target_phys_addr_t addr)
	72	{
	73	SLAVIO_INTCTLState *s = opaque;
dd4131b3	74	uint32_t saddr, ret;
e80cfcfc FB	75	int cpu;
	76
	77	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	78	saddr = (addr & INTCTL_MAXADDR) >> 2;
	79	switch (saddr) {
	80	case 0:
dd4131b3 BS	81	ret = s->intreg_pending[cpu];
dd4131b3 BS	82	break;
e80cfcfc	83	default:
dd4131b3 BS	84	ret = 0;
dd4131b3 BS	85	break;
e80cfcfc	86	}
1569fc29	87	DPRINTF("read cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, ret);
dd4131b3 BS	88
dd4131b3 BS	89	return ret;
e80cfcfc FB	90	}
	91
	92	static void slavio_intctl_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	93	{
	94	SLAVIO_INTCTLState *s = opaque;
	95	uint32_t saddr;
	96	int cpu;
	97
	98	cpu = (addr & (MAX_CPUS - 1) * TARGET_PAGE_SIZE) >> 12;
	99	saddr = (addr & INTCTL_MAXADDR) >> 2;
1569fc29	100	DPRINTF("write cpu %d reg 0x" TARGET_FMT_plx " = %x\n", cpu, addr, val);
e80cfcfc FB	101	switch (saddr) {
	102	case 1: // clear pending softints
	103	if (val & 0x4000)
	104	val \|= 80000000;
	105	val &= 0xfffe0000;
	106	s->intreg_pending[cpu] &= ~val;
327ac2e7	107	slavio_check_interrupts(s);
66321a11	108	DPRINTF("Cleared cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	109	break;
	110	case 2: // set softint
	111	val &= 0xfffe0000;
	112	s->intreg_pending[cpu] \|= val;
ba3c64fb	113	slavio_check_interrupts(s);
66321a11	114	DPRINTF("Set cpu %d irq mask %x, curmask %x\n", cpu, val, s->intreg_pending[cpu]);
e80cfcfc FB	115	break;
	116	default:
	117	break;
	118	}
	119	}
	120
	121	static CPUReadMemoryFunc *slavio_intctl_mem_read[3] = {
	122	slavio_intctl_mem_readl,
	123	slavio_intctl_mem_readl,
	124	slavio_intctl_mem_readl,
	125	};
	126
	127	static CPUWriteMemoryFunc *slavio_intctl_mem_write[3] = {
	128	slavio_intctl_mem_writel,
	129	slavio_intctl_mem_writel,
	130	slavio_intctl_mem_writel,
	131	};
	132
	133	// master system interrupt controller
	134	static uint32_t slavio_intctlm_mem_readl(void *opaque, target_phys_addr_t addr)
	135	{
	136	SLAVIO_INTCTLState *s = opaque;
dd4131b3	137	uint32_t saddr, ret;
e80cfcfc FB	138
	139	saddr = (addr & INTCTLM_MAXADDR) >> 2;
	140	switch (saddr) {
	141	case 0:
dd4131b3 BS	142	ret = s->intregm_pending & 0x7fffffff;
dd4131b3 BS	143	break;
e80cfcfc	144	case 1:
dd4131b3 BS	145	ret = s->intregm_disabled;
dd4131b3 BS	146	break;
e80cfcfc	147	case 4:
dd4131b3 BS	148	ret = s->target_cpu;
dd4131b3 BS	149	break;
e80cfcfc	150	default:
dd4131b3 BS	151	ret = 0;
dd4131b3 BS	152	break;
e80cfcfc	153	}
1569fc29	154	DPRINTF("read system reg 0x" TARGET_FMT_plx " = %x\n", addr, ret);
dd4131b3 BS	155
dd4131b3 BS	156	return ret;
e80cfcfc FB	157	}
	158
	159	static void slavio_intctlm_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	160	{
	161	SLAVIO_INTCTLState *s = opaque;
	162	uint32_t saddr;
	163
c6fdf5fc	164	saddr = (addr & INTCTLM_MASK) >> 2;
1569fc29	165	DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
e80cfcfc FB	166	switch (saddr) {
e80cfcfc FB	167	case 2: // clear (enable)
6bae7071	168	// Force clear unused bits
3475187d	169	val &= ~0x4fb2007f;
e80cfcfc	170	s->intregm_disabled &= ~val;
66321a11 FB	171	DPRINTF("Enabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
66321a11 FB	172	slavio_check_interrupts(s);
e80cfcfc FB	173	break;
e80cfcfc FB	174	case 3: // set (disable, clear pending)
6bae7071	175	// Force clear unused bits
3475187d	176	val &= ~0x4fb2007f;
e80cfcfc FB	177	s->intregm_disabled \|= val;
e80cfcfc FB	178	s->intregm_pending &= ~val;
327ac2e7	179	slavio_check_interrupts(s);
66321a11	180	DPRINTF("Disabled master irq mask %x, curmask %x\n", val, s->intregm_disabled);
e80cfcfc FB	181	break;
	182	case 4:
	183	s->target_cpu = val & (MAX_CPUS - 1);
327ac2e7	184	slavio_check_interrupts(s);
66321a11	185	DPRINTF("Set master irq cpu %d\n", s->target_cpu);
e80cfcfc FB	186	break;
	187	default:
	188	break;
	189	}
	190	}
	191
	192	static CPUReadMemoryFunc *slavio_intctlm_mem_read[3] = {
	193	slavio_intctlm_mem_readl,
	194	slavio_intctlm_mem_readl,
	195	slavio_intctlm_mem_readl,
	196	};
	197
	198	static CPUWriteMemoryFunc *slavio_intctlm_mem_write[3] = {
	199	slavio_intctlm_mem_writel,
	200	slavio_intctlm_mem_writel,
	201	slavio_intctlm_mem_writel,
	202	};
	203
	204	void slavio_pic_info(void *opaque)
	205	{
	206	SLAVIO_INTCTLState *s = opaque;
	207	int i;
	208
	209	for (i = 0; i < MAX_CPUS; i++) {
	210	term_printf("per-cpu %d: pending 0x%08x\n", i, s->intreg_pending[i]);
	211	}
	212	term_printf("master: pending 0x%08x, disabled 0x%08x\n", s->intregm_pending, s->intregm_disabled);
	213	}
	214
	215	void slavio_irq_info(void *opaque)
	216	{
	217	#ifndef DEBUG_IRQ_COUNT
	218	term_printf("irq statistic code not compiled.\n");
	219	#else
	220	SLAVIO_INTCTLState *s = opaque;
	221	int i;
	222	int64_t count;
	223
	224	term_printf("IRQ statistics:\n");
	225	for (i = 0; i < 32; i++) {
	226	count = s->irq_count[i];
	227	if (count > 0)
26a76461	228	term_printf("%2d: %" PRId64 "\n", i, count);
e80cfcfc FB	229	}
	230	#endif
	231	}
	232
66321a11 FB	233	static void slavio_check_interrupts(void *opaque)
	234	{
	235	SLAVIO_INTCTLState *s = opaque;
327ac2e7 BS	236	uint32_t pending = s->intregm_pending, pil_pending;
327ac2e7 BS	237	unsigned int i, j;
66321a11 FB	238
	239	pending &= ~s->intregm_disabled;
	240
b3a23197	241	DPRINTF("pending %x disabled %x\n", pending, s->intregm_disabled);
ba3c64fb	242	for (i = 0; i < MAX_CPUS; i++) {
327ac2e7	243	pil_pending = 0;
b3a23197 BS	244	if (pending && !(s->intregm_disabled & 0x80000000) &&
	245	(i == s->target_cpu)) {
	246	for (j = 0; j < 32; j++) {
327ac2e7 BS	247	if (pending & (1 << j))
327ac2e7 BS	248	pil_pending \|= 1 << s->intbit_to_level[j];
b3a23197 BS	249	}
b3a23197 BS	250	}
327ac2e7 BS	251	pil_pending \|= (s->intreg_pending[i] >> 16) & 0xfffe;
	252
	253	for (j = 0; j < MAX_PILS; j++) {
	254	if (pil_pending & (1 << j)) {
	255	if (!(s->pil_out[i] & (1 << j)))
	256	qemu_irq_raise(s->cpu_irqs[i][j]);
	257	} else {
	258	if (s->pil_out[i] & (1 << j))
	259	qemu_irq_lower(s->cpu_irqs[i][j]);
ba3c64fb FB	260	}
ba3c64fb FB	261	}
327ac2e7	262	s->pil_out[i] = pil_pending;
ba3c64fb	263	}
66321a11 FB	264	}
66321a11 FB	265
e80cfcfc FB	266	/*
	267	* "irq" here is the bit number in the system interrupt register to
	268	* separate serial and keyboard interrupts sharing a level.
	269	*/
d7edfd27	270	static void slavio_set_irq(void *opaque, int irq, int level)
e80cfcfc FB	271	{
e80cfcfc FB	272	SLAVIO_INTCTLState *s = opaque;
b3a23197 BS	273	uint32_t mask = 1 << irq;
	274	uint32_t pil = s->intbit_to_level[irq];
	275
	276	DPRINTF("Set cpu %d irq %d -> pil %d level %d\n", s->target_cpu, irq, pil,
	277	level);
	278	if (pil > 0) {
	279	if (level) {
327ac2e7 BS	280	#ifdef DEBUG_IRQ_COUNT
	281	s->irq_count[pil]++;
	282	#endif
b3a23197 BS	283	s->intregm_pending \|= mask;
	284	s->intreg_pending[s->target_cpu] \|= 1 << pil;
	285	} else {
	286	s->intregm_pending &= ~mask;
	287	s->intreg_pending[s->target_cpu] &= ~(1 << pil);
	288	}
	289	slavio_check_interrupts(s);
e80cfcfc FB	290	}
	291	}
	292
d7edfd27	293	static void slavio_set_timer_irq_cpu(void *opaque, int cpu, int level)
ba3c64fb FB	294	{
	295	SLAVIO_INTCTLState *s = opaque;
	296
b3a23197	297	DPRINTF("Set cpu %d local timer level %d\n", cpu, level);
d7edfd27	298
b3a23197	299	if (level)
d7edfd27	300	s->intreg_pending[cpu] \|= s->cputimer_bit;
b3a23197	301	else
d7edfd27	302	s->intreg_pending[cpu] &= ~s->cputimer_bit;
d7edfd27	303
ba3c64fb FB	304	slavio_check_interrupts(s);
	305	}
	306
e80cfcfc FB	307	static void slavio_intctl_save(QEMUFile f, void opaque)
	308	{
	309	SLAVIO_INTCTLState *s = opaque;
	310	int i;
5fafdf24	311
e80cfcfc FB	312	for (i = 0; i < MAX_CPUS; i++) {
	313	qemu_put_be32s(f, &s->intreg_pending[i]);
	314	}
	315	qemu_put_be32s(f, &s->intregm_pending);
	316	qemu_put_be32s(f, &s->intregm_disabled);
	317	qemu_put_be32s(f, &s->target_cpu);
	318	}
	319
	320	static int slavio_intctl_load(QEMUFile f, void opaque, int version_id)
	321	{
	322	SLAVIO_INTCTLState *s = opaque;
	323	int i;
	324
	325	if (version_id != 1)
	326	return -EINVAL;
	327
	328	for (i = 0; i < MAX_CPUS; i++) {
	329	qemu_get_be32s(f, &s->intreg_pending[i]);
	330	}
	331	qemu_get_be32s(f, &s->intregm_pending);
	332	qemu_get_be32s(f, &s->intregm_disabled);
	333	qemu_get_be32s(f, &s->target_cpu);
327ac2e7	334	slavio_check_interrupts(s);
e80cfcfc FB	335	return 0;
	336	}
	337
	338	static void slavio_intctl_reset(void *opaque)
	339	{
	340	SLAVIO_INTCTLState *s = opaque;
	341	int i;
	342
	343	for (i = 0; i < MAX_CPUS; i++) {
	344	s->intreg_pending[i] = 0;
	345	}
6bae7071	346	s->intregm_disabled = ~0xffb2007f;
e80cfcfc FB	347	s->intregm_pending = 0;
e80cfcfc FB	348	s->target_cpu = 0;
327ac2e7	349	slavio_check_interrupts(s);
e80cfcfc FB	350	}
e80cfcfc FB	351
5dcb6b91	352	void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
d537cf6c	353	const uint32_t *intbit_to_level,
d7edfd27	354	qemu_irq irq, qemu_irq cpu_irq,
b3a23197	355	qemu_irq **parent_irq, unsigned int cputimer)
e80cfcfc FB	356	{
	357	int slavio_intctl_io_memory, slavio_intctlm_io_memory, i;
	358	SLAVIO_INTCTLState *s;
	359
	360	s = qemu_mallocz(sizeof(SLAVIO_INTCTLState));
	361	if (!s)
	362	return NULL;
	363
e0353fe2	364	s->intbit_to_level = intbit_to_level;
e80cfcfc FB	365	for (i = 0; i < MAX_CPUS; i++) {
e80cfcfc FB	366	slavio_intctl_io_memory = cpu_register_io_memory(0, slavio_intctl_mem_read, slavio_intctl_mem_write, s);
5aca8c3b BS	367	cpu_register_physical_memory(addr + i * TARGET_PAGE_SIZE, INTCTL_SIZE,
5aca8c3b BS	368	slavio_intctl_io_memory);
b3a23197	369	s->cpu_irqs[i] = parent_irq[i];
e80cfcfc FB	370	}
	371
	372	slavio_intctlm_io_memory = cpu_register_io_memory(0, slavio_intctlm_mem_read, slavio_intctlm_mem_write, s);
5aca8c3b	373	cpu_register_physical_memory(addrg, INTCTLM_SIZE, slavio_intctlm_io_memory);
e80cfcfc FB	374
	375	register_savevm("slavio_intctl", addr, 1, slavio_intctl_save, slavio_intctl_load, s);
	376	qemu_register_reset(slavio_intctl_reset, s);
d537cf6c	377	*irq = qemu_allocate_irqs(slavio_set_irq, s, 32);
d7edfd27 BS	378
	379	*cpu_irq = qemu_allocate_irqs(slavio_set_timer_irq_cpu, s, MAX_CPUS);
	380	s->cputimer_bit = 1 << s->intbit_to_level[cputimer];
e80cfcfc FB	381	slavio_intctl_reset(s);
	382	return s;
	383	}
	384