[mirror_qemu.git] / hw / slavio_misc.c

/*
 * QEMU Sparc SLAVIO aux io port emulation
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "sysemu.h"

/* debug misc */
//#define DEBUG_MISC

/*
 * This is the auxio port, chip control and system control part of
 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * This also includes the PMC CPU idle controller.
 */

#ifdef DEBUG_MISC
#define MISC_DPRINTF(fmt, args...) \
do { printf("MISC: " fmt , ##args); } while (0)
#else
#define MISC_DPRINTF(fmt, args...)
#endif

typedef struct MiscState {
    qemu_irq irq;
    uint8_t config;
    uint8_t aux1, aux2;
    uint8_t diag, mctrl;
    uint32_t sysctrl;
    uint16_t leds;
    qemu_irq cpu_halt;
    qemu_irq fdc_tc;
} MiscState;

#define MISC_SIZE 1
#define SYSCTRL_MAXADDR 3
#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
#define LED_MAXADDR 1
#define LED_SIZE (LED_MAXADDR + 1)

#define MISC_MASK 0x0fff0000
#define MISC_LEDS 0x01600000
#define MISC_CFG  0x01800000
#define MISC_DIAG 0x01a00000
#define MISC_MDM  0x01b00000
#define MISC_SYS  0x01f00000

#define AUX1_TC        0x02

#define AUX2_PWROFF    0x01
#define AUX2_PWRINTCLR 0x02
#define AUX2_PWRFAIL   0x20

#define CFG_PWRINTEN   0x08

#define SYS_RESET      0x01
#define SYS_RESETSTAT  0x02

static void slavio_misc_update_irq(void *opaque)
{
    MiscState *s = opaque;

    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
        MISC_DPRINTF("Raise IRQ\n");
        qemu_irq_raise(s->irq);
    } else {
        MISC_DPRINTF("Lower IRQ\n");
        qemu_irq_lower(s->irq);
    }
}

static void slavio_misc_reset(void *opaque)
{
    MiscState *s = opaque;

    // Diagnostic and system control registers not cleared in reset
    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}

void slavio_set_power_fail(void *opaque, int power_failing)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
    if (power_failing && (s->config & CFG_PWRINTEN)) {
        s->aux2 |= AUX2_PWRFAIL;
    } else {
        s->aux2 &= ~AUX2_PWRFAIL;
    }
    slavio_misc_update_irq(s);
}

static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    switch (addr & MISC_MASK) {
    case MISC_CFG:
        MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
        s->config = val & 0xff;
        slavio_misc_update_irq(s);
        break;
    case MISC_DIAG:
        MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
        s->diag = val & 0xff;
        break;
    case MISC_MDM:
        MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
        s->mctrl = val & 0xff;
        break;
    default:
        break;
    }
}

static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr & MISC_MASK) {
    case MISC_CFG:
        ret = s->config;
        MISC_DPRINTF("Read config %2.2x\n", ret);
        break;
    case MISC_DIAG:
        ret = s->diag;
        MISC_DPRINTF("Read diag %2.2x\n", ret);
        break;
    case MISC_MDM:
        ret = s->mctrl;
        MISC_DPRINTF("Read modem control %2.2x\n", ret);
        break;
    default:
        break;
    }
    return ret;
}

static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
    slavio_misc_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
    slavio_misc_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
    if (val & AUX1_TC) {
        // Send a pulse to floppy terminal count line
        if (s->fdc_tc) {
            qemu_irq_raise(s->fdc_tc);
            qemu_irq_lower(s->fdc_tc);
        }
        val &= ~AUX1_TC;
    }
    s->aux1 = val & 0xff;
}

static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux1;
    MISC_DPRINTF("Read aux1 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
    slavio_aux1_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
    slavio_aux1_mem_writeb,
    NULL,
    NULL,
};

static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    val &= AUX2_PWRINTCLR | AUX2_PWROFF;
    MISC_DPRINTF("Write aux2 %2.2x\n", val);
    val |= s->aux2 & AUX2_PWRFAIL;
    if (val & AUX2_PWRINTCLR) // Clear Power Fail int
        val &= AUX2_PWROFF;
    s->aux2 = val;
    if (val & AUX2_PWROFF)
        qemu_system_shutdown_request();
    slavio_misc_update_irq(s);
}

static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    ret = s->aux2;
    MISC_DPRINTF("Read aux2 %2.2x\n", ret);

    return ret;
}

static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
    slavio_aux2_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
    slavio_aux2_mem_writeb,
    NULL,
    NULL,
};

static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
    qemu_irq_raise(s->cpu_halt);
}

static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
{
    uint32_t ret = 0;

    MISC_DPRINTF("Read power management %2.2x\n", ret);
    return ret;
}

static CPUReadMemoryFunc *apc_mem_read[3] = {
    apc_mem_readb,
    NULL,
    NULL,
};

static CPUWriteMemoryFunc *apc_mem_write[3] = {
    apc_mem_writeb,
    NULL,
    NULL,
};

static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0, saddr;

    saddr = addr & SYSCTRL_MAXADDR;
    switch (saddr) {
    case 0:
        ret = s->sysctrl;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
                 ret);
    return ret;
}

static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    MiscState *s = opaque;
    uint32_t saddr;

    saddr = addr & SYSCTRL_MAXADDR;
    MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " =  %x\n", addr,
                 val);
    switch (saddr) {
    case 0:
        if (val & SYS_RESET) {
            s->sysctrl = SYS_RESETSTAT;
            qemu_system_reset_request();
        }
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
    NULL,
    NULL,
    slavio_sysctrl_mem_writel,
};

static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0, saddr;

    saddr = addr & LED_MAXADDR;
    switch (saddr) {
    case 0:
        ret = s->leds;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
                 ret);
    return ret;
}

static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;
    uint32_t saddr;

    saddr = addr & LED_MAXADDR;
    MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " =  %x\n", addr,
                 val);
    switch (saddr) {
    case 0:
        s->leds = val;
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
    NULL,
    slavio_led_mem_readw,
    NULL,
};

static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
    NULL,
    slavio_led_mem_writew,
    NULL,
};

static void slavio_misc_save(QEMUFile *f, void *opaque)
{
    MiscState *s = opaque;
    uint32_t tmp = 0;
    uint8_t tmp8;

    qemu_put_be32s(f, &tmp); /* ignored, was IRQ.  */
    qemu_put_8s(f, &s->config);
    qemu_put_8s(f, &s->aux1);
    qemu_put_8s(f, &s->aux2);
    qemu_put_8s(f, &s->diag);
    qemu_put_8s(f, &s->mctrl);
    tmp8 = s->sysctrl & 0xff;
    qemu_put_8s(f, &tmp8);
}

static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
{
    MiscState *s = opaque;
    uint32_t tmp;
    uint8_t tmp8;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &tmp);
    qemu_get_8s(f, &s->config);
    qemu_get_8s(f, &s->aux1);
    qemu_get_8s(f, &s->aux2);
    qemu_get_8s(f, &s->diag);
    qemu_get_8s(f, &s->mctrl);
    qemu_get_8s(f, &tmp8);
    s->sysctrl = (uint32_t)tmp8;
    return 0;
}

void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
                       target_phys_addr_t aux1_base,
                       target_phys_addr_t aux2_base, qemu_irq irq,
                       qemu_irq cpu_halt, qemu_irq **fdc_tc)
{
    int io;
    MiscState *s;

    s = qemu_mallocz(sizeof(MiscState));
    if (!s)
        return NULL;

    if (base) {
        /* 8 bit registers */
        io = cpu_register_io_memory(0, slavio_misc_mem_read,
                                    slavio_misc_mem_write, s);
        // Slavio control
        cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
        // Diagnostics
        cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
        // Modem control
        cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);

        /* 16 bit registers */
        io = cpu_register_io_memory(0, slavio_led_mem_read,
                                    slavio_led_mem_write, s);
        /* ss600mp diag LEDs */
        cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);

        /* 32 bit registers */
        io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
                                    slavio_sysctrl_mem_write, s);
        // System control
        cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
    }

    // AUX 1 (Misc System Functions)
    if (aux1_base) {
        io = cpu_register_io_memory(0, slavio_aux1_mem_read,
                                    slavio_aux1_mem_write, s);
        cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
    }

    // AUX 2 (Software Powerdown Control)
    if (aux2_base) {
        io = cpu_register_io_memory(0, slavio_aux2_mem_read,
                                    slavio_aux2_mem_write, s);
        cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
    }

    // Power management (APC) XXX: not a Slavio device
    if (power_base) {
        io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
        cpu_register_physical_memory(power_base, MISC_SIZE, io);
    }

    s->irq = irq;
    s->cpu_halt = cpu_halt;
    *fdc_tc = &s->fdc_tc;

    register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
                    s);
    qemu_register_reset(slavio_misc_reset, s);
    slavio_misc_reset(s);

    return s;
}
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sparc SLAVIO aux io port emulation
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "sun4m.h"
	26	#include "sysemu.h"
	27
3475187d FB	28	/* debug misc */
	29	//#define DEBUG_MISC
	30
	31	/*
	32	* This is the auxio port, chip control and system control part of
	33	* chip STP2001 (Slave I/O), also produced as NCR89C105. See
	34	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	35	*
	36	* This also includes the PMC CPU idle controller.
	37	*/
	38
	39	#ifdef DEBUG_MISC
	40	#define MISC_DPRINTF(fmt, args...) \
	41	do { printf("MISC: " fmt , ##args); } while (0)
	42	#else
	43	#define MISC_DPRINTF(fmt, args...)
	44	#endif
	45
	46	typedef struct MiscState {
d537cf6c	47	qemu_irq irq;
3475187d FB	48	uint8_t config;
3475187d FB	49	uint8_t aux1, aux2;
bfa30a38 BS	50	uint8_t diag, mctrl;
bfa30a38 BS	51	uint32_t sysctrl;
6a3b9cc9	52	uint16_t leds;
6d0c293d	53	qemu_irq cpu_halt;
2be17ebd	54	qemu_irq fdc_tc;
3475187d FB	55	} MiscState;
3475187d FB	56
5aca8c3b	57	#define MISC_SIZE 1
bfa30a38 BS	58	#define SYSCTRL_MAXADDR 3
bfa30a38 BS	59	#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
d5296cb5	60	#define LED_MAXADDR 1
6a3b9cc9	61	#define LED_SIZE (LED_MAXADDR + 1)
3475187d	62
7debeb82 BS	63	#define MISC_MASK 0x0fff0000
	64	#define MISC_LEDS 0x01600000
	65	#define MISC_CFG 0x01800000
7debeb82 BS	66	#define MISC_DIAG 0x01a00000
	67	#define MISC_MDM 0x01b00000
	68	#define MISC_SYS 0x01f00000
7debeb82	69
2be17ebd BS	70	#define AUX1_TC 0x02
2be17ebd BS	71
7debeb82 BS	72	#define AUX2_PWROFF 0x01
	73	#define AUX2_PWRINTCLR 0x02
	74	#define AUX2_PWRFAIL 0x20
	75
	76	#define CFG_PWRINTEN 0x08
	77
	78	#define SYS_RESET 0x01
	79	#define SYS_RESETSTAT 0x02
	80
3475187d FB	81	static void slavio_misc_update_irq(void *opaque)
	82	{
	83	MiscState *s = opaque;
	84
7debeb82	85	if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
d537cf6c PB	86	MISC_DPRINTF("Raise IRQ\n");
d537cf6c PB	87	qemu_irq_raise(s->irq);
3475187d	88	} else {
d537cf6c PB	89	MISC_DPRINTF("Lower IRQ\n");
d537cf6c PB	90	qemu_irq_lower(s->irq);
3475187d FB	91	}
	92	}
	93
	94	static void slavio_misc_reset(void *opaque)
	95	{
	96	MiscState *s = opaque;
	97
4e3b1ea1	98	// Diagnostic and system control registers not cleared in reset
3475187d FB	99	s->config = s->aux1 = s->aux2 = s->mctrl = 0;
	100	}
	101
	102	void slavio_set_power_fail(void *opaque, int power_failing)
	103	{
	104	MiscState *s = opaque;
	105
	106	MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
7debeb82 BS	107	if (power_failing && (s->config & CFG_PWRINTEN)) {
7debeb82 BS	108	s->aux2 \|= AUX2_PWRFAIL;
3475187d	109	} else {
7debeb82	110	s->aux2 &= ~AUX2_PWRFAIL;
3475187d FB	111	}
	112	slavio_misc_update_irq(s);
	113	}
	114
bfa30a38 BS	115	static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
bfa30a38 BS	116	uint32_t val)
3475187d FB	117	{
	118	MiscState *s = opaque;
	119
7debeb82 BS	120	switch (addr & MISC_MASK) {
7debeb82 BS	121	case MISC_CFG:
f930d07e BS	122	MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
	123	s->config = val & 0xff;
	124	slavio_misc_update_irq(s);
	125	break;
7debeb82	126	case MISC_DIAG:
f930d07e BS	127	MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
	128	s->diag = val & 0xff;
	129	break;
7debeb82	130	case MISC_MDM:
f930d07e BS	131	MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
	132	s->mctrl = val & 0xff;
	133	break;
df33e639	134	default:
f930d07e	135	break;
3475187d FB	136	}
	137	}
	138
	139	static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
	140	{
	141	MiscState *s = opaque;
	142	uint32_t ret = 0;
	143
7debeb82 BS	144	switch (addr & MISC_MASK) {
7debeb82 BS	145	case MISC_CFG:
f930d07e BS	146	ret = s->config;
	147	MISC_DPRINTF("Read config %2.2x\n", ret);
	148	break;
7debeb82	149	case MISC_DIAG:
f930d07e BS	150	ret = s->diag;
	151	MISC_DPRINTF("Read diag %2.2x\n", ret);
	152	break;
7debeb82	153	case MISC_MDM:
f930d07e BS	154	ret = s->mctrl;
	155	MISC_DPRINTF("Read modem control %2.2x\n", ret);
	156	break;
df33e639	157	default:
f930d07e	158	break;
3475187d FB	159	}
	160	return ret;
	161	}
	162
	163	static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
	164	slavio_misc_mem_readb,
7c560456 BS	165	NULL,
7c560456 BS	166	NULL,
3475187d FB	167	};
	168
	169	static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
	170	slavio_misc_mem_writeb,
7c560456 BS	171	NULL,
7c560456 BS	172	NULL,
3475187d FB	173	};
3475187d FB	174
0019ad53 BS	175	static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
	176	uint32_t val)
	177	{
	178	MiscState *s = opaque;
	179
	180	MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
2be17ebd BS	181	if (val & AUX1_TC) {
	182	// Send a pulse to floppy terminal count line
	183	if (s->fdc_tc) {
	184	qemu_irq_raise(s->fdc_tc);
	185	qemu_irq_lower(s->fdc_tc);
	186	}
	187	val &= ~AUX1_TC;
	188	}
0019ad53 BS	189	s->aux1 = val & 0xff;
	190	}
	191
	192	static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
	193	{
	194	MiscState *s = opaque;
	195	uint32_t ret = 0;
	196
	197	ret = s->aux1;
	198	MISC_DPRINTF("Read aux1 %2.2x\n", ret);
	199
	200	return ret;
	201	}
	202
	203	static CPUReadMemoryFunc *slavio_aux1_mem_read[3] = {
	204	slavio_aux1_mem_readb,
	205	NULL,
	206	NULL,
	207	};
	208
	209	static CPUWriteMemoryFunc *slavio_aux1_mem_write[3] = {
	210	slavio_aux1_mem_writeb,
	211	NULL,
	212	NULL,
	213	};
	214
	215	static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
	216	uint32_t val)
	217	{
	218	MiscState *s = opaque;
	219
	220	val &= AUX2_PWRINTCLR \| AUX2_PWROFF;
	221	MISC_DPRINTF("Write aux2 %2.2x\n", val);
	222	val \|= s->aux2 & AUX2_PWRFAIL;
	223	if (val & AUX2_PWRINTCLR) // Clear Power Fail int
	224	val &= AUX2_PWROFF;
	225	s->aux2 = val;
	226	if (val & AUX2_PWROFF)
	227	qemu_system_shutdown_request();
	228	slavio_misc_update_irq(s);
	229	}
	230
	231	static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
	232	{
	233	MiscState *s = opaque;
	234	uint32_t ret = 0;
	235
	236	ret = s->aux2;
	237	MISC_DPRINTF("Read aux2 %2.2x\n", ret);
	238
	239	return ret;
	240	}
	241
	242	static CPUReadMemoryFunc *slavio_aux2_mem_read[3] = {
	243	slavio_aux2_mem_readb,
	244	NULL,
	245	NULL,
	246	};
	247
	248	static CPUWriteMemoryFunc *slavio_aux2_mem_write[3] = {
	249	slavio_aux2_mem_writeb,
	250	NULL,
	251	NULL,
	252	};
253
254	static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
255	{
256	MiscState *s = opaque;
257
258	MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
6d0c293d	259	qemu_irq_raise(s->cpu_halt);
0019ad53 BS	260	}
	261
	262	static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
	263	{
	264	uint32_t ret = 0;
	265
	266	MISC_DPRINTF("Read power management %2.2x\n", ret);
	267	return ret;
	268	}
	269
	270	static CPUReadMemoryFunc *apc_mem_read[3] = {
	271	apc_mem_readb,
	272	NULL,
	273	NULL,
	274	};
	275
	276	static CPUWriteMemoryFunc *apc_mem_write[3] = {
	277	apc_mem_writeb,
	278	NULL,
	279	NULL,
	280	};
	281
bfa30a38 BS	282	static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
	283	{
	284	MiscState *s = opaque;
	285	uint32_t ret = 0, saddr;
	286
	287	saddr = addr & SYSCTRL_MAXADDR;
	288	switch (saddr) {
	289	case 0:
	290	ret = s->sysctrl;
	291	break;
	292	default:
	293	break;
	294	}
	295	MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
	296	ret);
	297	return ret;
	298	}
	299
	300	static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
	301	uint32_t val)
	302	{
	303	MiscState *s = opaque;
	304	uint32_t saddr;
	305
	306	saddr = addr & SYSCTRL_MAXADDR;
	307	MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
	308	val);
	309	switch (saddr) {
	310	case 0:
7debeb82 BS	311	if (val & SYS_RESET) {
7debeb82 BS	312	s->sysctrl = SYS_RESETSTAT;
bfa30a38 BS	313	qemu_system_reset_request();
	314	}
	315	break;
	316	default:
	317	break;
	318	}
	319	}
	320
	321	static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
7c560456 BS	322	NULL,
7c560456 BS	323	NULL,
bfa30a38 BS	324	slavio_sysctrl_mem_readl,
	325	};
	326
	327	static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
7c560456 BS	328	NULL,
7c560456 BS	329	NULL,
bfa30a38 BS	330	slavio_sysctrl_mem_writel,
	331	};
	332
7c560456	333	static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
6a3b9cc9 BS	334	{
	335	MiscState *s = opaque;
	336	uint32_t ret = 0, saddr;
	337
	338	saddr = addr & LED_MAXADDR;
	339	switch (saddr) {
	340	case 0:
	341	ret = s->leds;
	342	break;
	343	default:
	344	break;
	345	}
	346	MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
	347	ret);
	348	return ret;
	349	}
	350
7c560456	351	static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
6a3b9cc9 BS	352	uint32_t val)
	353	{
	354	MiscState *s = opaque;
	355	uint32_t saddr;
	356
	357	saddr = addr & LED_MAXADDR;
	358	MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
	359	val);
	360	switch (saddr) {
	361	case 0:
d5296cb5	362	s->leds = val;
6a3b9cc9 BS	363	break;
	364	default:
	365	break;
	366	}
	367	}
	368
	369	static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
7c560456 BS	370	NULL,
	371	slavio_led_mem_readw,
	372	NULL,
6a3b9cc9 BS	373	};
	374
	375	static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
7c560456 BS	376	NULL,
	377	slavio_led_mem_writew,
	378	NULL,
6a3b9cc9 BS	379	};
6a3b9cc9 BS	380
3475187d FB	381	static void slavio_misc_save(QEMUFile f, void opaque)
	382	{
	383	MiscState *s = opaque;
22548760	384	uint32_t tmp = 0;
bfa30a38	385	uint8_t tmp8;
3475187d	386
d537cf6c	387	qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
3475187d FB	388	qemu_put_8s(f, &s->config);
	389	qemu_put_8s(f, &s->aux1);
	390	qemu_put_8s(f, &s->aux2);
	391	qemu_put_8s(f, &s->diag);
	392	qemu_put_8s(f, &s->mctrl);
bfa30a38 BS	393	tmp8 = s->sysctrl & 0xff;
bfa30a38 BS	394	qemu_put_8s(f, &tmp8);
3475187d FB	395	}
	396
	397	static int slavio_misc_load(QEMUFile f, void opaque, int version_id)
	398	{
	399	MiscState *s = opaque;
22548760	400	uint32_t tmp;
bfa30a38	401	uint8_t tmp8;
3475187d FB	402
	403	if (version_id != 1)
	404	return -EINVAL;
	405
d537cf6c	406	qemu_get_be32s(f, &tmp);
3475187d FB	407	qemu_get_8s(f, &s->config);
	408	qemu_get_8s(f, &s->aux1);
	409	qemu_get_8s(f, &s->aux2);
	410	qemu_get_8s(f, &s->diag);
	411	qemu_get_8s(f, &s->mctrl);
bfa30a38 BS	412	qemu_get_8s(f, &tmp8);
bfa30a38 BS	413	s->sysctrl = (uint32_t)tmp8;
3475187d FB	414	return 0;
	415	}
	416
5dcb6b91	417	void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
0019ad53 BS	418	target_phys_addr_t aux1_base,
0019ad53 BS	419	target_phys_addr_t aux2_base, qemu_irq irq,
6d0c293d	420	qemu_irq cpu_halt, qemu_irq **fdc_tc)
3475187d	421	{
0019ad53	422	int io;
3475187d FB	423	MiscState *s;
	424
	425	s = qemu_mallocz(sizeof(MiscState));
	426	if (!s)
	427	return NULL;
	428
0019ad53 BS	429	if (base) {
	430	/* 8 bit registers */
	431	io = cpu_register_io_memory(0, slavio_misc_mem_read,
	432	slavio_misc_mem_write, s);
	433	// Slavio control
	434	cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE, io);
	435	// Diagnostics
	436	cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE, io);
	437	// Modem control
	438	cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE, io);
	439
	440	/* 16 bit registers */
	441	io = cpu_register_io_memory(0, slavio_led_mem_read,
	442	slavio_led_mem_write, s);
	443	/* ss600mp diag LEDs */
	444	cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE, io);
	445
	446	/* 32 bit registers */
	447	io = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
	448	slavio_sysctrl_mem_write, s);
	449	// System control
	450	cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE, io);
	451	}
	452
	453	// AUX 1 (Misc System Functions)
	454	if (aux1_base) {
	455	io = cpu_register_io_memory(0, slavio_aux1_mem_read,
	456	slavio_aux1_mem_write, s);
	457	cpu_register_physical_memory(aux1_base, MISC_SIZE, io);
	458	}
	459
	460	// AUX 2 (Software Powerdown Control)
	461	if (aux2_base) {
	462	io = cpu_register_io_memory(0, slavio_aux2_mem_read,
	463	slavio_aux2_mem_write, s);
	464	cpu_register_physical_memory(aux2_base, MISC_SIZE, io);
	465	}
	466
	467	// Power management (APC) XXX: not a Slavio device
	468	if (power_base) {
	469	io = cpu_register_io_memory(0, apc_mem_read, apc_mem_write, s);
	470	cpu_register_physical_memory(power_base, MISC_SIZE, io);
	471	}
bfa30a38	472
3475187d	473	s->irq = irq;
6d0c293d	474	s->cpu_halt = cpu_halt;
2be17ebd	475	*fdc_tc = &s->fdc_tc;
3475187d	476
bfa30a38 BS	477	register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
bfa30a38 BS	478	s);
3475187d FB	479	qemu_register_reset(slavio_misc_reset, s);
3475187d FB	480	slavio_misc_reset(s);
0019ad53	481
3475187d FB	482	return s;
3475187d FB	483	}