[mirror_qemu.git] / hw / slavio_misc.c

/*
 * QEMU Sparc SLAVIO aux io port emulation
 *
 * Copyright (c) 2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "hw.h"
#include "sun4m.h"
#include "sysemu.h"

/* debug misc */
//#define DEBUG_MISC

/*
 * This is the auxio port, chip control and system control part of
 * chip STP2001 (Slave I/O), also produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * This also includes the PMC CPU idle controller.
 */

#ifdef DEBUG_MISC
#define MISC_DPRINTF(fmt, args...) \
do { printf("MISC: " fmt , ##args); } while (0)
#else
#define MISC_DPRINTF(fmt, args...)
#endif

typedef struct MiscState {
    qemu_irq irq;
    uint8_t config;
    uint8_t aux1, aux2;
    uint8_t diag, mctrl;
    uint32_t sysctrl;
    uint16_t leds;
    target_phys_addr_t power_base;
} MiscState;

#define MISC_SIZE 1
#define SYSCTRL_MAXADDR 3
#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
#define LED_MAXADDR 2
#define LED_SIZE (LED_MAXADDR + 1)

#define MISC_MASK 0x0fff0000
#define MISC_LEDS 0x01600000
#define MISC_CFG  0x01800000
#define MISC_AUX1 0x01900000
#define MISC_AUX2 0x01910000
#define MISC_DIAG 0x01a00000
#define MISC_MDM  0x01b00000
#define MISC_SYS  0x01f00000

#define AUX2_PWROFF    0x01
#define AUX2_PWRINTCLR 0x02
#define AUX2_PWRFAIL   0x20

#define CFG_PWRINTEN   0x08

#define SYS_RESET      0x01
#define SYS_RESETSTAT  0x02

static void slavio_misc_update_irq(void *opaque)
{
    MiscState *s = opaque;

    if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
        MISC_DPRINTF("Raise IRQ\n");
        qemu_irq_raise(s->irq);
    } else {
        MISC_DPRINTF("Lower IRQ\n");
        qemu_irq_lower(s->irq);
    }
}

static void slavio_misc_reset(void *opaque)
{
    MiscState *s = opaque;

    // Diagnostic and system control registers not cleared in reset
    s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}

void slavio_set_power_fail(void *opaque, int power_failing)
{
    MiscState *s = opaque;

    MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
    if (power_failing && (s->config & CFG_PWRINTEN)) {
        s->aux2 |= AUX2_PWRFAIL;
    } else {
        s->aux2 &= ~AUX2_PWRFAIL;
    }
    slavio_misc_update_irq(s);
}

static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
                                   uint32_t val)
{
    MiscState *s = opaque;

    switch (addr & MISC_MASK) {
    case MISC_CFG:
        MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
        s->config = val & 0xff;
        slavio_misc_update_irq(s);
        break;
    case MISC_AUX1:
        MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
        s->aux1 = val & 0xff;
        break;
    case MISC_AUX2:
        val &= AUX2_PWRINTCLR | AUX2_PWROFF;
        MISC_DPRINTF("Write aux2 %2.2x\n", val);
        val |= s->aux2 & AUX2_PWRFAIL;
        if (val & AUX2_PWRINTCLR) // Clear Power Fail int
            val &= AUX2_PWROFF;
        s->aux2 = val;
        if (val & AUX2_PWROFF)
            qemu_system_shutdown_request();
        slavio_misc_update_irq(s);
        break;
    case MISC_DIAG:
        MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
        s->diag = val & 0xff;
        break;
    case MISC_MDM:
        MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
        s->mctrl = val & 0xff;
        break;
    default:
        if (addr == s->power_base) {
            MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
            cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
        }
        break;
    }
}

static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0;

    switch (addr & MISC_MASK) {
    case MISC_CFG:
        ret = s->config;
        MISC_DPRINTF("Read config %2.2x\n", ret);
        break;
    case MISC_AUX1:
        ret = s->aux1;
        MISC_DPRINTF("Read aux1 %2.2x\n", ret);
        break;
    case MISC_AUX2:
        ret = s->aux2;
        MISC_DPRINTF("Read aux2 %2.2x\n", ret);
        break;
    case MISC_DIAG:
        ret = s->diag;
        MISC_DPRINTF("Read diag %2.2x\n", ret);
        break;
    case MISC_MDM:
        ret = s->mctrl;
        MISC_DPRINTF("Read modem control %2.2x\n", ret);
        break;
    default:
        if (addr == s->power_base) {
            MISC_DPRINTF("Read power management %2.2x\n", ret);
        }
        break;
    }
    return ret;
}

static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
    slavio_misc_mem_readb,
    slavio_misc_mem_readb,
    slavio_misc_mem_readb,
};

static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
    slavio_misc_mem_writeb,
    slavio_misc_mem_writeb,
    slavio_misc_mem_writeb,
};

static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0, saddr;

    saddr = addr & SYSCTRL_MAXADDR;
    switch (saddr) {
    case 0:
        ret = s->sysctrl;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
                 ret);
    return ret;
}

static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
                                      uint32_t val)
{
    MiscState *s = opaque;
    uint32_t saddr;

    saddr = addr & SYSCTRL_MAXADDR;
    MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " =  %x\n", addr,
                 val);
    switch (saddr) {
    case 0:
        if (val & SYS_RESET) {
            s->sysctrl = SYS_RESETSTAT;
            qemu_system_reset_request();
        }
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
    slavio_sysctrl_mem_readl,
    slavio_sysctrl_mem_readl,
    slavio_sysctrl_mem_readl,
};

static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
    slavio_sysctrl_mem_writel,
    slavio_sysctrl_mem_writel,
    slavio_sysctrl_mem_writel,
};

static uint32_t slavio_led_mem_reads(void *opaque, target_phys_addr_t addr)
{
    MiscState *s = opaque;
    uint32_t ret = 0, saddr;

    saddr = addr & LED_MAXADDR;
    switch (saddr) {
    case 0:
        ret = s->leds;
        break;
    default:
        break;
    }
    MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
                 ret);
    return ret;
}

static void slavio_led_mem_writes(void *opaque, target_phys_addr_t addr,
                                  uint32_t val)
{
    MiscState *s = opaque;
    uint32_t saddr;

    saddr = addr & LED_MAXADDR;
    MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " =  %x\n", addr,
                 val);
    switch (saddr) {
    case 0:
        s->sysctrl = val;
        break;
    default:
        break;
    }
}

static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
    slavio_led_mem_reads,
    slavio_led_mem_reads,
    slavio_led_mem_reads,
};

static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
    slavio_led_mem_writes,
    slavio_led_mem_writes,
    slavio_led_mem_writes,
};

static void slavio_misc_save(QEMUFile *f, void *opaque)
{
    MiscState *s = opaque;
    int tmp;
    uint8_t tmp8;

    tmp = 0;
    qemu_put_be32s(f, &tmp); /* ignored, was IRQ.  */
    qemu_put_8s(f, &s->config);
    qemu_put_8s(f, &s->aux1);
    qemu_put_8s(f, &s->aux2);
    qemu_put_8s(f, &s->diag);
    qemu_put_8s(f, &s->mctrl);
    tmp8 = s->sysctrl & 0xff;
    qemu_put_8s(f, &tmp8);
}

static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
{
    MiscState *s = opaque;
    int tmp;
    uint8_t tmp8;

    if (version_id != 1)
        return -EINVAL;

    qemu_get_be32s(f, &tmp);
    qemu_get_8s(f, &s->config);
    qemu_get_8s(f, &s->aux1);
    qemu_get_8s(f, &s->aux2);
    qemu_get_8s(f, &s->diag);
    qemu_get_8s(f, &s->mctrl);
    qemu_get_8s(f, &tmp8);
    s->sysctrl = (uint32_t)tmp8;
    return 0;
}

void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
                       qemu_irq irq)
{
    int slavio_misc_io_memory;
    MiscState *s;

    s = qemu_mallocz(sizeof(MiscState));
    if (!s)
        return NULL;

    /* 8 bit registers */
    slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
                                                   slavio_misc_mem_write, s);
    // Slavio control
    cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE,
                                 slavio_misc_io_memory);
    // AUX 1
    cpu_register_physical_memory(base + MISC_AUX1, MISC_SIZE,
                                 slavio_misc_io_memory);
    // AUX 2
    cpu_register_physical_memory(base + MISC_AUX2, MISC_SIZE,
                                 slavio_misc_io_memory);
    // Diagnostics
    cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE,
                                 slavio_misc_io_memory);
    // Modem control
    cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE,
                                 slavio_misc_io_memory);
    // Power management
    cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
    s->power_base = power_base;

    /* 16 bit registers */
    slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
                                                   slavio_led_mem_write, s);
    /* ss600mp diag LEDs */
    cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE,
                                 slavio_misc_io_memory);

    /* 32 bit registers */
    slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
                                                   slavio_sysctrl_mem_write,
                                                   s);
    // System control
    cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE,
                                 slavio_misc_io_memory);

    s->irq = irq;

    register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
                    s);
    qemu_register_reset(slavio_misc_reset, s);
    slavio_misc_reset(s);
    return s;
}
Commit	Line	Data
3475187d FB	1	/*
3475187d FB	2	* QEMU Sparc SLAVIO aux io port emulation
5fafdf24	3	*
3475187d	4	* Copyright (c) 2005 Fabrice Bellard
5fafdf24	5	*
3475187d FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
87ecb68b PB	24	#include "hw.h"
	25	#include "sun4m.h"
	26	#include "sysemu.h"
	27
3475187d FB	28	/* debug misc */
	29	//#define DEBUG_MISC
	30
	31	/*
	32	* This is the auxio port, chip control and system control part of
	33	* chip STP2001 (Slave I/O), also produced as NCR89C105. See
	34	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
	35	*
	36	* This also includes the PMC CPU idle controller.
	37	*/
	38
	39	#ifdef DEBUG_MISC
	40	#define MISC_DPRINTF(fmt, args...) \
	41	do { printf("MISC: " fmt , ##args); } while (0)
	42	#else
	43	#define MISC_DPRINTF(fmt, args...)
	44	#endif
	45
	46	typedef struct MiscState {
d537cf6c	47	qemu_irq irq;
3475187d FB	48	uint8_t config;
3475187d FB	49	uint8_t aux1, aux2;
bfa30a38 BS	50	uint8_t diag, mctrl;
bfa30a38 BS	51	uint32_t sysctrl;
6a3b9cc9	52	uint16_t leds;
df33e639	53	target_phys_addr_t power_base;
3475187d FB	54	} MiscState;
3475187d FB	55
5aca8c3b	56	#define MISC_SIZE 1
bfa30a38 BS	57	#define SYSCTRL_MAXADDR 3
bfa30a38 BS	58	#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
6a3b9cc9 BS	59	#define LED_MAXADDR 2
6a3b9cc9 BS	60	#define LED_SIZE (LED_MAXADDR + 1)
3475187d	61
7debeb82 BS	62	#define MISC_MASK 0x0fff0000
	63	#define MISC_LEDS 0x01600000
	64	#define MISC_CFG 0x01800000
	65	#define MISC_AUX1 0x01900000
	66	#define MISC_AUX2 0x01910000
	67	#define MISC_DIAG 0x01a00000
	68	#define MISC_MDM 0x01b00000
	69	#define MISC_SYS 0x01f00000
7debeb82 BS	70
	71	#define AUX2_PWROFF 0x01
	72	#define AUX2_PWRINTCLR 0x02
	73	#define AUX2_PWRFAIL 0x20
	74
	75	#define CFG_PWRINTEN 0x08
	76
	77	#define SYS_RESET 0x01
	78	#define SYS_RESETSTAT 0x02
	79
3475187d FB	80	static void slavio_misc_update_irq(void *opaque)
	81	{
	82	MiscState *s = opaque;
	83
7debeb82	84	if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
d537cf6c PB	85	MISC_DPRINTF("Raise IRQ\n");
d537cf6c PB	86	qemu_irq_raise(s->irq);
3475187d	87	} else {
d537cf6c PB	88	MISC_DPRINTF("Lower IRQ\n");
d537cf6c PB	89	qemu_irq_lower(s->irq);
3475187d FB	90	}
	91	}
	92
	93	static void slavio_misc_reset(void *opaque)
	94	{
	95	MiscState *s = opaque;
	96
4e3b1ea1	97	// Diagnostic and system control registers not cleared in reset
3475187d FB	98	s->config = s->aux1 = s->aux2 = s->mctrl = 0;
	99	}
	100
	101	void slavio_set_power_fail(void *opaque, int power_failing)
	102	{
	103	MiscState *s = opaque;
	104
	105	MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
7debeb82 BS	106	if (power_failing && (s->config & CFG_PWRINTEN)) {
7debeb82 BS	107	s->aux2 \|= AUX2_PWRFAIL;
3475187d	108	} else {
7debeb82	109	s->aux2 &= ~AUX2_PWRFAIL;
3475187d FB	110	}
	111	slavio_misc_update_irq(s);
	112	}
	113
bfa30a38 BS	114	static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
bfa30a38 BS	115	uint32_t val)
3475187d FB	116	{
	117	MiscState *s = opaque;
	118
7debeb82 BS	119	switch (addr & MISC_MASK) {
7debeb82 BS	120	case MISC_CFG:
f930d07e BS	121	MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
	122	s->config = val & 0xff;
	123	slavio_misc_update_irq(s);
	124	break;
7debeb82	125	case MISC_AUX1:
f930d07e BS	126	MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
	127	s->aux1 = val & 0xff;
	128	break;
7debeb82 BS	129	case MISC_AUX2:
7debeb82 BS	130	val &= AUX2_PWRINTCLR \| AUX2_PWROFF;
f930d07e	131	MISC_DPRINTF("Write aux2 %2.2x\n", val);
7debeb82 BS	132	val \|= s->aux2 & AUX2_PWRFAIL;
	133	if (val & AUX2_PWRINTCLR) // Clear Power Fail int
	134	val &= AUX2_PWROFF;
f930d07e	135	s->aux2 = val;
7debeb82	136	if (val & AUX2_PWROFF)
f930d07e BS	137	qemu_system_shutdown_request();
	138	slavio_misc_update_irq(s);
	139	break;
7debeb82	140	case MISC_DIAG:
f930d07e BS	141	MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
	142	s->diag = val & 0xff;
	143	break;
7debeb82	144	case MISC_MDM:
f930d07e BS	145	MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
	146	s->mctrl = val & 0xff;
	147	break;
df33e639 BS	148	default:
	149	if (addr == s->power_base) {
	150	MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
	151	cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
	152	}
f930d07e	153	break;
3475187d FB	154	}
	155	}
	156
	157	static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
	158	{
	159	MiscState *s = opaque;
	160	uint32_t ret = 0;
	161
7debeb82 BS	162	switch (addr & MISC_MASK) {
7debeb82 BS	163	case MISC_CFG:
f930d07e BS	164	ret = s->config;
	165	MISC_DPRINTF("Read config %2.2x\n", ret);
	166	break;
7debeb82	167	case MISC_AUX1:
f930d07e BS	168	ret = s->aux1;
	169	MISC_DPRINTF("Read aux1 %2.2x\n", ret);
	170	break;
7debeb82	171	case MISC_AUX2:
f930d07e BS	172	ret = s->aux2;
	173	MISC_DPRINTF("Read aux2 %2.2x\n", ret);
	174	break;
7debeb82	175	case MISC_DIAG:
f930d07e BS	176	ret = s->diag;
	177	MISC_DPRINTF("Read diag %2.2x\n", ret);
	178	break;
7debeb82	179	case MISC_MDM:
f930d07e BS	180	ret = s->mctrl;
	181	MISC_DPRINTF("Read modem control %2.2x\n", ret);
	182	break;
df33e639 BS	183	default:
	184	if (addr == s->power_base) {
	185	MISC_DPRINTF("Read power management %2.2x\n", ret);
	186	}
f930d07e	187	break;
3475187d FB	188	}
	189	return ret;
	190	}
	191
	192	static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
	193	slavio_misc_mem_readb,
	194	slavio_misc_mem_readb,
	195	slavio_misc_mem_readb,
	196	};
	197
	198	static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
	199	slavio_misc_mem_writeb,
	200	slavio_misc_mem_writeb,
	201	slavio_misc_mem_writeb,
	202	};
	203
bfa30a38 BS	204	static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
	205	{
	206	MiscState *s = opaque;
	207	uint32_t ret = 0, saddr;
	208
	209	saddr = addr & SYSCTRL_MAXADDR;
	210	switch (saddr) {
	211	case 0:
	212	ret = s->sysctrl;
	213	break;
	214	default:
	215	break;
	216	}
	217	MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
	218	ret);
	219	return ret;
	220	}
	221
	222	static void slavio_sysctrl_mem_writel(void *opaque, target_phys_addr_t addr,
	223	uint32_t val)
	224	{
	225	MiscState *s = opaque;
	226	uint32_t saddr;
	227
	228	saddr = addr & SYSCTRL_MAXADDR;
	229	MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
	230	val);
	231	switch (saddr) {
	232	case 0:
7debeb82 BS	233	if (val & SYS_RESET) {
7debeb82 BS	234	s->sysctrl = SYS_RESETSTAT;
bfa30a38 BS	235	qemu_system_reset_request();
	236	}
	237	break;
	238	default:
	239	break;
	240	}
	241	}
	242
	243	static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
	244	slavio_sysctrl_mem_readl,
	245	slavio_sysctrl_mem_readl,
	246	slavio_sysctrl_mem_readl,
	247	};
	248
	249	static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
	250	slavio_sysctrl_mem_writel,
	251	slavio_sysctrl_mem_writel,
	252	slavio_sysctrl_mem_writel,
	253	};
	254
6a3b9cc9 BS	255	static uint32_t slavio_led_mem_reads(void *opaque, target_phys_addr_t addr)
	256	{
	257	MiscState *s = opaque;
	258	uint32_t ret = 0, saddr;
	259
	260	saddr = addr & LED_MAXADDR;
	261	switch (saddr) {
	262	case 0:
	263	ret = s->leds;
	264	break;
	265	default:
	266	break;
	267	}
	268	MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
	269	ret);
	270	return ret;
	271	}
	272
	273	static void slavio_led_mem_writes(void *opaque, target_phys_addr_t addr,
	274	uint32_t val)
	275	{
	276	MiscState *s = opaque;
	277	uint32_t saddr;
	278
	279	saddr = addr & LED_MAXADDR;
	280	MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
	281	val);
	282	switch (saddr) {
	283	case 0:
	284	s->sysctrl = val;
	285	break;
	286	default:
	287	break;
	288	}
	289	}
	290
	291	static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
	292	slavio_led_mem_reads,
	293	slavio_led_mem_reads,
	294	slavio_led_mem_reads,
	295	};
	296
	297	static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
	298	slavio_led_mem_writes,
	299	slavio_led_mem_writes,
	300	slavio_led_mem_writes,
	301	};
	302
3475187d FB	303	static void slavio_misc_save(QEMUFile f, void opaque)
	304	{
	305	MiscState *s = opaque;
d537cf6c	306	int tmp;
bfa30a38	307	uint8_t tmp8;
3475187d	308
d537cf6c PB	309	tmp = 0;
d537cf6c PB	310	qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
3475187d FB	311	qemu_put_8s(f, &s->config);
	312	qemu_put_8s(f, &s->aux1);
	313	qemu_put_8s(f, &s->aux2);
	314	qemu_put_8s(f, &s->diag);
	315	qemu_put_8s(f, &s->mctrl);
bfa30a38 BS	316	tmp8 = s->sysctrl & 0xff;
bfa30a38 BS	317	qemu_put_8s(f, &tmp8);
3475187d FB	318	}
	319
	320	static int slavio_misc_load(QEMUFile f, void opaque, int version_id)
	321	{
	322	MiscState *s = opaque;
d537cf6c	323	int tmp;
bfa30a38	324	uint8_t tmp8;
3475187d FB	325
	326	if (version_id != 1)
	327	return -EINVAL;
	328
d537cf6c	329	qemu_get_be32s(f, &tmp);
3475187d FB	330	qemu_get_8s(f, &s->config);
	331	qemu_get_8s(f, &s->aux1);
	332	qemu_get_8s(f, &s->aux2);
	333	qemu_get_8s(f, &s->diag);
	334	qemu_get_8s(f, &s->mctrl);
bfa30a38 BS	335	qemu_get_8s(f, &tmp8);
bfa30a38 BS	336	s->sysctrl = (uint32_t)tmp8;
3475187d FB	337	return 0;
	338	}
	339
5dcb6b91 BS	340	void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
5dcb6b91 BS	341	qemu_irq irq)
3475187d FB	342	{
	343	int slavio_misc_io_memory;
	344	MiscState *s;
	345
	346	s = qemu_mallocz(sizeof(MiscState));
	347	if (!s)
	348	return NULL;
	349
bfa30a38 BS	350	/* 8 bit registers */
	351	slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
	352	slavio_misc_mem_write, s);
3475187d	353	// Slavio control
7debeb82	354	cpu_register_physical_memory(base + MISC_CFG, MISC_SIZE,
5aca8c3b	355	slavio_misc_io_memory);
3475187d	356	// AUX 1
7debeb82	357	cpu_register_physical_memory(base + MISC_AUX1, MISC_SIZE,
5aca8c3b	358	slavio_misc_io_memory);
3475187d	359	// AUX 2
7debeb82	360	cpu_register_physical_memory(base + MISC_AUX2, MISC_SIZE,
5aca8c3b	361	slavio_misc_io_memory);
3475187d	362	// Diagnostics
7debeb82	363	cpu_register_physical_memory(base + MISC_DIAG, MISC_SIZE,
5aca8c3b	364	slavio_misc_io_memory);
3475187d	365	// Modem control
7debeb82	366	cpu_register_physical_memory(base + MISC_MDM, MISC_SIZE,
5aca8c3b	367	slavio_misc_io_memory);
3475187d	368	// Power management
5aca8c3b	369	cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
df33e639	370	s->power_base = power_base;
3475187d	371
6a3b9cc9 BS	372	/* 16 bit registers */
	373	slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
	374	slavio_led_mem_write, s);
	375	/* ss600mp diag LEDs */
7debeb82	376	cpu_register_physical_memory(base + MISC_LEDS, MISC_SIZE,
6a3b9cc9 BS	377	slavio_misc_io_memory);
6a3b9cc9 BS	378
bfa30a38 BS	379	/* 32 bit registers */
	380	slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
	381	slavio_sysctrl_mem_write,
	382	s);
	383	// System control
7debeb82	384	cpu_register_physical_memory(base + MISC_SYS, SYSCTRL_SIZE,
bfa30a38 BS	385	slavio_misc_io_memory);
bfa30a38 BS	386
3475187d FB	387	s->irq = irq;
3475187d FB	388
bfa30a38 BS	389	register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
bfa30a38 BS	390	s);
3475187d FB	391	qemu_register_reset(slavio_misc_reset, s);
	392	slavio_misc_reset(s);
	393	return s;
	394	}