[mirror_qemu.git] / hw / slavio_timer.c

/*
 * QEMU Sparc SLAVIO timer controller emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
#include "vl.h"

//#define DEBUG_TIMER

#ifdef DEBUG_TIMER
#define DPRINTF(fmt, args...) \
do { printf("TIMER: " fmt , ##args); } while (0)
#else
#define DPRINTF(fmt, args...)
#endif

/*
 * Registers of hardware timer in sun4m.
 *
 * This is the timer/counter part of chip STP2001 (Slave I/O), also
 * produced as NCR89C105. See
 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
 *
 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
 * are zero. Bit 31 is 1 when count has been reached.
 *
 * Per-CPU timers interrupt local CPU, system timer uses normal
 * interrupt routing.
 *
 */

#define MAX_CPUS 16

typedef struct SLAVIO_TIMERState {
    qemu_irq irq;
    ptimer_state *timer;
    uint32_t count, counthigh, reached;
    uint64_t limit;
    // processor only
    int running;
    struct SLAVIO_TIMERState *master;
    int slave_index;
    // system only
    struct SLAVIO_TIMERState *slave[MAX_CPUS];
    uint32_t slave_mode;
} SLAVIO_TIMERState;

#define TIMER_MAXADDR 0x1f
#define SYS_TIMER_SIZE 0x14
#define CPU_TIMER_SIZE 0x10

static int slavio_timer_is_user(SLAVIO_TIMERState *s)
{
    return s->master && (s->master->slave_mode & (1 << s->slave_index));
}

// Update count, set irq, update expire_time
// Convert from ptimer countdown units
static void slavio_timer_get_out(SLAVIO_TIMERState *s)
{
    uint64_t count;

    count = s->limit - (ptimer_get_count(s->timer) << 9);
    DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
            s->count);
    s->count = count & 0xfffffe00;
    s->counthigh = count >> 32;
}

// timer callback
static void slavio_timer_irq(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    slavio_timer_get_out(s);
    DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
    if (!slavio_timer_is_user(s)) {
        s->reached = 0x80000000;
        qemu_irq_raise(s->irq);
    }
}

static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr, ret;

    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
        // read limit (system counter mode) or read most signifying
        // part of counter (user mode)
        if (slavio_timer_is_user(s)) {
            // read user timer MSW
            slavio_timer_get_out(s);
            ret = s->counthigh;
        } else {
            // read limit
            // clear irq
            qemu_irq_lower(s->irq);
            s->reached = 0;
            ret = s->limit & 0x7fffffff;
        }
        break;
    case 1:
        // read counter and reached bit (system mode) or read lsbits
        // of counter (user mode)
        slavio_timer_get_out(s);
        if (slavio_timer_is_user(s)) // read user timer LSW
            ret = s->count & 0xffffffe00;
        else // read limit
            ret = (s->count & 0x7ffffe00) | s->reached;
        break;
    case 3:
        // only available in processor counter/timer
        // read start/stop status
        ret = s->running;
        break;
    case 4:
        // only available in system counter
        // read user/system mode
        ret = s->slave_mode;
        break;
    default:
        DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
        ret = 0;
        break;
    }
    DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);

    return ret;
}

static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t saddr;
    int reload = 0;

    DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
    saddr = (addr & TIMER_MAXADDR) >> 2;
    switch (saddr) {
    case 0:
        if (slavio_timer_is_user(s)) {
            // set user counter MSW, reset counter
            qemu_irq_lower(s->irq);
            s->limit = 0x7ffffffffffffe00ULL;
            DPRINTF("processor %d user timer reset\n", s->slave_index);
            ptimer_set_limit(s->timer, s->limit >> 9, 1);
        } else {
            // set limit, reset counter
            qemu_irq_lower(s->irq);
            s->limit = val & 0x7ffffe00ULL;
            if (!s->limit)
                s->limit = 0x7ffffe00ULL;
            ptimer_set_limit(s->timer, s->limit >> 9, 1);
        }
        break;
    case 1:
        if (slavio_timer_is_user(s)) {
            // set user counter LSW, reset counter
            qemu_irq_lower(s->irq);
            s->limit = 0x7ffffffffffffe00ULL;
            DPRINTF("processor %d user timer reset\n", s->slave_index);
            ptimer_set_limit(s->timer, s->limit >> 9, 1);
        } else
            DPRINTF("not user timer\n");
        break;
    case 2:
        // set limit without resetting counter
        s->limit = val & 0x7ffffe00ULL;
        if (!s->limit)
            s->limit = 0x7ffffe00ULL;
        ptimer_set_limit(s->timer, s->limit >> 9, reload);
        break;
    case 3:
        if (slavio_timer_is_user(s)) {
            // start/stop user counter
            if ((val & 1) && !s->running) {
                DPRINTF("processor %d user timer started\n", s->slave_index);
                ptimer_run(s->timer, 0);
                s->running = 1;
            } else if (!(val & 1) && s->running) {
                DPRINTF("processor %d user timer stopped\n", s->slave_index);
                ptimer_stop(s->timer);
                s->running = 0;
            }
        }
        break;
    case 4:
        if (s->master == NULL) {
            unsigned int i;

            for (i = 0; i < MAX_CPUS; i++) {
                if (val & (1 << i)) {
                    qemu_irq_lower(s->slave[i]->irq);
                    s->slave[i]->limit = -1ULL;
                }
                if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
                    ptimer_stop(s->slave[i]->timer);
                    ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9, 1);
                    DPRINTF("processor %d timer changed\n", s->slave[i]->slave_index);
                    ptimer_run(s->slave[i]->timer, 0);
                }
            }
            s->slave_mode = val & ((1 << MAX_CPUS) - 1);
        } else
            DPRINTF("not system timer\n");
        break;
    default:
        DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
        break;
    }
}

static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
    slavio_timer_mem_readl,
};

static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
    slavio_timer_mem_writel,
};

static void slavio_timer_save(QEMUFile *f, void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    qemu_put_be64s(f, &s->limit);
    qemu_put_be32s(f, &s->count);
    qemu_put_be32s(f, &s->counthigh);
    qemu_put_be32(f, 0); // Was irq
    qemu_put_be32s(f, &s->reached);
    qemu_put_be32s(f, &s->running);
    qemu_put_be32s(f, 0); // Was mode
    qemu_put_ptimer(f, s->timer);
}

static int slavio_timer_load(QEMUFile *f, void *opaque, int version_id)
{
    SLAVIO_TIMERState *s = opaque;
    uint32_t tmp;

    if (version_id != 2)
        return -EINVAL;

    qemu_get_be64s(f, &s->limit);
    qemu_get_be32s(f, &s->count);
    qemu_get_be32s(f, &s->counthigh);
    qemu_get_be32s(f, &tmp); // Was irq
    qemu_get_be32s(f, &s->reached);
    qemu_get_be32s(f, &s->running);
    qemu_get_be32s(f, &tmp); // Was mode
    qemu_get_ptimer(f, s->timer);

    return 0;
}

static void slavio_timer_reset(void *opaque)
{
    SLAVIO_TIMERState *s = opaque;

    if (slavio_timer_is_user(s))
        s->limit = 0x7ffffffffffffe00ULL;
    else
        s->limit = 0x7ffffe00ULL;
    s->count = 0;
    s->reached = 0;
    ptimer_set_limit(s->timer, s->limit >> 9, 1);
    ptimer_run(s->timer, 0);
    s->running = 1;
    qemu_irq_lower(s->irq);
}

static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
                                            qemu_irq irq,
                                            SLAVIO_TIMERState *master,
                                            int slave_index)
{
    int slavio_timer_io_memory;
    SLAVIO_TIMERState *s;
    QEMUBH *bh;

    s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
    if (!s)
        return s;
    s->irq = irq;
    s->master = master;
    s->slave_index = slave_index;
    bh = qemu_bh_new(slavio_timer_irq, s);
    s->timer = ptimer_init(bh);
    ptimer_set_period(s->timer, 500ULL);

    slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
                                                    slavio_timer_mem_write, s);
    if (master)
        cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
    else
        cpu_register_physical_memory(addr, SYS_TIMER_SIZE, slavio_timer_io_memory);
    register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
    qemu_register_reset(slavio_timer_reset, s);
    slavio_timer_reset(s);

    return s;
}

void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
                           qemu_irq *cpu_irqs)
{
    SLAVIO_TIMERState *master;
    unsigned int i;

    master = slavio_timer_init(base + 0x10000ULL, master_irq, NULL, 0);

    for (i = 0; i < MAX_CPUS; i++) {
        master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
                                             (i * TARGET_PAGE_SIZE),
                                             cpu_irqs[i], master, i);
    }
}
Commit	Line	Data
e80cfcfc FB	1	/*
	2	* QEMU Sparc SLAVIO timer controller emulation
	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
e80cfcfc FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	#include "vl.h"
	25
	26	//#define DEBUG_TIMER
	27
66321a11 FB	28	#ifdef DEBUG_TIMER
	29	#define DPRINTF(fmt, args...) \
	30	do { printf("TIMER: " fmt , ##args); } while (0)
	31	#else
	32	#define DPRINTF(fmt, args...)
	33	#endif
	34
e80cfcfc FB	35	/*
	36	* Registers of hardware timer in sun4m.
	37	*
	38	* This is the timer/counter part of chip STP2001 (Slave I/O), also
	39	* produced as NCR89C105. See
	40	* http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
5fafdf24	41	*
e80cfcfc FB	42	* The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
	43	* are zero. Bit 31 is 1 when count has been reached.
	44	*
ba3c64fb FB	45	* Per-CPU timers interrupt local CPU, system timer uses normal
	46	* interrupt routing.
	47	*
e80cfcfc FB	48	*/
e80cfcfc FB	49
81732d19 BS	50	#define MAX_CPUS 16
81732d19 BS	51
e80cfcfc	52	typedef struct SLAVIO_TIMERState {
d7edfd27	53	qemu_irq irq;
8d05ea8a BS	54	ptimer_state *timer;
	55	uint32_t count, counthigh, reached;
	56	uint64_t limit;
115646b6 BS	57	// processor only
	58	int running;
	59	struct SLAVIO_TIMERState *master;
	60	int slave_index;
	61	// system only
81732d19 BS	62	struct SLAVIO_TIMERState *slave[MAX_CPUS];
81732d19 BS	63	uint32_t slave_mode;
e80cfcfc FB	64	} SLAVIO_TIMERState;
	65
	66	#define TIMER_MAXADDR 0x1f
115646b6	67	#define SYS_TIMER_SIZE 0x14
81732d19	68	#define CPU_TIMER_SIZE 0x10
e80cfcfc	69
115646b6 BS	70	static int slavio_timer_is_user(SLAVIO_TIMERState *s)
	71	{
	72	return s->master && (s->master->slave_mode & (1 << s->slave_index));
	73	}
	74
e80cfcfc	75	// Update count, set irq, update expire_time
8d05ea8a	76	// Convert from ptimer countdown units
e80cfcfc FB	77	static void slavio_timer_get_out(SLAVIO_TIMERState *s)
e80cfcfc FB	78	{
8d05ea8a	79	uint64_t count;
e80cfcfc	80
8d05ea8a BS	81	count = s->limit - (ptimer_get_count(s->timer) << 9);
	82	DPRINTF("get_out: limit %" PRIx64 " count %x%08x\n", s->limit, s->counthigh,
	83	s->count);
	84	s->count = count & 0xfffffe00;
	85	s->counthigh = count >> 32;
e80cfcfc FB	86	}
	87
	88	// timer callback
	89	static void slavio_timer_irq(void *opaque)
	90	{
	91	SLAVIO_TIMERState *s = opaque;
	92
e80cfcfc	93	slavio_timer_get_out(s);
8d05ea8a	94	DPRINTF("callback: count %x%08x\n", s->counthigh, s->count);
115646b6 BS	95	if (!slavio_timer_is_user(s)) {
115646b6 BS	96	s->reached = 0x80000000;
f930d07e	97	qemu_irq_raise(s->irq);
115646b6	98	}
e80cfcfc FB	99	}
	100
	101	static uint32_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr)
	102	{
	103	SLAVIO_TIMERState *s = opaque;
8d05ea8a	104	uint32_t saddr, ret;
e80cfcfc FB	105
	106	saddr = (addr & TIMER_MAXADDR) >> 2;
	107	switch (saddr) {
	108	case 0:
f930d07e BS	109	// read limit (system counter mode) or read most signifying
f930d07e BS	110	// part of counter (user mode)
115646b6 BS	111	if (slavio_timer_is_user(s)) {
	112	// read user timer MSW
	113	slavio_timer_get_out(s);
	114	ret = s->counthigh;
	115	} else {
	116	// read limit
f930d07e	117	// clear irq
d7edfd27	118	qemu_irq_lower(s->irq);
f930d07e	119	s->reached = 0;
8d05ea8a	120	ret = s->limit & 0x7fffffff;
f930d07e	121	}
8d05ea8a	122	break;
e80cfcfc	123	case 1:
f930d07e BS	124	// read counter and reached bit (system mode) or read lsbits
	125	// of counter (user mode)
	126	slavio_timer_get_out(s);
115646b6 BS	127	if (slavio_timer_is_user(s)) // read user timer LSW
	128	ret = s->count & 0xffffffe00;
	129	else // read limit
	130	ret = (s->count & 0x7ffffe00) \| s->reached;
8d05ea8a	131	break;
e80cfcfc	132	case 3:
115646b6	133	// only available in processor counter/timer
f930d07e	134	// read start/stop status
115646b6	135	ret = s->running;
8d05ea8a	136	break;
e80cfcfc	137	case 4:
115646b6	138	// only available in system counter
f930d07e	139	// read user/system mode
81732d19	140	ret = s->slave_mode;
8d05ea8a	141	break;
e80cfcfc	142	default:
115646b6	143	DPRINTF("invalid read address " TARGET_FMT_plx "\n", addr);
8d05ea8a BS	144	ret = 0;
8d05ea8a BS	145	break;
e80cfcfc	146	}
8d05ea8a BS	147	DPRINTF("read " TARGET_FMT_plx " = %08x\n", addr, ret);
	148
	149	return ret;
e80cfcfc FB	150	}
	151
	152	static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
	153	{
	154	SLAVIO_TIMERState *s = opaque;
	155	uint32_t saddr;
8d05ea8a	156	int reload = 0;
e80cfcfc	157
8d05ea8a	158	DPRINTF("write " TARGET_FMT_plx " %08x\n", addr, val);
e80cfcfc FB	159	saddr = (addr & TIMER_MAXADDR) >> 2;
	160	switch (saddr) {
	161	case 0:
115646b6 BS	162	if (slavio_timer_is_user(s)) {
115646b6 BS	163	// set user counter MSW, reset counter
81732d19	164	qemu_irq_lower(s->irq);
115646b6 BS	165	s->limit = 0x7ffffffffffffe00ULL;
	166	DPRINTF("processor %d user timer reset\n", s->slave_index);
	167	ptimer_set_limit(s->timer, s->limit >> 9, 1);
	168	} else {
	169	// set limit, reset counter
	170	qemu_irq_lower(s->irq);
	171	s->limit = val & 0x7ffffe00ULL;
81732d19	172	if (!s->limit)
115646b6	173	s->limit = 0x7ffffe00ULL;
81732d19	174	ptimer_set_limit(s->timer, s->limit >> 9, 1);
81732d19	175	}
115646b6 BS	176	break;
	177	case 1:
	178	if (slavio_timer_is_user(s)) {
	179	// set user counter LSW, reset counter
	180	qemu_irq_lower(s->irq);
	181	s->limit = 0x7ffffffffffffe00ULL;
	182	DPRINTF("processor %d user timer reset\n", s->slave_index);
	183	ptimer_set_limit(s->timer, s->limit >> 9, 1);
	184	} else
	185	DPRINTF("not user timer\n");
	186	break;
e80cfcfc	187	case 2:
f930d07e	188	// set limit without resetting counter
8d05ea8a BS	189	s->limit = val & 0x7ffffe00ULL;
	190	if (!s->limit)
	191	s->limit = 0x7ffffe00ULL;
	192	ptimer_set_limit(s->timer, s->limit >> 9, reload);
f930d07e	193	break;
e80cfcfc	194	case 3:
115646b6 BS	195	if (slavio_timer_is_user(s)) {
	196	// start/stop user counter
	197	if ((val & 1) && !s->running) {
	198	DPRINTF("processor %d user timer started\n", s->slave_index);
8d05ea8a	199	ptimer_run(s->timer, 0);
115646b6 BS	200	s->running = 1;
	201	} else if (!(val & 1) && s->running) {
	202	DPRINTF("processor %d user timer stopped\n", s->slave_index);
	203	ptimer_stop(s->timer);
	204	s->running = 0;
f930d07e BS	205	}
	206	}
	207	break;
e80cfcfc	208	case 4:
115646b6	209	if (s->master == NULL) {
81732d19 BS	210	unsigned int i;
	211
	212	for (i = 0; i < MAX_CPUS; i++) {
	213	if (val & (1 << i)) {
	214	qemu_irq_lower(s->slave[i]->irq);
	215	s->slave[i]->limit = -1ULL;
81732d19	216	}
115646b6 BS	217	if ((val & (1 << i)) != (s->slave_mode & (1 << i))) {
	218	ptimer_stop(s->slave[i]->timer);
	219	ptimer_set_limit(s->slave[i]->timer, s->slave[i]->limit >> 9, 1);
	220	DPRINTF("processor %d timer changed\n", s->slave[i]->slave_index);
	221	ptimer_run(s->slave[i]->timer, 0);
	222	}
81732d19 BS	223	}
81732d19 BS	224	s->slave_mode = val & ((1 << MAX_CPUS) - 1);
115646b6 BS	225	} else
115646b6 BS	226	DPRINTF("not system timer\n");
f930d07e	227	break;
e80cfcfc	228	default:
115646b6	229	DPRINTF("invalid write address " TARGET_FMT_plx "\n", addr);
f930d07e	230	break;
e80cfcfc FB	231	}
	232	}
	233
	234	static CPUReadMemoryFunc *slavio_timer_mem_read[3] = {
	235	slavio_timer_mem_readl,
	236	slavio_timer_mem_readl,
	237	slavio_timer_mem_readl,
	238	};
	239
	240	static CPUWriteMemoryFunc *slavio_timer_mem_write[3] = {
	241	slavio_timer_mem_writel,
	242	slavio_timer_mem_writel,
	243	slavio_timer_mem_writel,
	244	};
	245
	246	static void slavio_timer_save(QEMUFile f, void opaque)
	247	{
	248	SLAVIO_TIMERState *s = opaque;
	249
8d05ea8a	250	qemu_put_be64s(f, &s->limit);
e80cfcfc FB	251	qemu_put_be32s(f, &s->count);
e80cfcfc FB	252	qemu_put_be32s(f, &s->counthigh);
d7edfd27	253	qemu_put_be32(f, 0); // Was irq
e80cfcfc	254	qemu_put_be32s(f, &s->reached);
115646b6 BS	255	qemu_put_be32s(f, &s->running);
115646b6 BS	256	qemu_put_be32s(f, 0); // Was mode
8d05ea8a	257	qemu_put_ptimer(f, s->timer);
e80cfcfc FB	258	}
	259
	260	static int slavio_timer_load(QEMUFile f, void opaque, int version_id)
	261	{
	262	SLAVIO_TIMERState *s = opaque;
d7edfd27	263	uint32_t tmp;
3b46e624	264
8d05ea8a	265	if (version_id != 2)
e80cfcfc FB	266	return -EINVAL;
e80cfcfc FB	267
8d05ea8a	268	qemu_get_be64s(f, &s->limit);
e80cfcfc FB	269	qemu_get_be32s(f, &s->count);
e80cfcfc FB	270	qemu_get_be32s(f, &s->counthigh);
d7edfd27	271	qemu_get_be32s(f, &tmp); // Was irq
e80cfcfc	272	qemu_get_be32s(f, &s->reached);
115646b6 BS	273	qemu_get_be32s(f, &s->running);
115646b6 BS	274	qemu_get_be32s(f, &tmp); // Was mode
8d05ea8a BS	275	qemu_get_ptimer(f, s->timer);
8d05ea8a BS	276
e80cfcfc FB	277	return 0;
	278	}
	279
	280	static void slavio_timer_reset(void *opaque)
	281	{
	282	SLAVIO_TIMERState *s = opaque;
	283
115646b6 BS	284	if (slavio_timer_is_user(s))
	285	s->limit = 0x7ffffffffffffe00ULL;
	286	else
	287	s->limit = 0x7ffffe00ULL;
e80cfcfc	288	s->count = 0;
e80cfcfc	289	s->reached = 0;
8d05ea8a BS	290	ptimer_set_limit(s->timer, s->limit >> 9, 1);
8d05ea8a BS	291	ptimer_run(s->timer, 0);
115646b6	292	s->running = 1;
d7edfd27	293	qemu_irq_lower(s->irq);
e80cfcfc FB	294	}
e80cfcfc FB	295
81732d19	296	static SLAVIO_TIMERState *slavio_timer_init(target_phys_addr_t addr,
115646b6 BS	297	qemu_irq irq,
	298	SLAVIO_TIMERState *master,
	299	int slave_index)
e80cfcfc FB	300	{
	301	int slavio_timer_io_memory;
	302	SLAVIO_TIMERState *s;
8d05ea8a	303	QEMUBH *bh;
e80cfcfc FB	304
	305	s = qemu_mallocz(sizeof(SLAVIO_TIMERState));
	306	if (!s)
81732d19	307	return s;
e80cfcfc	308	s->irq = irq;
115646b6 BS	309	s->master = master;
115646b6 BS	310	s->slave_index = slave_index;
8d05ea8a BS	311	bh = qemu_bh_new(slavio_timer_irq, s);
	312	s->timer = ptimer_init(bh);
	313	ptimer_set_period(s->timer, 500ULL);
e80cfcfc FB	314
e80cfcfc FB	315	slavio_timer_io_memory = cpu_register_io_memory(0, slavio_timer_mem_read,
f930d07e	316	slavio_timer_mem_write, s);
115646b6	317	if (master)
81732d19 BS	318	cpu_register_physical_memory(addr, CPU_TIMER_SIZE, slavio_timer_io_memory);
81732d19 BS	319	else
115646b6	320	cpu_register_physical_memory(addr, SYS_TIMER_SIZE, slavio_timer_io_memory);
8d05ea8a	321	register_savevm("slavio_timer", addr, 2, slavio_timer_save, slavio_timer_load, s);
e80cfcfc FB	322	qemu_register_reset(slavio_timer_reset, s);
e80cfcfc FB	323	slavio_timer_reset(s);
81732d19 BS	324
	325	return s;
	326	}
	327
	328	void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
	329	qemu_irq *cpu_irqs)
	330	{
	331	SLAVIO_TIMERState *master;
	332	unsigned int i;
	333
115646b6	334	master = slavio_timer_init(base + 0x10000ULL, master_irq, NULL, 0);
81732d19 BS	335
	336	for (i = 0; i < MAX_CPUS; i++) {
	337	master->slave[i] = slavio_timer_init(base + (target_phys_addr_t)
	338	(i * TARGET_PAGE_SIZE),
115646b6	339	cpu_irqs[i], master, i);
81732d19	340	}
e80cfcfc	341	}