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e80cfcfc
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1/*
2 * QEMU Sparc SLAVIO timer controller emulation
3 *
66321a11 4 * Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24 5 *
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
c70c59ee 24
87ecb68b
PB
25#include "sun4m.h"
26#include "qemu-timer.h"
c70c59ee 27#include "sysbus.h"
97bf4851 28#include "trace.h"
66321a11 29
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30/*
31 * Registers of hardware timer in sun4m.
32 *
33 * This is the timer/counter part of chip STP2001 (Slave I/O), also
34 * produced as NCR89C105. See
35 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt
5fafdf24 36 *
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37 * The 31-bit counter is incremented every 500ns by bit 9. Bits 8..0
38 * are zero. Bit 31 is 1 when count has been reached.
39 *
ba3c64fb
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40 * Per-CPU timers interrupt local CPU, system timer uses normal
41 * interrupt routing.
42 *
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43 */
44
81732d19
BS
45#define MAX_CPUS 16
46
7204ff9c 47typedef struct CPUTimerState {
d7edfd27 48 qemu_irq irq;
8d05ea8a
BS
49 ptimer_state *timer;
50 uint32_t count, counthigh, reached;
f90074f4 51 /* processor only */
22548760 52 uint32_t running;
f90074f4 53 uint64_t limit;
7204ff9c
BS
54} CPUTimerState;
55
56typedef struct SLAVIO_TIMERState {
57 SysBusDevice busdev;
58 uint32_t num_cpus;
7204ff9c 59 uint32_t cputimer_mode;
f90074f4 60 CPUTimerState cputimer[MAX_CPUS + 1];
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61} SLAVIO_TIMERState;
62
7204ff9c 63typedef struct TimerContext {
a3d12d07 64 MemoryRegion iomem;
7204ff9c
BS
65 SLAVIO_TIMERState *s;
66 unsigned int timer_index; /* 0 for system, 1 ... MAX_CPUS for CPU timers */
67} TimerContext;
68
115646b6 69#define SYS_TIMER_SIZE 0x14
81732d19 70#define CPU_TIMER_SIZE 0x10
e80cfcfc 71
d2c38b24
BS
72#define TIMER_LIMIT 0
73#define TIMER_COUNTER 1
74#define TIMER_COUNTER_NORST 2
75#define TIMER_STATUS 3
76#define TIMER_MODE 4
77
78#define TIMER_COUNT_MASK32 0xfffffe00
79#define TIMER_LIMIT_MASK32 0x7fffffff
80#define TIMER_MAX_COUNT64 0x7ffffffffffffe00ULL
81#define TIMER_MAX_COUNT32 0x7ffffe00ULL
82#define TIMER_REACHED 0x80000000
83#define TIMER_PERIOD 500ULL // 500ns
68fb89a2
BS
84#define LIMIT_TO_PERIODS(l) (((l) >> 9) - 1)
85#define PERIODS_TO_LIMIT(l) (((l) + 1) << 9)
d2c38b24 86
7204ff9c 87static int slavio_timer_is_user(TimerContext *tc)
115646b6 88{
7204ff9c
BS
89 SLAVIO_TIMERState *s = tc->s;
90 unsigned int timer_index = tc->timer_index;
91
92 return timer_index != 0 && (s->cputimer_mode & (1 << (timer_index - 1)));
115646b6
BS
93}
94
e80cfcfc 95// Update count, set irq, update expire_time
8d05ea8a 96// Convert from ptimer countdown units
7204ff9c 97static void slavio_timer_get_out(CPUTimerState *t)
e80cfcfc 98{
bd7e2875 99 uint64_t count, limit;
e80cfcfc 100
7204ff9c 101 if (t->limit == 0) { /* free-run system or processor counter */
bd7e2875 102 limit = TIMER_MAX_COUNT32;
7204ff9c
BS
103 } else {
104 limit = t->limit;
105 }
9ebec28b
BS
106 count = limit - PERIODS_TO_LIMIT(ptimer_get_count(t->timer));
107
97bf4851 108 trace_slavio_timer_get_out(t->limit, t->counthigh, t->count);
7204ff9c
BS
109 t->count = count & TIMER_COUNT_MASK32;
110 t->counthigh = count >> 32;
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111}
112
113// timer callback
114static void slavio_timer_irq(void *opaque)
115{
7204ff9c
BS
116 TimerContext *tc = opaque;
117 SLAVIO_TIMERState *s = tc->s;
118 CPUTimerState *t = &s->cputimer[tc->timer_index];
119
120 slavio_timer_get_out(t);
97bf4851 121 trace_slavio_timer_irq(t->counthigh, t->count);
68fb89a2
BS
122 /* if limit is 0 (free-run), there will be no match */
123 if (t->limit != 0) {
124 t->reached = TIMER_REACHED;
125 }
452efba6
BS
126 /* there is no interrupt if user timer or free-run */
127 if (!slavio_timer_is_user(tc) && t->limit != 0) {
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128 qemu_irq_raise(t->irq);
129 }
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130}
131
a3d12d07
BC
132static uint64_t slavio_timer_mem_readl(void *opaque, target_phys_addr_t addr,
133 unsigned size)
e80cfcfc 134{
7204ff9c
BS
135 TimerContext *tc = opaque;
136 SLAVIO_TIMERState *s = tc->s;
8d05ea8a 137 uint32_t saddr, ret;
7204ff9c
BS
138 unsigned int timer_index = tc->timer_index;
139 CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc 140
e64d7d59 141 saddr = addr >> 2;
e80cfcfc 142 switch (saddr) {
d2c38b24 143 case TIMER_LIMIT:
f930d07e
BS
144 // read limit (system counter mode) or read most signifying
145 // part of counter (user mode)
7204ff9c 146 if (slavio_timer_is_user(tc)) {
115646b6 147 // read user timer MSW
7204ff9c
BS
148 slavio_timer_get_out(t);
149 ret = t->counthigh | t->reached;
115646b6
BS
150 } else {
151 // read limit
f930d07e 152 // clear irq
7204ff9c
BS
153 qemu_irq_lower(t->irq);
154 t->reached = 0;
155 ret = t->limit & TIMER_LIMIT_MASK32;
f930d07e 156 }
8d05ea8a 157 break;
d2c38b24 158 case TIMER_COUNTER:
f930d07e
BS
159 // read counter and reached bit (system mode) or read lsbits
160 // of counter (user mode)
7204ff9c
BS
161 slavio_timer_get_out(t);
162 if (slavio_timer_is_user(tc)) { // read user timer LSW
163 ret = t->count & TIMER_MAX_COUNT64;
164 } else { // read limit
165 ret = (t->count & TIMER_MAX_COUNT32) |
166 t->reached;
167 }
8d05ea8a 168 break;
d2c38b24 169 case TIMER_STATUS:
115646b6 170 // only available in processor counter/timer
f930d07e 171 // read start/stop status
7204ff9c
BS
172 if (timer_index > 0) {
173 ret = t->running;
174 } else {
175 ret = 0;
176 }
8d05ea8a 177 break;
d2c38b24 178 case TIMER_MODE:
115646b6 179 // only available in system counter
f930d07e 180 // read user/system mode
7204ff9c 181 ret = s->cputimer_mode;
8d05ea8a 182 break;
e80cfcfc 183 default:
97bf4851 184 trace_slavio_timer_mem_readl_invalid(addr);
8d05ea8a
BS
185 ret = 0;
186 break;
e80cfcfc 187 }
97bf4851 188 trace_slavio_timer_mem_readl(addr, ret);
8d05ea8a 189 return ret;
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190}
191
c227f099 192static void slavio_timer_mem_writel(void *opaque, target_phys_addr_t addr,
a3d12d07 193 uint64_t val, unsigned size)
e80cfcfc 194{
7204ff9c
BS
195 TimerContext *tc = opaque;
196 SLAVIO_TIMERState *s = tc->s;
e80cfcfc 197 uint32_t saddr;
7204ff9c
BS
198 unsigned int timer_index = tc->timer_index;
199 CPUTimerState *t = &s->cputimer[timer_index];
e80cfcfc 200
97bf4851 201 trace_slavio_timer_mem_writel(addr, val);
e64d7d59 202 saddr = addr >> 2;
e80cfcfc 203 switch (saddr) {
d2c38b24 204 case TIMER_LIMIT:
7204ff9c 205 if (slavio_timer_is_user(tc)) {
e1cb9502
BS
206 uint64_t count;
207
115646b6 208 // set user counter MSW, reset counter
7204ff9c
BS
209 t->limit = TIMER_MAX_COUNT64;
210 t->counthigh = val & (TIMER_MAX_COUNT64 >> 32);
211 t->reached = 0;
212 count = ((uint64_t)t->counthigh << 32) | t->count;
97bf4851 213 trace_slavio_timer_mem_writel_limit(timer_index, count);
9ebec28b 214 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
115646b6
BS
215 } else {
216 // set limit, reset counter
7204ff9c
BS
217 qemu_irq_lower(t->irq);
218 t->limit = val & TIMER_MAX_COUNT32;
219 if (t->timer) {
220 if (t->limit == 0) { /* free-run */
221 ptimer_set_limit(t->timer,
77f193da 222 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
7204ff9c
BS
223 } else {
224 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 1);
225 }
85e3023e 226 }
81732d19 227 }
115646b6 228 break;
d2c38b24 229 case TIMER_COUNTER:
7204ff9c 230 if (slavio_timer_is_user(tc)) {
e1cb9502
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231 uint64_t count;
232
115646b6 233 // set user counter LSW, reset counter
7204ff9c
BS
234 t->limit = TIMER_MAX_COUNT64;
235 t->count = val & TIMER_MAX_COUNT64;
236 t->reached = 0;
237 count = ((uint64_t)t->counthigh) << 32 | t->count;
97bf4851 238 trace_slavio_timer_mem_writel_limit(timer_index, count);
9ebec28b 239 ptimer_set_count(t->timer, LIMIT_TO_PERIODS(t->limit - count));
97bf4851
BS
240 } else {
241 trace_slavio_timer_mem_writel_counter_invalid();
242 }
115646b6 243 break;
d2c38b24 244 case TIMER_COUNTER_NORST:
f930d07e 245 // set limit without resetting counter
7204ff9c 246 t->limit = val & TIMER_MAX_COUNT32;
9ebec28b
BS
247 if (t->limit == 0) { /* free-run */
248 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 0);
249 } else {
250 ptimer_set_limit(t->timer, LIMIT_TO_PERIODS(t->limit), 0);
85e3023e 251 }
f930d07e 252 break;
d2c38b24 253 case TIMER_STATUS:
7204ff9c 254 if (slavio_timer_is_user(tc)) {
115646b6 255 // start/stop user counter
7204ff9c 256 if ((val & 1) && !t->running) {
97bf4851 257 trace_slavio_timer_mem_writel_status_start(timer_index);
9ebec28b 258 ptimer_run(t->timer, 0);
7204ff9c
BS
259 t->running = 1;
260 } else if (!(val & 1) && t->running) {
97bf4851 261 trace_slavio_timer_mem_writel_status_stop(timer_index);
9ebec28b 262 ptimer_stop(t->timer);
7204ff9c 263 t->running = 0;
f930d07e
BS
264 }
265 }
266 break;
d2c38b24 267 case TIMER_MODE:
7204ff9c 268 if (timer_index == 0) {
81732d19
BS
269 unsigned int i;
270
7204ff9c 271 for (i = 0; i < s->num_cpus; i++) {
67e42751 272 unsigned int processor = 1 << i;
7204ff9c 273 CPUTimerState *curr_timer = &s->cputimer[i + 1];
67e42751
BS
274
275 // check for a change in timer mode for this processor
7204ff9c 276 if ((val & processor) != (s->cputimer_mode & processor)) {
67e42751 277 if (val & processor) { // counter -> user timer
7204ff9c 278 qemu_irq_lower(curr_timer->irq);
67e42751 279 // counters are always running
7204ff9c
BS
280 ptimer_stop(curr_timer->timer);
281 curr_timer->running = 0;
67e42751 282 // user timer limit is always the same
7204ff9c
BS
283 curr_timer->limit = TIMER_MAX_COUNT64;
284 ptimer_set_limit(curr_timer->timer,
285 LIMIT_TO_PERIODS(curr_timer->limit),
77f193da 286 1);
67e42751
BS
287 // set this processors user timer bit in config
288 // register
7204ff9c 289 s->cputimer_mode |= processor;
97bf4851 290 trace_slavio_timer_mem_writel_mode_user(timer_index);
67e42751
BS
291 } else { // user timer -> counter
292 // stop the user timer if it is running
7204ff9c
BS
293 if (curr_timer->running) {
294 ptimer_stop(curr_timer->timer);
295 }
67e42751 296 // start the counter
7204ff9c
BS
297 ptimer_run(curr_timer->timer, 0);
298 curr_timer->running = 1;
67e42751
BS
299 // clear this processors user timer bit in config
300 // register
7204ff9c 301 s->cputimer_mode &= ~processor;
97bf4851 302 trace_slavio_timer_mem_writel_mode_counter(timer_index);
67e42751 303 }
115646b6 304 }
81732d19 305 }
7204ff9c 306 } else {
97bf4851 307 trace_slavio_timer_mem_writel_mode_invalid();
7204ff9c 308 }
f930d07e 309 break;
e80cfcfc 310 default:
97bf4851 311 trace_slavio_timer_mem_writel_invalid(addr);
f930d07e 312 break;
e80cfcfc
FB
313 }
314}
315
a3d12d07
BC
316static const MemoryRegionOps slavio_timer_mem_ops = {
317 .read = slavio_timer_mem_readl,
318 .write = slavio_timer_mem_writel,
319 .endianness = DEVICE_NATIVE_ENDIAN,
320 .valid = {
321 .min_access_size = 4,
322 .max_access_size = 4,
323 },
e80cfcfc
FB
324};
325
f4b19cd0
BS
326static const VMStateDescription vmstate_timer = {
327 .name ="timer",
328 .version_id = 3,
329 .minimum_version_id = 3,
330 .minimum_version_id_old = 3,
331 .fields = (VMStateField []) {
332 VMSTATE_UINT64(limit, CPUTimerState),
333 VMSTATE_UINT32(count, CPUTimerState),
334 VMSTATE_UINT32(counthigh, CPUTimerState),
335 VMSTATE_UINT32(reached, CPUTimerState),
336 VMSTATE_UINT32(running, CPUTimerState),
337 VMSTATE_PTIMER(timer, CPUTimerState),
338 VMSTATE_END_OF_LIST()
7204ff9c 339 }
f4b19cd0 340};
e80cfcfc 341
f4b19cd0
BS
342static const VMStateDescription vmstate_slavio_timer = {
343 .name ="slavio_timer",
344 .version_id = 3,
345 .minimum_version_id = 3,
346 .minimum_version_id_old = 3,
347 .fields = (VMStateField []) {
348 VMSTATE_STRUCT_ARRAY(cputimer, SLAVIO_TIMERState, MAX_CPUS + 1, 3,
349 vmstate_timer, CPUTimerState),
350 VMSTATE_END_OF_LIST()
7204ff9c 351 }
f4b19cd0 352};
e80cfcfc 353
0e0bfeea 354static void slavio_timer_reset(DeviceState *d)
e80cfcfc 355{
0e0bfeea 356 SLAVIO_TIMERState *s = container_of(d, SLAVIO_TIMERState, busdev.qdev);
7204ff9c
BS
357 unsigned int i;
358 CPUTimerState *curr_timer;
359
360 for (i = 0; i <= MAX_CPUS; i++) {
361 curr_timer = &s->cputimer[i];
362 curr_timer->limit = 0;
363 curr_timer->count = 0;
364 curr_timer->reached = 0;
5933e8a9 365 if (i <= s->num_cpus) {
7204ff9c
BS
366 ptimer_set_limit(curr_timer->timer,
367 LIMIT_TO_PERIODS(TIMER_MAX_COUNT32), 1);
368 ptimer_run(curr_timer->timer, 0);
5933e8a9 369 curr_timer->running = 1;
7204ff9c 370 }
85e3023e 371 }
7204ff9c 372 s->cputimer_mode = 0;
e80cfcfc
FB
373}
374
81a322d4 375static int slavio_timer_init1(SysBusDevice *dev)
c70c59ee 376{
c70c59ee 377 SLAVIO_TIMERState *s = FROM_SYSBUS(SLAVIO_TIMERState, dev);
8d05ea8a 378 QEMUBH *bh;
7204ff9c
BS
379 unsigned int i;
380 TimerContext *tc;
e80cfcfc 381
7204ff9c 382 for (i = 0; i <= MAX_CPUS; i++) {
a3d12d07
BC
383 uint64_t size;
384 char timer_name[20];
385
7267c094 386 tc = g_malloc0(sizeof(TimerContext));
7204ff9c
BS
387 tc->s = s;
388 tc->timer_index = i;
c70c59ee 389
7204ff9c
BS
390 bh = qemu_bh_new(slavio_timer_irq, tc);
391 s->cputimer[i].timer = ptimer_init(bh);
392 ptimer_set_period(s->cputimer[i].timer, TIMER_PERIOD);
e80cfcfc 393
a3d12d07
BC
394 size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
395 snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
396 memory_region_init_io(&tc->iomem, &slavio_timer_mem_ops, tc,
397 timer_name, size);
750ecd44 398 sysbus_init_mmio(dev, &tc->iomem);
7204ff9c
BS
399
400 sysbus_init_irq(dev, &s->cputimer[i].irq);
c70c59ee
BS
401 }
402
81a322d4 403 return 0;
81732d19
BS
404}
405
c70c59ee
BS
406static SysBusDeviceInfo slavio_timer_info = {
407 .init = slavio_timer_init1,
408 .qdev.name = "slavio_timer",
409 .qdev.size = sizeof(SLAVIO_TIMERState),
0e0bfeea
BS
410 .qdev.vmsd = &vmstate_slavio_timer,
411 .qdev.reset = slavio_timer_reset,
ee6847d1 412 .qdev.props = (Property[]) {
18c637dc
GH
413 DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0),
414 DEFINE_PROP_END_OF_LIST(),
c70c59ee
BS
415 }
416};
417
418static void slavio_timer_register_devices(void)
419{
420 sysbus_register_withprop(&slavio_timer_info);
421}
422
423device_init(slavio_timer_register_devices)