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9fdf0c29
DG
1/*
2 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
3 *
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 * Copyright (c) 2010 David Gibson, IBM Corporation.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 *
26 */
27#include "sysemu.h"
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28#include "hw.h"
29#include "elf.h"
1422e32d 30#include "net/net.h"
6e270446 31#include "blockdev.h"
e97c3636
DG
32#include "cpus.h"
33#include "kvm.h"
34#include "kvm_ppc.h"
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35
36#include "hw/boards.h"
37#include "hw/ppc.h"
38#include "hw/loader.h"
39
40#include "hw/spapr.h"
4040ab72 41#include "hw/spapr_vio.h"
3384f95c 42#include "hw/spapr_pci.h"
b5cec4c5 43#include "hw/xics.h"
a2cb15b0 44#include "hw/pci/msi.h"
9fdf0c29 45
f61b4bed
AG
46#include "kvm.h"
47#include "kvm_ppc.h"
a2cb15b0 48#include "pci/pci.h"
f61b4bed 49
022c62cb 50#include "exec/address-spaces.h"
35139a59 51#include "hw/usb.h"
077805fa 52#include "qemu-config.h"
890c2b77 53
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54#include <libfdt.h>
55
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BH
56/* SLOF memory layout:
57 *
58 * SLOF raw image loaded at 0, copies its romfs right below the flat
59 * device-tree, then position SLOF itself 31M below that
60 *
61 * So we set FW_OVERHEAD to 40MB which should account for all of that
62 * and more
63 *
64 * We load our kernel at 4M, leaving space for SLOF initial image
65 */
9fdf0c29 66#define FDT_MAX_SIZE 0x10000
39ac8455 67#define RTAS_MAX_SIZE 0x10000
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68#define FW_MAX_SIZE 0x400000
69#define FW_FILE_NAME "slof.bin"
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BH
70#define FW_OVERHEAD 0x2800000
71#define KERNEL_LOAD_ADDR FW_MAX_SIZE
a9f8ad8f 72
4d8d5467 73#define MIN_RMA_SLOF 128UL
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74
75#define TIMEBASE_FREQ 512000000ULL
76
41019fec 77#define MAX_CPUS 256
4d8d5467 78#define XICS_IRQS 1024
9fdf0c29 79
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DG
80#define SPAPR_PCI_BUID 0x800000020000001ULL
81#define SPAPR_PCI_MEM_WIN_ADDR (0x10000000000ULL + 0xA0000000)
82#define SPAPR_PCI_MEM_WIN_SIZE 0x20000000
83#define SPAPR_PCI_IO_WIN_ADDR (0x10000000000ULL + 0x80000000)
0ee2c058 84#define SPAPR_PCI_MSI_WIN_ADDR (0x10000000000ULL + 0x90000000)
3384f95c 85
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DG
86#define PHANDLE_XICP 0x00001111
87
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88#define HTAB_SIZE(spapr) (1ULL << ((spapr)->htab_shift))
89
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DG
90sPAPREnvironment *spapr;
91
ff9d2afa 92int spapr_allocate_irq(int hint, bool lsi)
e6c866d4 93{
a307d594 94 int irq;
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DG
95
96 if (hint) {
97 irq = hint;
98 /* FIXME: we should probably check for collisions somehow */
99 } else {
100 irq = spapr->next_irq++;
101 }
102
a307d594
AK
103 /* Configure irq type */
104 if (!xics_get_qirq(spapr->icp, irq)) {
105 return 0;
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DG
106 }
107
ff9d2afa 108 xics_set_irq_type(spapr->icp, irq, lsi);
e6c866d4 109
a307d594 110 return irq;
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DG
111}
112
f4b9523b 113/* Allocate block of consequtive IRQs, returns a number of the first */
ff9d2afa 114int spapr_allocate_irq_block(int num, bool lsi)
f4b9523b
AK
115{
116 int first = -1;
117 int i;
118
119 for (i = 0; i < num; ++i) {
120 int irq;
121
ff9d2afa 122 irq = spapr_allocate_irq(0, lsi);
f4b9523b
AK
123 if (!irq) {
124 return -1;
125 }
126
127 if (0 == i) {
128 first = irq;
129 }
130
131 /* If the above doesn't create a consecutive block then that's
132 * an internal bug */
133 assert(irq == (first + i));
134 }
135
136 return first;
137}
138
7f763a5d 139static int spapr_fixup_cpu_dt(void *fdt, sPAPREnvironment *spapr)
6e806cc3
BR
140{
141 int ret = 0, offset;
e2684c0b 142 CPUPPCState *env;
6e806cc3
BR
143 char cpu_model[32];
144 int smt = kvmppc_smt_threads();
7f763a5d 145 uint32_t pft_size_prop[] = {0, cpu_to_be32(spapr->htab_shift)};
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BR
146
147 assert(spapr->cpu_model);
148
149 for (env = first_cpu; env != NULL; env = env->next_cpu) {
150 uint32_t associativity[] = {cpu_to_be32(0x5),
151 cpu_to_be32(0x0),
152 cpu_to_be32(0x0),
153 cpu_to_be32(0x0),
154 cpu_to_be32(env->numa_node),
155 cpu_to_be32(env->cpu_index)};
156
157 if ((env->cpu_index % smt) != 0) {
158 continue;
159 }
160
161 snprintf(cpu_model, 32, "/cpus/%s@%x", spapr->cpu_model,
162 env->cpu_index);
163
164 offset = fdt_path_offset(fdt, cpu_model);
165 if (offset < 0) {
166 return offset;
167 }
168
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DG
169 if (nb_numa_nodes > 1) {
170 ret = fdt_setprop(fdt, offset, "ibm,associativity", associativity,
171 sizeof(associativity));
172 if (ret < 0) {
173 return ret;
174 }
175 }
176
177 ret = fdt_setprop(fdt, offset, "ibm,pft-size",
178 pft_size_prop, sizeof(pft_size_prop));
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BR
179 if (ret < 0) {
180 return ret;
181 }
182 }
183 return ret;
184}
185
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BH
186
187static size_t create_page_sizes_prop(CPUPPCState *env, uint32_t *prop,
188 size_t maxsize)
189{
190 size_t maxcells = maxsize / sizeof(uint32_t);
191 int i, j, count;
192 uint32_t *p = prop;
193
194 for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
195 struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
196
197 if (!sps->page_shift) {
198 break;
199 }
200 for (count = 0; count < PPC_PAGE_SIZES_MAX_SZ; count++) {
201 if (sps->enc[count].page_shift == 0) {
202 break;
203 }
204 }
205 if ((p - prop) >= (maxcells - 3 - count * 2)) {
206 break;
207 }
208 *(p++) = cpu_to_be32(sps->page_shift);
209 *(p++) = cpu_to_be32(sps->slb_enc);
210 *(p++) = cpu_to_be32(count);
211 for (j = 0; j < count; j++) {
212 *(p++) = cpu_to_be32(sps->enc[j].page_shift);
213 *(p++) = cpu_to_be32(sps->enc[j].pte_enc);
214 }
215 }
216
217 return (p - prop) * sizeof(uint32_t);
218}
219
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DG
220#define _FDT(exp) \
221 do { \
222 int ret = (exp); \
223 if (ret < 0) { \
224 fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
225 #exp, fdt_strerror(ret)); \
226 exit(1); \
227 } \
228 } while (0)
229
230
a3467baa 231static void *spapr_create_fdt_skel(const char *cpu_model,
a8170e5e
AK
232 hwaddr initrd_base,
233 hwaddr initrd_size,
234 hwaddr kernel_size,
a3467baa 235 const char *boot_device,
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236 const char *kernel_cmdline,
237 uint32_t epow_irq)
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238{
239 void *fdt;
e2684c0b 240 CPUPPCState *env;
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241 uint32_t start_prop = cpu_to_be32(initrd_base);
242 uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
ee86dfee 243 char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
a3d0abae 244 "\0hcall-tce\0hcall-vio\0hcall-splpar\0hcall-bulk";
c73e3771 245 char qemu_hypertas_prop[] = "hcall-memop1";
7f763a5d 246 uint32_t refpoints[] = {cpu_to_be32(0x4), cpu_to_be32(0x4)};
b5cec4c5 247 uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
9fdf0c29 248 char *modelname;
7f763a5d 249 int i, smt = kvmppc_smt_threads();
6e806cc3 250 unsigned char vec5[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x80};
9fdf0c29 251
7267c094 252 fdt = g_malloc0(FDT_MAX_SIZE);
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DG
253 _FDT((fdt_create(fdt, FDT_MAX_SIZE)));
254
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BH
255 if (kernel_size) {
256 _FDT((fdt_add_reservemap_entry(fdt, KERNEL_LOAD_ADDR, kernel_size)));
257 }
258 if (initrd_size) {
259 _FDT((fdt_add_reservemap_entry(fdt, initrd_base, initrd_size)));
260 }
9fdf0c29
DG
261 _FDT((fdt_finish_reservemap(fdt)));
262
263 /* Root node */
264 _FDT((fdt_begin_node(fdt, "")));
265 _FDT((fdt_property_string(fdt, "device_type", "chrp")));
5d73dd66 266 _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)")));
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DG
267
268 _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
269 _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
270
271 /* /chosen */
272 _FDT((fdt_begin_node(fdt, "chosen")));
273
6e806cc3
BR
274 /* Set Form1_affinity */
275 _FDT((fdt_property(fdt, "ibm,architecture-vec-5", vec5, sizeof(vec5))));
276
9fdf0c29
DG
277 _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
278 _FDT((fdt_property(fdt, "linux,initrd-start",
279 &start_prop, sizeof(start_prop))));
280 _FDT((fdt_property(fdt, "linux,initrd-end",
281 &end_prop, sizeof(end_prop))));
4d8d5467
BH
282 if (kernel_size) {
283 uint64_t kprop[2] = { cpu_to_be64(KERNEL_LOAD_ADDR),
284 cpu_to_be64(kernel_size) };
9fdf0c29 285
4d8d5467
BH
286 _FDT((fdt_property(fdt, "qemu,boot-kernel", &kprop, sizeof(kprop))));
287 }
288 _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device)));
f28359d8
LZ
289 _FDT((fdt_property_cell(fdt, "qemu,graphic-width", graphic_width)));
290 _FDT((fdt_property_cell(fdt, "qemu,graphic-height", graphic_height)));
291 _FDT((fdt_property_cell(fdt, "qemu,graphic-depth", graphic_depth)));
3384f95c 292
9fdf0c29
DG
293 _FDT((fdt_end_node(fdt)));
294
9fdf0c29
DG
295 /* cpus */
296 _FDT((fdt_begin_node(fdt, "cpus")));
297
298 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
299 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
300
7267c094 301 modelname = g_strdup(cpu_model);
9fdf0c29
DG
302
303 for (i = 0; i < strlen(modelname); i++) {
304 modelname[i] = toupper(modelname[i]);
305 }
306
6e806cc3
BR
307 /* This is needed during FDT finalization */
308 spapr->cpu_model = g_strdup(modelname);
309
c7a5c0c9
DG
310 for (env = first_cpu; env != NULL; env = env->next_cpu) {
311 int index = env->cpu_index;
e97c3636
DG
312 uint32_t servers_prop[smp_threads];
313 uint32_t gservers_prop[smp_threads * 2];
9fdf0c29
DG
314 char *nodename;
315 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
316 0xffffffff, 0xffffffff};
0a8b2938
AG
317 uint32_t tbfreq = kvm_enabled() ? kvmppc_get_tbfreq() : TIMEBASE_FREQ;
318 uint32_t cpufreq = kvm_enabled() ? kvmppc_get_clockfreq() : 1000000000;
5af9873d
BH
319 uint32_t page_sizes_prop[64];
320 size_t page_sizes_prop_size;
9fdf0c29 321
e97c3636
DG
322 if ((index % smt) != 0) {
323 continue;
324 }
325
c7a5c0c9 326 if (asprintf(&nodename, "%s@%x", modelname, index) < 0) {
9fdf0c29
DG
327 fprintf(stderr, "Allocation failure\n");
328 exit(1);
329 }
330
331 _FDT((fdt_begin_node(fdt, nodename)));
332
333 free(nodename);
334
c7a5c0c9 335 _FDT((fdt_property_cell(fdt, "reg", index)));
9fdf0c29
DG
336 _FDT((fdt_property_string(fdt, "device_type", "cpu")));
337
338 _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
339 _FDT((fdt_property_cell(fdt, "dcache-block-size",
340 env->dcache_line_size)));
341 _FDT((fdt_property_cell(fdt, "icache-block-size",
342 env->icache_line_size)));
0a8b2938
AG
343 _FDT((fdt_property_cell(fdt, "timebase-frequency", tbfreq)));
344 _FDT((fdt_property_cell(fdt, "clock-frequency", cpufreq)));
9fdf0c29
DG
345 _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
346 _FDT((fdt_property_string(fdt, "status", "okay")));
347 _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
e97c3636
DG
348
349 /* Build interrupt servers and gservers properties */
350 for (i = 0; i < smp_threads; i++) {
351 servers_prop[i] = cpu_to_be32(index + i);
352 /* Hack, direct the group queues back to cpu 0 */
353 gservers_prop[i*2] = cpu_to_be32(index + i);
354 gservers_prop[i*2 + 1] = 0;
355 }
356 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-server#s",
357 servers_prop, sizeof(servers_prop))));
b5cec4c5 358 _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
e97c3636 359 gservers_prop, sizeof(gservers_prop))));
9fdf0c29 360
c7a5c0c9 361 if (env->mmu_model & POWERPC_MMU_1TSEG) {
9fdf0c29
DG
362 _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
363 segs, sizeof(segs))));
364 }
365
6659394f
DG
366 /* Advertise VMX/VSX (vector extensions) if available
367 * 0 / no property == no vector extensions
368 * 1 == VMX / Altivec available
369 * 2 == VSX available */
a7342588
DG
370 if (env->insns_flags & PPC_ALTIVEC) {
371 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
372
6659394f
DG
373 _FDT((fdt_property_cell(fdt, "ibm,vmx", vmx)));
374 }
375
376 /* Advertise DFP (Decimal Floating Point) if available
377 * 0 / no property == no DFP
378 * 1 == DFP available */
a7342588
DG
379 if (env->insns_flags2 & PPC2_DFP) {
380 _FDT((fdt_property_cell(fdt, "ibm,dfp", 1)));
6659394f
DG
381 }
382
5af9873d
BH
383 page_sizes_prop_size = create_page_sizes_prop(env, page_sizes_prop,
384 sizeof(page_sizes_prop));
385 if (page_sizes_prop_size) {
386 _FDT((fdt_property(fdt, "ibm,segment-page-sizes",
387 page_sizes_prop, page_sizes_prop_size)));
388 }
389
9fdf0c29
DG
390 _FDT((fdt_end_node(fdt)));
391 }
392
7267c094 393 g_free(modelname);
9fdf0c29
DG
394
395 _FDT((fdt_end_node(fdt)));
396
f43e3525
DG
397 /* RTAS */
398 _FDT((fdt_begin_node(fdt, "rtas")));
399
400 _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
401 sizeof(hypertas_prop))));
c73e3771
BH
402 _FDT((fdt_property(fdt, "qemu,hypertas-functions", qemu_hypertas_prop,
403 sizeof(qemu_hypertas_prop))));
f43e3525 404
6e806cc3
BR
405 _FDT((fdt_property(fdt, "ibm,associativity-reference-points",
406 refpoints, sizeof(refpoints))));
407
74d042e5
DG
408 _FDT((fdt_property_cell(fdt, "rtas-error-log-max", RTAS_ERROR_LOG_MAX)));
409
f43e3525
DG
410 _FDT((fdt_end_node(fdt)));
411
b5cec4c5 412 /* interrupt controller */
9dfef5aa 413 _FDT((fdt_begin_node(fdt, "interrupt-controller")));
b5cec4c5
DG
414
415 _FDT((fdt_property_string(fdt, "device_type",
416 "PowerPC-External-Interrupt-Presentation")));
417 _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
b5cec4c5
DG
418 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
419 _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
420 interrupt_server_ranges_prop,
421 sizeof(interrupt_server_ranges_prop))));
0c103f8e
DG
422 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 2)));
423 _FDT((fdt_property_cell(fdt, "linux,phandle", PHANDLE_XICP)));
424 _FDT((fdt_property_cell(fdt, "phandle", PHANDLE_XICP)));
b5cec4c5
DG
425
426 _FDT((fdt_end_node(fdt)));
427
4040ab72
DG
428 /* vdevice */
429 _FDT((fdt_begin_node(fdt, "vdevice")));
430
431 _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
432 _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
433 _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
434 _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5
DG
435 _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
436 _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72
DG
437
438 _FDT((fdt_end_node(fdt)));
439
74d042e5
DG
440 /* event-sources */
441 spapr_events_fdt_skel(fdt, epow_irq);
442
9fdf0c29
DG
443 _FDT((fdt_end_node(fdt))); /* close root node */
444 _FDT((fdt_finish(fdt)));
445
a3467baa
DG
446 return fdt;
447}
448
7f763a5d
DG
449static int spapr_populate_memory(sPAPREnvironment *spapr, void *fdt)
450{
451 uint32_t associativity[] = {cpu_to_be32(0x4), cpu_to_be32(0x0),
452 cpu_to_be32(0x0), cpu_to_be32(0x0),
453 cpu_to_be32(0x0)};
454 char mem_name[32];
a8170e5e 455 hwaddr node0_size, mem_start;
7f763a5d
DG
456 uint64_t mem_reg_property[2];
457 int i, off;
458
459 /* memory node(s) */
460 node0_size = (nb_numa_nodes > 1) ? node_mem[0] : ram_size;
461 if (spapr->rma_size > node0_size) {
462 spapr->rma_size = node0_size;
463 }
464
465 /* RMA */
466 mem_reg_property[0] = 0;
467 mem_reg_property[1] = cpu_to_be64(spapr->rma_size);
468 off = fdt_add_subnode(fdt, 0, "memory@0");
469 _FDT(off);
470 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
471 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
472 sizeof(mem_reg_property))));
473 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
474 sizeof(associativity))));
475
476 /* RAM: Node 0 */
477 if (node0_size > spapr->rma_size) {
478 mem_reg_property[0] = cpu_to_be64(spapr->rma_size);
479 mem_reg_property[1] = cpu_to_be64(node0_size - spapr->rma_size);
480
481 sprintf(mem_name, "memory@" TARGET_FMT_lx, spapr->rma_size);
482 off = fdt_add_subnode(fdt, 0, mem_name);
483 _FDT(off);
484 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
485 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
486 sizeof(mem_reg_property))));
487 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
488 sizeof(associativity))));
489 }
490
491 /* RAM: Node 1 and beyond */
492 mem_start = node0_size;
493 for (i = 1; i < nb_numa_nodes; i++) {
494 mem_reg_property[0] = cpu_to_be64(mem_start);
495 mem_reg_property[1] = cpu_to_be64(node_mem[i]);
496 associativity[3] = associativity[4] = cpu_to_be32(i);
497 sprintf(mem_name, "memory@" TARGET_FMT_lx, mem_start);
498 off = fdt_add_subnode(fdt, 0, mem_name);
499 _FDT(off);
500 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
501 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
502 sizeof(mem_reg_property))));
503 _FDT((fdt_setprop(fdt, off, "ibm,associativity", associativity,
504 sizeof(associativity))));
505 mem_start += node_mem[i];
506 }
507
508 return 0;
509}
510
a3467baa 511static void spapr_finalize_fdt(sPAPREnvironment *spapr,
a8170e5e
AK
512 hwaddr fdt_addr,
513 hwaddr rtas_addr,
514 hwaddr rtas_size)
a3467baa
DG
515{
516 int ret;
517 void *fdt;
3384f95c 518 sPAPRPHBState *phb;
a3467baa 519
7267c094 520 fdt = g_malloc(FDT_MAX_SIZE);
a3467baa
DG
521
522 /* open out the base tree into a temp buffer for the final tweaks */
523 _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE)));
4040ab72 524
7f763a5d
DG
525 ret = spapr_populate_memory(spapr, fdt);
526 if (ret < 0) {
527 fprintf(stderr, "couldn't setup memory nodes in fdt\n");
528 exit(1);
529 }
530
4040ab72
DG
531 ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
532 if (ret < 0) {
533 fprintf(stderr, "couldn't setup vio devices in fdt\n");
534 exit(1);
535 }
536
3384f95c 537 QLIST_FOREACH(phb, &spapr->phbs, list) {
e0fdbd7c 538 ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
3384f95c
DG
539 }
540
541 if (ret < 0) {
542 fprintf(stderr, "couldn't setup PCI devices in fdt\n");
543 exit(1);
544 }
545
39ac8455
DG
546 /* RTAS */
547 ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
548 if (ret < 0) {
549 fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
550 }
551
6e806cc3 552 /* Advertise NUMA via ibm,associativity */
7f763a5d
DG
553 ret = spapr_fixup_cpu_dt(fdt, spapr);
554 if (ret < 0) {
555 fprintf(stderr, "Couldn't finalize CPU device tree properties\n");
6e806cc3
BR
556 }
557
3fc5acde 558 if (!spapr->has_graphics) {
f28359d8
LZ
559 spapr_populate_chosen_stdout(fdt, spapr->vio_bus);
560 }
68f3a94c 561
4040ab72
DG
562 _FDT((fdt_pack(fdt)));
563
4d8d5467
BH
564 if (fdt_totalsize(fdt) > FDT_MAX_SIZE) {
565 hw_error("FDT too big ! 0x%x bytes (max is 0x%x)\n",
566 fdt_totalsize(fdt), FDT_MAX_SIZE);
567 exit(1);
568 }
569
a3467baa 570 cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt));
9fdf0c29 571
7267c094 572 g_free(fdt);
9fdf0c29
DG
573}
574
575static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
576{
577 return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
578}
579
1b14670a 580static void emulate_spapr_hypercall(PowerPCCPU *cpu)
9fdf0c29 581{
1b14670a
AF
582 CPUPPCState *env = &cpu->env;
583
efcb9383
DG
584 if (msr_pr) {
585 hcall_dprintf("Hypercall made with MSR[PR]=1\n");
586 env->gpr[3] = H_PRIVILEGE;
587 } else {
aa100fa4 588 env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]);
efcb9383 589 }
9fdf0c29
DG
590}
591
7f763a5d
DG
592static void spapr_reset_htab(sPAPREnvironment *spapr)
593{
594 long shift;
595
596 /* allocate hash page table. For now we always make this 16mb,
597 * later we should probably make it scale to the size of guest
598 * RAM */
599
600 shift = kvmppc_reset_htab(spapr->htab_shift);
601
602 if (shift > 0) {
603 /* Kernel handles htab, we don't need to allocate one */
604 spapr->htab_shift = shift;
605 } else {
606 if (!spapr->htab) {
607 /* Allocate an htab if we don't yet have one */
608 spapr->htab = qemu_memalign(HTAB_SIZE(spapr), HTAB_SIZE(spapr));
609 }
610
611 /* And clear it */
612 memset(spapr->htab, 0, HTAB_SIZE(spapr));
613 }
614
615 /* Update the RMA size if necessary */
616 if (spapr->vrma_adjust) {
617 spapr->rma_size = kvmppc_rma_size(ram_size, spapr->htab_shift);
618 }
9fdf0c29
DG
619}
620
c8787ad4 621static void ppc_spapr_reset(void)
a3467baa 622{
7f763a5d
DG
623 /* Reset the hash table & recalc the RMA */
624 spapr_reset_htab(spapr);
a3467baa 625
c8787ad4 626 qemu_devices_reset();
a3467baa
DG
627
628 /* Load the fdt */
629 spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr,
630 spapr->rtas_size);
631
632 /* Set up the entry state */
633 first_cpu->gpr[3] = spapr->fdt_addr;
634 first_cpu->gpr[5] = 0;
635 first_cpu->halted = 0;
636 first_cpu->nip = spapr->entry_point;
637
638}
639
1bba0dc9
AF
640static void spapr_cpu_reset(void *opaque)
641{
5b2038e0 642 PowerPCCPU *cpu = opaque;
048706d9 643 CPUPPCState *env = &cpu->env;
1bba0dc9 644
5b2038e0 645 cpu_reset(CPU(cpu));
048706d9
DG
646
647 /* All CPUs start halted. CPU0 is unhalted from the machine level
648 * reset code and the rest are explicitly started up by the guest
649 * using an RTAS call */
650 env->halted = 1;
651
652 env->spr[SPR_HIOR] = 0;
7f763a5d
DG
653
654 env->external_htab = spapr->htab;
655 env->htab_base = -1;
656 env->htab_mask = HTAB_SIZE(spapr) - 1;
657 env->spr[SPR_SDR1] = (unsigned long)spapr->htab |
658 (spapr->htab_shift - 18);
1bba0dc9
AF
659}
660
639e8102
DG
661static void spapr_create_nvram(sPAPREnvironment *spapr)
662{
663 QemuOpts *machine_opts;
664 DeviceState *dev;
665
666 dev = qdev_create(&spapr->vio_bus->bus, "spapr-nvram");
667
668 machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0);
669 if (machine_opts) {
670 const char *drivename;
671
672 drivename = qemu_opt_get(machine_opts, "nvram");
673 if (drivename) {
674 BlockDriverState *bs;
675
676 bs = bdrv_find(drivename);
677 if (!bs) {
678 fprintf(stderr, "No such block device \"%s\" for nvram\n",
679 drivename);
680 exit(1);
681 }
682 qdev_prop_set_drive_nofail(dev, "drive", bs);
683 }
684 }
685
686 qdev_init_nofail(dev);
687
688 spapr->nvram = (struct sPAPRNVRAM *)dev;
689}
690
8c57b867 691/* Returns whether we want to use VGA or not */
f28359d8
LZ
692static int spapr_vga_init(PCIBus *pci_bus)
693{
8c57b867 694 switch (vga_interface_type) {
8c57b867 695 case VGA_NONE:
1ddcae82
AJ
696 case VGA_STD:
697 return pci_vga_init(pci_bus) != NULL;
8c57b867 698 default:
f28359d8
LZ
699 fprintf(stderr, "This vga model is not supported,"
700 "currently it only supports -vga std\n");
8c57b867
AG
701 exit(0);
702 break;
f28359d8 703 }
f28359d8
LZ
704}
705
9fdf0c29 706/* pSeries LPAR / sPAPR hardware init */
5f072e1f 707static void ppc_spapr_init(QEMUMachineInitArgs *args)
9fdf0c29 708{
5f072e1f
EH
709 ram_addr_t ram_size = args->ram_size;
710 const char *cpu_model = args->cpu_model;
711 const char *kernel_filename = args->kernel_filename;
712 const char *kernel_cmdline = args->kernel_cmdline;
713 const char *initrd_filename = args->initrd_filename;
714 const char *boot_device = args->boot_device;
05769733 715 PowerPCCPU *cpu;
e2684c0b 716 CPUPPCState *env;
8c9f64df 717 PCIHostState *phb;
9fdf0c29 718 int i;
890c2b77
AK
719 MemoryRegion *sysmem = get_system_memory();
720 MemoryRegion *ram = g_new(MemoryRegion, 1);
a8170e5e 721 hwaddr rma_alloc_size;
4d8d5467
BH
722 uint32_t initrd_base = 0;
723 long kernel_size = 0, initrd_size = 0;
724 long load_limit, rtas_limit, fw_size;
39ac8455 725 char *filename;
9fdf0c29 726
0ee2c058
AK
727 msi_supported = true;
728
d43b45e2
DG
729 spapr = g_malloc0(sizeof(*spapr));
730 QLIST_INIT(&spapr->phbs);
731
9fdf0c29
DG
732 cpu_ppc_hypercall = emulate_spapr_hypercall;
733
354ac20a
DG
734 /* Allocate RMA if necessary */
735 rma_alloc_size = kvmppc_alloc_rma("ppc_spapr.rma", sysmem);
736
737 if (rma_alloc_size == -1) {
738 hw_error("qemu: Unable to create RMA\n");
739 exit(1);
740 }
7f763a5d 741
354ac20a 742 if (rma_alloc_size && (rma_alloc_size < ram_size)) {
7f763a5d 743 spapr->rma_size = rma_alloc_size;
354ac20a 744 } else {
7f763a5d
DG
745 spapr->rma_size = ram_size;
746
747 /* With KVM, we don't actually know whether KVM supports an
748 * unbounded RMA (PR KVM) or is limited by the hash table size
749 * (HV KVM using VRMA), so we always assume the latter
750 *
751 * In that case, we also limit the initial allocations for RTAS
752 * etc... to 256M since we have no way to know what the VRMA size
753 * is going to be as it depends on the size of the hash table
754 * isn't determined yet.
755 */
756 if (kvm_enabled()) {
757 spapr->vrma_adjust = 1;
758 spapr->rma_size = MIN(spapr->rma_size, 0x10000000);
759 }
354ac20a
DG
760 }
761
4d8d5467 762 /* We place the device tree and RTAS just below either the top of the RMA,
354ac20a
DG
763 * or just below 2GB, whichever is lowere, so that it can be
764 * processed with 32-bit real mode code if necessary */
7f763a5d 765 rtas_limit = MIN(spapr->rma_size, 0x80000000);
4d8d5467
BH
766 spapr->rtas_addr = rtas_limit - RTAS_MAX_SIZE;
767 spapr->fdt_addr = spapr->rtas_addr - FDT_MAX_SIZE;
768 load_limit = spapr->fdt_addr - FW_OVERHEAD;
9fdf0c29 769
382be75d
DG
770 /* We aim for a hash table of size 1/128 the size of RAM. The
771 * normal rule of thumb is 1/64 the size of RAM, but that's much
772 * more than needed for the Linux guests we support. */
773 spapr->htab_shift = 18; /* Minimum architected size */
774 while (spapr->htab_shift <= 46) {
775 if ((1ULL << (spapr->htab_shift + 7)) >= ram_size) {
776 break;
777 }
778 spapr->htab_shift++;
779 }
7f763a5d 780
9fdf0c29
DG
781 /* init CPUs */
782 if (cpu_model == NULL) {
6b7a2cf6 783 cpu_model = kvm_enabled() ? "host" : "POWER7";
9fdf0c29
DG
784 }
785 for (i = 0; i < smp_cpus; i++) {
05769733
AF
786 cpu = cpu_ppc_init(cpu_model);
787 if (cpu == NULL) {
9fdf0c29
DG
788 fprintf(stderr, "Unable to find PowerPC CPU definition\n");
789 exit(1);
790 }
05769733
AF
791 env = &cpu->env;
792
9fdf0c29
DG
793 /* Set time-base frequency to 512 MHz */
794 cpu_ppc_tb_init(env, TIMEBASE_FREQ);
9fdf0c29 795
048706d9 796 /* PAPR always has exception vectors in RAM not ROM */
9fdf0c29 797 env->hreset_excp_prefix = 0;
048706d9
DG
798
799 /* Tell KVM that we're in PAPR mode */
800 if (kvm_enabled()) {
801 kvmppc_set_papr(env);
802 }
803
804 qemu_register_reset(spapr_cpu_reset, cpu);
9fdf0c29
DG
805 }
806
807 /* allocate RAM */
f73a2575 808 spapr->ram_limit = ram_size;
354ac20a
DG
809 if (spapr->ram_limit > rma_alloc_size) {
810 ram_addr_t nonrma_base = rma_alloc_size;
811 ram_addr_t nonrma_size = spapr->ram_limit - rma_alloc_size;
812
c5705a77
AK
813 memory_region_init_ram(ram, "ppc_spapr.ram", nonrma_size);
814 vmstate_register_ram_global(ram);
354ac20a
DG
815 memory_region_add_subregion(sysmem, nonrma_base, ram);
816 }
9fdf0c29 817
39ac8455 818 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
a3467baa 819 spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr,
4d8d5467 820 rtas_limit - spapr->rtas_addr);
a3467baa 821 if (spapr->rtas_size < 0) {
39ac8455
DG
822 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
823 exit(1);
824 }
4d8d5467
BH
825 if (spapr->rtas_size > RTAS_MAX_SIZE) {
826 hw_error("RTAS too big ! 0x%lx bytes (max is 0x%x)\n",
827 spapr->rtas_size, RTAS_MAX_SIZE);
828 exit(1);
829 }
7267c094 830 g_free(filename);
39ac8455 831
4d8d5467 832
b5cec4c5 833 /* Set up Interrupt Controller */
c7a5c0c9 834 spapr->icp = xics_system_init(XICS_IRQS);
bf3bc4c4 835 spapr->next_irq = XICS_IRQ_BASE;
b5cec4c5 836
74d042e5
DG
837 /* Set up EPOW events infrastructure */
838 spapr_events_init(spapr);
839
ad0ebb91
DG
840 /* Set up IOMMU */
841 spapr_iommu_init();
842
b5cec4c5 843 /* Set up VIO bus */
4040ab72
DG
844 spapr->vio_bus = spapr_vio_bus_init();
845
277f9acf 846 for (i = 0; i < MAX_SERIAL_PORTS; i++) {
4040ab72 847 if (serial_hds[i]) {
d601fac4 848 spapr_vty_create(spapr->vio_bus, serial_hds[i]);
4040ab72
DG
849 }
850 }
9fdf0c29 851
639e8102
DG
852 /* We always have at least the nvram device on VIO */
853 spapr_create_nvram(spapr);
854
3384f95c 855 /* Set up PCI */
fa28f71b
AK
856 spapr_pci_rtas_init();
857
3384f95c
DG
858 spapr_create_phb(spapr, "pci", SPAPR_PCI_BUID,
859 SPAPR_PCI_MEM_WIN_ADDR,
860 SPAPR_PCI_MEM_WIN_SIZE,
0ee2c058
AK
861 SPAPR_PCI_IO_WIN_ADDR,
862 SPAPR_PCI_MSI_WIN_ADDR);
8558d942 863 phb = PCI_HOST_BRIDGE(QLIST_FIRST(&spapr->phbs));
3384f95c 864
277f9acf 865 for (i = 0; i < nb_nics; i++) {
8d90ad90
DG
866 NICInfo *nd = &nd_table[i];
867
868 if (!nd->model) {
7267c094 869 nd->model = g_strdup("ibmveth");
8d90ad90
DG
870 }
871
872 if (strcmp(nd->model, "ibmveth") == 0) {
d601fac4 873 spapr_vlan_create(spapr->vio_bus, nd);
8d90ad90 874 } else {
3384f95c 875 pci_nic_init_nofail(&nd_table[i], nd->model, NULL);
8d90ad90
DG
876 }
877 }
878
6e270446 879 for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
d601fac4 880 spapr_vscsi_create(spapr->vio_bus);
6e270446
BH
881 }
882
f28359d8 883 /* Graphics */
8c9f64df 884 if (spapr_vga_init(phb->bus)) {
3fc5acde 885 spapr->has_graphics = true;
f28359d8
LZ
886 }
887
094b287f 888 if (usb_enabled(spapr->has_graphics)) {
8c9f64df 889 pci_create_simple(phb->bus, -1, "pci-ohci");
35139a59
DG
890 if (spapr->has_graphics) {
891 usbdevice_create("keyboard");
892 usbdevice_create("mouse");
893 }
894 }
895
7f763a5d 896 if (spapr->rma_size < (MIN_RMA_SLOF << 20)) {
4d8d5467
BH
897 fprintf(stderr, "qemu: pSeries SLOF firmware requires >= "
898 "%ldM guest RMA (Real Mode Area memory)\n", MIN_RMA_SLOF);
899 exit(1);
900 }
901
9fdf0c29
DG
902 if (kernel_filename) {
903 uint64_t lowaddr = 0;
904
9fdf0c29
DG
905 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
906 NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
907 if (kernel_size < 0) {
a3467baa
DG
908 kernel_size = load_image_targphys(kernel_filename,
909 KERNEL_LOAD_ADDR,
4d8d5467 910 load_limit - KERNEL_LOAD_ADDR);
9fdf0c29
DG
911 }
912 if (kernel_size < 0) {
913 fprintf(stderr, "qemu: could not load kernel '%s'\n",
914 kernel_filename);
915 exit(1);
916 }
917
918 /* load initrd */
919 if (initrd_filename) {
4d8d5467
BH
920 /* Try to locate the initrd in the gap between the kernel
921 * and the firmware. Add a bit of space just in case
922 */
923 initrd_base = (KERNEL_LOAD_ADDR + kernel_size + 0x1ffff) & ~0xffff;
9fdf0c29 924 initrd_size = load_image_targphys(initrd_filename, initrd_base,
4d8d5467 925 load_limit - initrd_base);
9fdf0c29
DG
926 if (initrd_size < 0) {
927 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
928 initrd_filename);
929 exit(1);
930 }
931 } else {
932 initrd_base = 0;
933 initrd_size = 0;
934 }
4d8d5467 935 }
a3467baa 936
4d8d5467
BH
937 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, FW_FILE_NAME);
938 fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE);
939 if (fw_size < 0) {
940 hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
941 exit(1);
942 }
943 g_free(filename);
4d8d5467
BH
944
945 spapr->entry_point = 0x100;
946
9fdf0c29 947 /* Prepare the device tree */
7f763a5d 948 spapr->fdt_skel = spapr_create_fdt_skel(cpu_model,
a3467baa 949 initrd_base, initrd_size,
4d8d5467 950 kernel_size,
74d042e5
DG
951 boot_device, kernel_cmdline,
952 spapr->epow_irq);
a3467baa 953 assert(spapr->fdt_skel != NULL);
9fdf0c29
DG
954}
955
956static QEMUMachine spapr_machine = {
957 .name = "pseries",
958 .desc = "pSeries Logical Partition (PAPR compliant)",
959 .init = ppc_spapr_init,
c8787ad4 960 .reset = ppc_spapr_reset,
2d0d2837 961 .block_default_type = IF_SCSI,
9fdf0c29 962 .max_cpus = MAX_CPUS,
9fdf0c29
DG
963 .no_parallel = 1,
964};
965
966static void spapr_machine_init(void)
967{
968 qemu_register_machine(&spapr_machine);
969}
970
971machine_init(spapr_machine_init);