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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | #include "sysemu.h" | |
9fdf0c29 DG |
28 | #include "hw.h" |
29 | #include "elf.h" | |
30 | ||
31 | #include "hw/boards.h" | |
32 | #include "hw/ppc.h" | |
33 | #include "hw/loader.h" | |
34 | ||
35 | #include "hw/spapr.h" | |
4040ab72 | 36 | #include "hw/spapr_vio.h" |
9fdf0c29 DG |
37 | |
38 | #include <libfdt.h> | |
39 | ||
40 | #define KERNEL_LOAD_ADDR 0x00000000 | |
41 | #define INITRD_LOAD_ADDR 0x02800000 | |
42 | #define FDT_MAX_SIZE 0x10000 | |
43 | ||
44 | #define TIMEBASE_FREQ 512000000ULL | |
45 | ||
46 | #define MAX_CPUS 32 | |
47 | ||
48 | sPAPREnvironment *spapr; | |
49 | ||
50 | static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize, | |
51 | const char *cpu_model, CPUState *envs[], | |
52 | sPAPREnvironment *spapr, | |
53 | target_phys_addr_t initrd_base, | |
54 | target_phys_addr_t initrd_size, | |
55 | const char *kernel_cmdline) | |
56 | { | |
57 | void *fdt; | |
58 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) }; | |
59 | uint32_t start_prop = cpu_to_be32(initrd_base); | |
60 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
61 | int i; | |
62 | char *modelname; | |
4040ab72 | 63 | int ret; |
9fdf0c29 DG |
64 | |
65 | #define _FDT(exp) \ | |
66 | do { \ | |
67 | int ret = (exp); \ | |
68 | if (ret < 0) { \ | |
69 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
70 | #exp, fdt_strerror(ret)); \ | |
71 | exit(1); \ | |
72 | } \ | |
73 | } while (0) | |
74 | ||
75 | fdt = qemu_mallocz(FDT_MAX_SIZE); | |
76 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); | |
77 | ||
78 | _FDT((fdt_finish_reservemap(fdt))); | |
79 | ||
80 | /* Root node */ | |
81 | _FDT((fdt_begin_node(fdt, ""))); | |
82 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
83 | _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR"))); | |
84 | ||
85 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); | |
86 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
87 | ||
88 | /* /chosen */ | |
89 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
90 | ||
91 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); | |
92 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
93 | &start_prop, sizeof(start_prop)))); | |
94 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
95 | &end_prop, sizeof(end_prop)))); | |
96 | ||
97 | _FDT((fdt_end_node(fdt))); | |
98 | ||
99 | /* memory node */ | |
100 | _FDT((fdt_begin_node(fdt, "memory@0"))); | |
101 | ||
102 | _FDT((fdt_property_string(fdt, "device_type", "memory"))); | |
103 | _FDT((fdt_property(fdt, "reg", | |
104 | mem_reg_property, sizeof(mem_reg_property)))); | |
105 | ||
106 | _FDT((fdt_end_node(fdt))); | |
107 | ||
108 | /* cpus */ | |
109 | _FDT((fdt_begin_node(fdt, "cpus"))); | |
110 | ||
111 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
112 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
113 | ||
114 | modelname = qemu_strdup(cpu_model); | |
115 | ||
116 | for (i = 0; i < strlen(modelname); i++) { | |
117 | modelname[i] = toupper(modelname[i]); | |
118 | } | |
119 | ||
120 | for (i = 0; i < smp_cpus; i++) { | |
121 | CPUState *env = envs[i]; | |
122 | char *nodename; | |
123 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
124 | 0xffffffff, 0xffffffff}; | |
125 | ||
126 | if (asprintf(&nodename, "%s@%x", modelname, i) < 0) { | |
127 | fprintf(stderr, "Allocation failure\n"); | |
128 | exit(1); | |
129 | } | |
130 | ||
131 | _FDT((fdt_begin_node(fdt, nodename))); | |
132 | ||
133 | free(nodename); | |
134 | ||
135 | _FDT((fdt_property_cell(fdt, "reg", i))); | |
136 | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); | |
137 | ||
138 | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); | |
139 | _FDT((fdt_property_cell(fdt, "dcache-block-size", | |
140 | env->dcache_line_size))); | |
141 | _FDT((fdt_property_cell(fdt, "icache-block-size", | |
142 | env->icache_line_size))); | |
143 | _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ))); | |
144 | /* Hardcode CPU frequency for now. It's kind of arbitrary on | |
145 | * full emu, for kvm we should copy it from the host */ | |
146 | _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000))); | |
147 | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); | |
148 | _FDT((fdt_property_string(fdt, "status", "okay"))); | |
149 | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); | |
150 | ||
151 | if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) { | |
152 | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", | |
153 | segs, sizeof(segs)))); | |
154 | } | |
155 | ||
156 | _FDT((fdt_end_node(fdt))); | |
157 | } | |
158 | ||
159 | qemu_free(modelname); | |
160 | ||
161 | _FDT((fdt_end_node(fdt))); | |
162 | ||
4040ab72 DG |
163 | /* vdevice */ |
164 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
165 | ||
166 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
167 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
168 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
169 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
170 | ||
171 | _FDT((fdt_end_node(fdt))); | |
172 | ||
9fdf0c29 DG |
173 | _FDT((fdt_end_node(fdt))); /* close root node */ |
174 | _FDT((fdt_finish(fdt))); | |
175 | ||
4040ab72 DG |
176 | /* re-expand to allow for further tweaks */ |
177 | _FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE))); | |
178 | ||
179 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); | |
180 | if (ret < 0) { | |
181 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
182 | exit(1); | |
183 | } | |
184 | ||
185 | _FDT((fdt_pack(fdt))); | |
186 | ||
9fdf0c29 DG |
187 | *fdt_size = fdt_totalsize(fdt); |
188 | ||
189 | return fdt; | |
190 | } | |
191 | ||
192 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
193 | { | |
194 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
195 | } | |
196 | ||
197 | static void emulate_spapr_hypercall(CPUState *env) | |
198 | { | |
199 | env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); | |
200 | } | |
201 | ||
9fdf0c29 DG |
202 | /* pSeries LPAR / sPAPR hardware init */ |
203 | static void ppc_spapr_init(ram_addr_t ram_size, | |
204 | const char *boot_device, | |
205 | const char *kernel_filename, | |
206 | const char *kernel_cmdline, | |
207 | const char *initrd_filename, | |
208 | const char *cpu_model) | |
209 | { | |
210 | CPUState *envs[MAX_CPUS]; | |
211 | void *fdt; | |
212 | int i; | |
213 | ram_addr_t ram_offset; | |
214 | target_phys_addr_t fdt_addr; | |
215 | uint32_t kernel_base, initrd_base; | |
216 | long kernel_size, initrd_size; | |
217 | int fdt_size; | |
218 | ||
219 | spapr = qemu_malloc(sizeof(*spapr)); | |
220 | cpu_ppc_hypercall = emulate_spapr_hypercall; | |
221 | ||
222 | /* We place the device tree just below either the top of RAM, or | |
223 | * 2GB, so that it can be processed with 32-bit code if | |
224 | * necessary */ | |
225 | fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE; | |
226 | ||
227 | /* init CPUs */ | |
228 | if (cpu_model == NULL) { | |
229 | cpu_model = "POWER7"; | |
230 | } | |
231 | for (i = 0; i < smp_cpus; i++) { | |
232 | CPUState *env = cpu_init(cpu_model); | |
233 | ||
234 | if (!env) { | |
235 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
236 | exit(1); | |
237 | } | |
238 | /* Set time-base frequency to 512 MHz */ | |
239 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
240 | qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); | |
241 | ||
242 | env->hreset_vector = 0x60; | |
243 | env->hreset_excp_prefix = 0; | |
244 | env->gpr[3] = i; | |
245 | ||
246 | envs[i] = env; | |
247 | } | |
248 | ||
249 | /* allocate RAM */ | |
250 | ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size); | |
251 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
252 | ||
4040ab72 DG |
253 | spapr->vio_bus = spapr_vio_bus_init(); |
254 | ||
255 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { | |
256 | if (serial_hds[i]) { | |
257 | spapr_vty_create(spapr->vio_bus, i, serial_hds[i]); | |
258 | } | |
259 | } | |
9fdf0c29 DG |
260 | |
261 | if (kernel_filename) { | |
262 | uint64_t lowaddr = 0; | |
263 | ||
264 | kernel_base = KERNEL_LOAD_ADDR; | |
265 | ||
266 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, | |
267 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
268 | if (kernel_size < 0) { | |
269 | kernel_size = load_image_targphys(kernel_filename, kernel_base, | |
270 | ram_size - kernel_base); | |
271 | } | |
272 | if (kernel_size < 0) { | |
273 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
274 | kernel_filename); | |
275 | exit(1); | |
276 | } | |
277 | ||
278 | /* load initrd */ | |
279 | if (initrd_filename) { | |
280 | initrd_base = INITRD_LOAD_ADDR; | |
281 | initrd_size = load_image_targphys(initrd_filename, initrd_base, | |
282 | ram_size - initrd_base); | |
283 | if (initrd_size < 0) { | |
284 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
285 | initrd_filename); | |
286 | exit(1); | |
287 | } | |
288 | } else { | |
289 | initrd_base = 0; | |
290 | initrd_size = 0; | |
291 | } | |
9fdf0c29 DG |
292 | } else { |
293 | fprintf(stderr, "pSeries machine needs -kernel for now"); | |
294 | exit(1); | |
295 | } | |
296 | ||
297 | /* Prepare the device tree */ | |
298 | fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr, | |
299 | initrd_base, initrd_size, kernel_cmdline); | |
300 | assert(fdt != NULL); | |
301 | ||
302 | cpu_physical_memory_write(fdt_addr, fdt, fdt_size); | |
303 | ||
304 | qemu_free(fdt); | |
305 | ||
306 | envs[0]->gpr[3] = fdt_addr; | |
307 | envs[0]->gpr[5] = 0; | |
308 | envs[0]->hreset_vector = kernel_base; | |
309 | } | |
310 | ||
311 | static QEMUMachine spapr_machine = { | |
312 | .name = "pseries", | |
313 | .desc = "pSeries Logical Partition (PAPR compliant)", | |
314 | .init = ppc_spapr_init, | |
315 | .max_cpus = MAX_CPUS, | |
316 | .no_vga = 1, | |
317 | .no_parallel = 1, | |
318 | }; | |
319 | ||
320 | static void spapr_machine_init(void) | |
321 | { | |
322 | qemu_register_machine(&spapr_machine); | |
323 | } | |
324 | ||
325 | machine_init(spapr_machine_init); |