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Commit | Line | Data |
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9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | #include "sysemu.h" | |
9fdf0c29 DG |
28 | #include "hw.h" |
29 | #include "elf.h" | |
8d90ad90 | 30 | #include "net.h" |
6e270446 | 31 | #include "blockdev.h" |
9fdf0c29 DG |
32 | |
33 | #include "hw/boards.h" | |
34 | #include "hw/ppc.h" | |
35 | #include "hw/loader.h" | |
36 | ||
37 | #include "hw/spapr.h" | |
4040ab72 | 38 | #include "hw/spapr_vio.h" |
b5cec4c5 | 39 | #include "hw/xics.h" |
9fdf0c29 DG |
40 | |
41 | #include <libfdt.h> | |
42 | ||
43 | #define KERNEL_LOAD_ADDR 0x00000000 | |
44 | #define INITRD_LOAD_ADDR 0x02800000 | |
45 | #define FDT_MAX_SIZE 0x10000 | |
39ac8455 | 46 | #define RTAS_MAX_SIZE 0x10000 |
a9f8ad8f DG |
47 | #define FW_MAX_SIZE 0x400000 |
48 | #define FW_FILE_NAME "slof.bin" | |
49 | ||
50 | #define MIN_RAM_SLOF 512UL | |
9fdf0c29 DG |
51 | |
52 | #define TIMEBASE_FREQ 512000000ULL | |
53 | ||
54 | #define MAX_CPUS 32 | |
b5cec4c5 | 55 | #define XICS_IRQS 1024 |
9fdf0c29 DG |
56 | |
57 | sPAPREnvironment *spapr; | |
58 | ||
59 | static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize, | |
60 | const char *cpu_model, CPUState *envs[], | |
61 | sPAPREnvironment *spapr, | |
62 | target_phys_addr_t initrd_base, | |
63 | target_phys_addr_t initrd_size, | |
a9f8ad8f | 64 | const char *boot_device, |
f43e3525 | 65 | const char *kernel_cmdline, |
39ac8455 DG |
66 | target_phys_addr_t rtas_addr, |
67 | target_phys_addr_t rtas_size, | |
f43e3525 | 68 | long hash_shift) |
9fdf0c29 DG |
69 | { |
70 | void *fdt; | |
71 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) }; | |
72 | uint32_t start_prop = cpu_to_be32(initrd_base); | |
73 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
f43e3525 | 74 | uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)}; |
ee86dfee | 75 | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
ed120055 | 76 | "\0hcall-tce\0hcall-vio\0hcall-splpar"; |
b5cec4c5 | 77 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; |
9fdf0c29 DG |
78 | int i; |
79 | char *modelname; | |
4040ab72 | 80 | int ret; |
9fdf0c29 DG |
81 | |
82 | #define _FDT(exp) \ | |
83 | do { \ | |
84 | int ret = (exp); \ | |
85 | if (ret < 0) { \ | |
86 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
87 | #exp, fdt_strerror(ret)); \ | |
88 | exit(1); \ | |
89 | } \ | |
90 | } while (0) | |
91 | ||
92 | fdt = qemu_mallocz(FDT_MAX_SIZE); | |
93 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); | |
94 | ||
95 | _FDT((fdt_finish_reservemap(fdt))); | |
96 | ||
97 | /* Root node */ | |
98 | _FDT((fdt_begin_node(fdt, ""))); | |
99 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
100 | _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR"))); | |
101 | ||
102 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); | |
103 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
104 | ||
105 | /* /chosen */ | |
106 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
107 | ||
108 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); | |
109 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
110 | &start_prop, sizeof(start_prop)))); | |
111 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
112 | &end_prop, sizeof(end_prop)))); | |
a9f8ad8f | 113 | _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); |
9fdf0c29 DG |
114 | |
115 | _FDT((fdt_end_node(fdt))); | |
116 | ||
117 | /* memory node */ | |
118 | _FDT((fdt_begin_node(fdt, "memory@0"))); | |
119 | ||
120 | _FDT((fdt_property_string(fdt, "device_type", "memory"))); | |
121 | _FDT((fdt_property(fdt, "reg", | |
122 | mem_reg_property, sizeof(mem_reg_property)))); | |
123 | ||
124 | _FDT((fdt_end_node(fdt))); | |
125 | ||
126 | /* cpus */ | |
127 | _FDT((fdt_begin_node(fdt, "cpus"))); | |
128 | ||
129 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
130 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
131 | ||
132 | modelname = qemu_strdup(cpu_model); | |
133 | ||
134 | for (i = 0; i < strlen(modelname); i++) { | |
135 | modelname[i] = toupper(modelname[i]); | |
136 | } | |
137 | ||
138 | for (i = 0; i < smp_cpus; i++) { | |
139 | CPUState *env = envs[i]; | |
b5cec4c5 | 140 | uint32_t gserver_prop[] = {cpu_to_be32(i), 0}; /* HACK! */ |
9fdf0c29 DG |
141 | char *nodename; |
142 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
143 | 0xffffffff, 0xffffffff}; | |
144 | ||
145 | if (asprintf(&nodename, "%s@%x", modelname, i) < 0) { | |
146 | fprintf(stderr, "Allocation failure\n"); | |
147 | exit(1); | |
148 | } | |
149 | ||
150 | _FDT((fdt_begin_node(fdt, nodename))); | |
151 | ||
152 | free(nodename); | |
153 | ||
154 | _FDT((fdt_property_cell(fdt, "reg", i))); | |
155 | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); | |
156 | ||
157 | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); | |
158 | _FDT((fdt_property_cell(fdt, "dcache-block-size", | |
159 | env->dcache_line_size))); | |
160 | _FDT((fdt_property_cell(fdt, "icache-block-size", | |
161 | env->icache_line_size))); | |
162 | _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ))); | |
163 | /* Hardcode CPU frequency for now. It's kind of arbitrary on | |
164 | * full emu, for kvm we should copy it from the host */ | |
165 | _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000))); | |
166 | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); | |
f43e3525 DG |
167 | _FDT((fdt_property(fdt, "ibm,pft-size", |
168 | pft_size_prop, sizeof(pft_size_prop)))); | |
9fdf0c29 DG |
169 | _FDT((fdt_property_string(fdt, "status", "okay"))); |
170 | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); | |
b5cec4c5 DG |
171 | _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", i))); |
172 | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", | |
173 | gserver_prop, sizeof(gserver_prop)))); | |
9fdf0c29 DG |
174 | |
175 | if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) { | |
176 | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", | |
177 | segs, sizeof(segs)))); | |
178 | } | |
179 | ||
180 | _FDT((fdt_end_node(fdt))); | |
181 | } | |
182 | ||
183 | qemu_free(modelname); | |
184 | ||
185 | _FDT((fdt_end_node(fdt))); | |
186 | ||
f43e3525 DG |
187 | /* RTAS */ |
188 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
189 | ||
190 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, | |
191 | sizeof(hypertas_prop)))); | |
192 | ||
193 | _FDT((fdt_end_node(fdt))); | |
194 | ||
b5cec4c5 DG |
195 | /* interrupt controller */ |
196 | _FDT((fdt_begin_node(fdt, "interrupt-controller@0"))); | |
197 | ||
198 | _FDT((fdt_property_string(fdt, "device_type", | |
199 | "PowerPC-External-Interrupt-Presentation"))); | |
200 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
201 | _FDT((fdt_property_cell(fdt, "reg", 0))); | |
202 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
203 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
204 | interrupt_server_ranges_prop, | |
205 | sizeof(interrupt_server_ranges_prop)))); | |
206 | ||
207 | _FDT((fdt_end_node(fdt))); | |
208 | ||
4040ab72 DG |
209 | /* vdevice */ |
210 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
211 | ||
212 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
213 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
214 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
215 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
216 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
217 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
218 | |
219 | _FDT((fdt_end_node(fdt))); | |
220 | ||
9fdf0c29 DG |
221 | _FDT((fdt_end_node(fdt))); /* close root node */ |
222 | _FDT((fdt_finish(fdt))); | |
223 | ||
4040ab72 DG |
224 | /* re-expand to allow for further tweaks */ |
225 | _FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE))); | |
226 | ||
227 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); | |
228 | if (ret < 0) { | |
229 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
230 | exit(1); | |
231 | } | |
232 | ||
39ac8455 DG |
233 | /* RTAS */ |
234 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
235 | if (ret < 0) { | |
236 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
237 | } | |
238 | ||
4040ab72 DG |
239 | _FDT((fdt_pack(fdt))); |
240 | ||
9fdf0c29 DG |
241 | *fdt_size = fdt_totalsize(fdt); |
242 | ||
243 | return fdt; | |
244 | } | |
245 | ||
246 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
247 | { | |
248 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
249 | } | |
250 | ||
251 | static void emulate_spapr_hypercall(CPUState *env) | |
252 | { | |
253 | env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); | |
254 | } | |
255 | ||
9fdf0c29 DG |
256 | /* pSeries LPAR / sPAPR hardware init */ |
257 | static void ppc_spapr_init(ram_addr_t ram_size, | |
258 | const char *boot_device, | |
259 | const char *kernel_filename, | |
260 | const char *kernel_cmdline, | |
261 | const char *initrd_filename, | |
262 | const char *cpu_model) | |
263 | { | |
264 | CPUState *envs[MAX_CPUS]; | |
f43e3525 | 265 | void *fdt, *htab; |
9fdf0c29 DG |
266 | int i; |
267 | ram_addr_t ram_offset; | |
39ac8455 | 268 | target_phys_addr_t fdt_addr, rtas_addr; |
9fdf0c29 | 269 | uint32_t kernel_base, initrd_base; |
a9f8ad8f | 270 | long kernel_size, initrd_size, htab_size, rtas_size, fw_size; |
f43e3525 | 271 | long pteg_shift = 17; |
9fdf0c29 | 272 | int fdt_size; |
39ac8455 | 273 | char *filename; |
0201e2da | 274 | int irq = 16; |
9fdf0c29 DG |
275 | |
276 | spapr = qemu_malloc(sizeof(*spapr)); | |
277 | cpu_ppc_hypercall = emulate_spapr_hypercall; | |
278 | ||
279 | /* We place the device tree just below either the top of RAM, or | |
280 | * 2GB, so that it can be processed with 32-bit code if | |
281 | * necessary */ | |
282 | fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE; | |
39ac8455 DG |
283 | /* RTAS goes just below that */ |
284 | rtas_addr = fdt_addr - RTAS_MAX_SIZE; | |
9fdf0c29 DG |
285 | |
286 | /* init CPUs */ | |
287 | if (cpu_model == NULL) { | |
288 | cpu_model = "POWER7"; | |
289 | } | |
290 | for (i = 0; i < smp_cpus; i++) { | |
291 | CPUState *env = cpu_init(cpu_model); | |
292 | ||
293 | if (!env) { | |
294 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
295 | exit(1); | |
296 | } | |
297 | /* Set time-base frequency to 512 MHz */ | |
298 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
299 | qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); | |
300 | ||
301 | env->hreset_vector = 0x60; | |
302 | env->hreset_excp_prefix = 0; | |
303 | env->gpr[3] = i; | |
304 | ||
305 | envs[i] = env; | |
306 | } | |
307 | ||
308 | /* allocate RAM */ | |
309 | ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size); | |
310 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
311 | ||
f43e3525 DG |
312 | /* allocate hash page table. For now we always make this 16mb, |
313 | * later we should probably make it scale to the size of guest | |
314 | * RAM */ | |
315 | htab_size = 1ULL << (pteg_shift + 7); | |
316 | htab = qemu_mallocz(htab_size); | |
317 | ||
318 | for (i = 0; i < smp_cpus; i++) { | |
319 | envs[i]->external_htab = htab; | |
320 | envs[i]->htab_base = -1; | |
321 | envs[i]->htab_mask = htab_size - 1; | |
322 | } | |
323 | ||
39ac8455 DG |
324 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
325 | rtas_size = load_image_targphys(filename, rtas_addr, ram_size - rtas_addr); | |
326 | if (rtas_size < 0) { | |
327 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); | |
328 | exit(1); | |
329 | } | |
330 | qemu_free(filename); | |
331 | ||
b5cec4c5 DG |
332 | /* Set up Interrupt Controller */ |
333 | spapr->icp = xics_system_init(smp_cpus, envs, XICS_IRQS); | |
334 | ||
335 | /* Set up VIO bus */ | |
4040ab72 DG |
336 | spapr->vio_bus = spapr_vio_bus_init(); |
337 | ||
0201e2da | 338 | for (i = 0; i < MAX_SERIAL_PORTS; i++, irq++) { |
4040ab72 | 339 | if (serial_hds[i]) { |
0201e2da DG |
340 | spapr_vty_create(spapr->vio_bus, i, serial_hds[i], |
341 | xics_find_qirq(spapr->icp, irq), irq); | |
4040ab72 DG |
342 | } |
343 | } | |
9fdf0c29 | 344 | |
8d90ad90 DG |
345 | for (i = 0; i < nb_nics; i++, irq++) { |
346 | NICInfo *nd = &nd_table[i]; | |
347 | ||
348 | if (!nd->model) { | |
349 | nd->model = qemu_strdup("ibmveth"); | |
350 | } | |
351 | ||
352 | if (strcmp(nd->model, "ibmveth") == 0) { | |
353 | spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd, | |
354 | xics_find_qirq(spapr->icp, irq), irq); | |
355 | } else { | |
356 | fprintf(stderr, "pSeries (sPAPR) platform does not support " | |
357 | "NIC model '%s' (only ibmveth is supported)\n", | |
358 | nd->model); | |
359 | exit(1); | |
360 | } | |
361 | } | |
362 | ||
6e270446 BH |
363 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
364 | spapr_vscsi_create(spapr->vio_bus, 0x2000 + i, | |
365 | xics_find_qirq(spapr->icp, irq), irq); | |
366 | irq++; | |
367 | } | |
368 | ||
9fdf0c29 DG |
369 | if (kernel_filename) { |
370 | uint64_t lowaddr = 0; | |
371 | ||
372 | kernel_base = KERNEL_LOAD_ADDR; | |
373 | ||
374 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, | |
375 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
376 | if (kernel_size < 0) { | |
377 | kernel_size = load_image_targphys(kernel_filename, kernel_base, | |
378 | ram_size - kernel_base); | |
379 | } | |
380 | if (kernel_size < 0) { | |
381 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
382 | kernel_filename); | |
383 | exit(1); | |
384 | } | |
385 | ||
386 | /* load initrd */ | |
387 | if (initrd_filename) { | |
388 | initrd_base = INITRD_LOAD_ADDR; | |
389 | initrd_size = load_image_targphys(initrd_filename, initrd_base, | |
390 | ram_size - initrd_base); | |
391 | if (initrd_size < 0) { | |
392 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
393 | initrd_filename); | |
394 | exit(1); | |
395 | } | |
396 | } else { | |
397 | initrd_base = 0; | |
398 | initrd_size = 0; | |
399 | } | |
9fdf0c29 | 400 | } else { |
a9f8ad8f DG |
401 | if (ram_size < (MIN_RAM_SLOF << 20)) { |
402 | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " | |
403 | "%ldM guest RAM\n", MIN_RAM_SLOF); | |
404 | exit(1); | |
405 | } | |
406 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "slof.bin"); | |
407 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); | |
408 | if (fw_size < 0) { | |
409 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); | |
410 | exit(1); | |
411 | } | |
412 | qemu_free(filename); | |
413 | kernel_base = 0x100; | |
414 | initrd_base = 0; | |
415 | initrd_size = 0; | |
416 | ||
417 | /* SLOF will startup the secondary CPUs using RTAS, | |
418 | rather than expecting a kexec() style entry */ | |
419 | for (i = 0; i < smp_cpus; i++) { | |
420 | envs[i]->halted = 1; | |
421 | } | |
9fdf0c29 DG |
422 | } |
423 | ||
424 | /* Prepare the device tree */ | |
425 | fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr, | |
a9f8ad8f DG |
426 | initrd_base, initrd_size, |
427 | boot_device, kernel_cmdline, | |
39ac8455 | 428 | rtas_addr, rtas_size, pteg_shift + 7); |
9fdf0c29 DG |
429 | assert(fdt != NULL); |
430 | ||
431 | cpu_physical_memory_write(fdt_addr, fdt, fdt_size); | |
432 | ||
433 | qemu_free(fdt); | |
434 | ||
435 | envs[0]->gpr[3] = fdt_addr; | |
436 | envs[0]->gpr[5] = 0; | |
437 | envs[0]->hreset_vector = kernel_base; | |
a9f8ad8f | 438 | envs[0]->halted = 0; |
9fdf0c29 DG |
439 | } |
440 | ||
441 | static QEMUMachine spapr_machine = { | |
442 | .name = "pseries", | |
443 | .desc = "pSeries Logical Partition (PAPR compliant)", | |
444 | .init = ppc_spapr_init, | |
445 | .max_cpus = MAX_CPUS, | |
446 | .no_vga = 1, | |
447 | .no_parallel = 1, | |
6e270446 | 448 | .use_scsi = 1, |
9fdf0c29 DG |
449 | }; |
450 | ||
451 | static void spapr_machine_init(void) | |
452 | { | |
453 | qemu_register_machine(&spapr_machine); | |
454 | } | |
455 | ||
456 | machine_init(spapr_machine_init); |