[mirror_qemu.git] / hw / spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 * Copyright (c) 2010 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */
#include "sysemu.h"
#include "hw.h"
#include "elf.h"
#include "net.h"

#include "hw/boards.h"
#include "hw/ppc.h"
#include "hw/loader.h"

#include "hw/spapr.h"
#include "hw/spapr_vio.h"
#include "hw/xics.h"

#include <libfdt.h>

#define KERNEL_LOAD_ADDR        0x00000000
#define INITRD_LOAD_ADDR        0x02800000
#define FDT_MAX_SIZE            0x10000
#define RTAS_MAX_SIZE           0x10000

#define TIMEBASE_FREQ           512000000ULL

#define MAX_CPUS                32
#define XICS_IRQS		1024

sPAPREnvironment *spapr;

static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize,
                              const char *cpu_model, CPUState *envs[],
                              sPAPREnvironment *spapr,
                              target_phys_addr_t initrd_base,
                              target_phys_addr_t initrd_size,
                              const char *kernel_cmdline,
                              target_phys_addr_t rtas_addr,
                              target_phys_addr_t rtas_size,
                              long hash_shift)
{
    void *fdt;
    uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
    uint32_t start_prop = cpu_to_be32(initrd_base);
    uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
    uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
    char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
        "\0hcall-tce\0hcall-vio";
    uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
    int i;
    char *modelname;
    int ret;

#define _FDT(exp) \
    do { \
        int ret = (exp);                                           \
        if (ret < 0) {                                             \
            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
                    #exp, fdt_strerror(ret));                      \
            exit(1);                                               \
        }                                                          \
    } while (0)

    fdt = qemu_mallocz(FDT_MAX_SIZE);
    _FDT((fdt_create(fdt, FDT_MAX_SIZE)));

    _FDT((fdt_finish_reservemap(fdt)));

    /* Root node */
    _FDT((fdt_begin_node(fdt, "")));
    _FDT((fdt_property_string(fdt, "device_type", "chrp")));
    _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));

    /* /chosen */
    _FDT((fdt_begin_node(fdt, "chosen")));

    _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
    _FDT((fdt_property(fdt, "linux,initrd-start",
                       &start_prop, sizeof(start_prop))));
    _FDT((fdt_property(fdt, "linux,initrd-end",
                       &end_prop, sizeof(end_prop))));

    _FDT((fdt_end_node(fdt)));

    /* memory node */
    _FDT((fdt_begin_node(fdt, "memory@0")));

    _FDT((fdt_property_string(fdt, "device_type", "memory")));
    _FDT((fdt_property(fdt, "reg",
                       mem_reg_property, sizeof(mem_reg_property))));

    _FDT((fdt_end_node(fdt)));

    /* cpus */
    _FDT((fdt_begin_node(fdt, "cpus")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));

    modelname = qemu_strdup(cpu_model);

    for (i = 0; i < strlen(modelname); i++) {
        modelname[i] = toupper(modelname[i]);
    }

    for (i = 0; i < smp_cpus; i++) {
        CPUState *env = envs[i];
        uint32_t gserver_prop[] = {cpu_to_be32(i), 0}; /* HACK! */
        char *nodename;
        uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
                           0xffffffff, 0xffffffff};

        if (asprintf(&nodename, "%s@%x", modelname, i) < 0) {
            fprintf(stderr, "Allocation failure\n");
            exit(1);
        }

        _FDT((fdt_begin_node(fdt, nodename)));

        free(nodename);

        _FDT((fdt_property_cell(fdt, "reg", i)));
        _FDT((fdt_property_string(fdt, "device_type", "cpu")));

        _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
        _FDT((fdt_property_cell(fdt, "dcache-block-size",
                                env->dcache_line_size)));
        _FDT((fdt_property_cell(fdt, "icache-block-size",
                                env->icache_line_size)));
        _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
        /* Hardcode CPU frequency for now.  It's kind of arbitrary on
         * full emu, for kvm we should copy it from the host */
        _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000)));
        _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
        _FDT((fdt_property(fdt, "ibm,pft-size",
                           pft_size_prop, sizeof(pft_size_prop))));
        _FDT((fdt_property_string(fdt, "status", "okay")));
        _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
        _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", i)));
        _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
                           gserver_prop, sizeof(gserver_prop))));

        if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) {
            _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
                               segs, sizeof(segs))));
        }

        _FDT((fdt_end_node(fdt)));
    }

    qemu_free(modelname);

    _FDT((fdt_end_node(fdt)));

    /* RTAS */
    _FDT((fdt_begin_node(fdt, "rtas")));

    _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
                       sizeof(hypertas_prop))));

    _FDT((fdt_end_node(fdt)));

    /* interrupt controller */
    _FDT((fdt_begin_node(fdt, "interrupt-controller@0")));

    _FDT((fdt_property_string(fdt, "device_type",
                              "PowerPC-External-Interrupt-Presentation")));
    _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
    _FDT((fdt_property_cell(fdt, "reg", 0)));
    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
    _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
                       interrupt_server_ranges_prop,
                       sizeof(interrupt_server_ranges_prop))));

    _FDT((fdt_end_node(fdt)));

    /* vdevice */
    _FDT((fdt_begin_node(fdt, "vdevice")));

    _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
    _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));

    _FDT((fdt_end_node(fdt)));

    _FDT((fdt_end_node(fdt))); /* close root node */
    _FDT((fdt_finish(fdt)));

    /* re-expand to allow for further tweaks */
    _FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE)));

    ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
    if (ret < 0) {
        fprintf(stderr, "couldn't setup vio devices in fdt\n");
        exit(1);
    }

    /* RTAS */
    ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
    if (ret < 0) {
        fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
    }

    _FDT((fdt_pack(fdt)));

    *fdt_size = fdt_totalsize(fdt);

    return fdt;
}

static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
{
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}

static void emulate_spapr_hypercall(CPUState *env)
{
    env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
}

/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(ram_addr_t ram_size,
                           const char *boot_device,
                           const char *kernel_filename,
                           const char *kernel_cmdline,
                           const char *initrd_filename,
                           const char *cpu_model)
{
    CPUState *envs[MAX_CPUS];
    void *fdt, *htab;
    int i;
    ram_addr_t ram_offset;
    target_phys_addr_t fdt_addr, rtas_addr;
    uint32_t kernel_base, initrd_base;
    long kernel_size, initrd_size, htab_size, rtas_size;
    long pteg_shift = 17;
    int fdt_size;
    char *filename;
    int irq = 16;

    spapr = qemu_malloc(sizeof(*spapr));
    cpu_ppc_hypercall = emulate_spapr_hypercall;

    /* We place the device tree just below either the top of RAM, or
     * 2GB, so that it can be processed with 32-bit code if
     * necessary */
    fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
    /* RTAS goes just below that */
    rtas_addr = fdt_addr - RTAS_MAX_SIZE;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "POWER7";
    }
    for (i = 0; i < smp_cpus; i++) {
        CPUState *env = cpu_init(cpu_model);

        if (!env) {
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
            exit(1);
        }
        /* Set time-base frequency to 512 MHz */
        cpu_ppc_tb_init(env, TIMEBASE_FREQ);
        qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);

        env->hreset_vector = 0x60;
        env->hreset_excp_prefix = 0;
        env->gpr[3] = i;

        envs[i] = env;
    }

    /* allocate RAM */
    ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size);
    cpu_register_physical_memory(0, ram_size, ram_offset);

    /* allocate hash page table.  For now we always make this 16mb,
     * later we should probably make it scale to the size of guest
     * RAM */
    htab_size = 1ULL << (pteg_shift + 7);
    htab = qemu_mallocz(htab_size);

    for (i = 0; i < smp_cpus; i++) {
        envs[i]->external_htab = htab;
        envs[i]->htab_base = -1;
        envs[i]->htab_mask = htab_size - 1;
    }

    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
    rtas_size = load_image_targphys(filename, rtas_addr, ram_size - rtas_addr);
    if (rtas_size < 0) {
        hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
        exit(1);
    }
    qemu_free(filename);

    /* Set up Interrupt Controller */
    spapr->icp = xics_system_init(smp_cpus, envs, XICS_IRQS);

    /* Set up VIO bus */
    spapr->vio_bus = spapr_vio_bus_init();

    for (i = 0; i < MAX_SERIAL_PORTS; i++, irq++) {
        if (serial_hds[i]) {
            spapr_vty_create(spapr->vio_bus, i, serial_hds[i],
                             xics_find_qirq(spapr->icp, irq), irq);
        }
    }

    for (i = 0; i < nb_nics; i++, irq++) {
        NICInfo *nd = &nd_table[i];

        if (!nd->model) {
            nd->model = qemu_strdup("ibmveth");
        }

        if (strcmp(nd->model, "ibmveth") == 0) {
            spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd,
                              xics_find_qirq(spapr->icp, irq), irq);
        } else {
            fprintf(stderr, "pSeries (sPAPR) platform does not support "
                    "NIC model '%s' (only ibmveth is supported)\n",
                    nd->model);
            exit(1);
        }
    }

    if (kernel_filename) {
        uint64_t lowaddr = 0;

        kernel_base = KERNEL_LOAD_ADDR;

        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
                               NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, kernel_base,
                                              ram_size - kernel_base);
        }
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                        initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
    } else {
        fprintf(stderr, "pSeries machine needs -kernel for now");
        exit(1);
    }

    /* Prepare the device tree */
    fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr,
                           initrd_base, initrd_size, kernel_cmdline,
                           rtas_addr, rtas_size, pteg_shift + 7);
    assert(fdt != NULL);

    cpu_physical_memory_write(fdt_addr, fdt, fdt_size);

    qemu_free(fdt);

    envs[0]->gpr[3] = fdt_addr;
    envs[0]->gpr[5] = 0;
    envs[0]->hreset_vector = kernel_base;
}

static QEMUMachine spapr_machine = {
    .name = "pseries",
    .desc = "pSeries Logical Partition (PAPR compliant)",
    .init = ppc_spapr_init,
    .max_cpus = MAX_CPUS,
    .no_vga = 1,
    .no_parallel = 1,
};

static void spapr_machine_init(void)
{
    qemu_register_machine(&spapr_machine);
}

machine_init(spapr_machine_init);
Commit	Line	Data
9fdf0c29 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* Copyright (c) 2004-2007 Fabrice Bellard
	5	* Copyright (c) 2007 Jocelyn Mayer
	6	* Copyright (c) 2010 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27	#include "sysemu.h"
9fdf0c29 DG	28	#include "hw.h"
9fdf0c29 DG	29	#include "elf.h"
8d90ad90	30	#include "net.h"
9fdf0c29 DG	31
	32	#include "hw/boards.h"
	33	#include "hw/ppc.h"
	34	#include "hw/loader.h"
	35
	36	#include "hw/spapr.h"
4040ab72	37	#include "hw/spapr_vio.h"
b5cec4c5	38	#include "hw/xics.h"
9fdf0c29 DG	39
	40	#include <libfdt.h>
	41
	42	#define KERNEL_LOAD_ADDR 0x00000000
	43	#define INITRD_LOAD_ADDR 0x02800000
	44	#define FDT_MAX_SIZE 0x10000
39ac8455	45	#define RTAS_MAX_SIZE 0x10000
9fdf0c29 DG	46
	47	#define TIMEBASE_FREQ 512000000ULL
	48
	49	#define MAX_CPUS 32
b5cec4c5	50	#define XICS_IRQS 1024
9fdf0c29 DG	51
	52	sPAPREnvironment *spapr;
	53
	54	static void spapr_create_fdt(int fdt_size, ram_addr_t ramsize,
	55	const char cpu_model, CPUState envs[],
	56	sPAPREnvironment *spapr,
	57	target_phys_addr_t initrd_base,
	58	target_phys_addr_t initrd_size,
f43e3525	59	const char *kernel_cmdline,
39ac8455 DG	60	target_phys_addr_t rtas_addr,
39ac8455 DG	61	target_phys_addr_t rtas_size,
f43e3525	62	long hash_shift)
9fdf0c29 DG	63	{
	64	void *fdt;
	65	uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
	66	uint32_t start_prop = cpu_to_be32(initrd_base);
	67	uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
f43e3525	68	uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
ee86dfee	69	char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
b45d63b6	70	"\0hcall-tce\0hcall-vio";
b5cec4c5	71	uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
9fdf0c29 DG	72	int i;
9fdf0c29 DG	73	char *modelname;
4040ab72	74	int ret;
9fdf0c29 DG	75
	76	#define _FDT(exp) \
	77	do { \
	78	int ret = (exp); \
	79	if (ret < 0) { \
	80	fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
	81	#exp, fdt_strerror(ret)); \
	82	exit(1); \
	83	} \
	84	} while (0)
	85
	86	fdt = qemu_mallocz(FDT_MAX_SIZE);
	87	_FDT((fdt_create(fdt, FDT_MAX_SIZE)));
	88
	89	_FDT((fdt_finish_reservemap(fdt)));
	90
	91	/* Root node */
	92	_FDT((fdt_begin_node(fdt, "")));
	93	_FDT((fdt_property_string(fdt, "device_type", "chrp")));
	94	_FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR")));
	95
	96	_FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
	97	_FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
	98
	99	/* /chosen */
	100	_FDT((fdt_begin_node(fdt, "chosen")));
	101
	102	_FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
	103	_FDT((fdt_property(fdt, "linux,initrd-start",
	104	&start_prop, sizeof(start_prop))));
	105	_FDT((fdt_property(fdt, "linux,initrd-end",
	106	&end_prop, sizeof(end_prop))));
	107
	108	_FDT((fdt_end_node(fdt)));
	109
	110	/* memory node */
	111	_FDT((fdt_begin_node(fdt, "memory@0")));
	112
	113	_FDT((fdt_property_string(fdt, "device_type", "memory")));
	114	_FDT((fdt_property(fdt, "reg",
	115	mem_reg_property, sizeof(mem_reg_property))));
	116
	117	_FDT((fdt_end_node(fdt)));
	118
	119	/* cpus */
	120	_FDT((fdt_begin_node(fdt, "cpus")));
	121
	122	_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
	123	_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
	124
	125	modelname = qemu_strdup(cpu_model);
	126
	127	for (i = 0; i < strlen(modelname); i++) {
	128	modelname[i] = toupper(modelname[i]);
	129	}
	130
	131	for (i = 0; i < smp_cpus; i++) {
	132	CPUState *env = envs[i];
b5cec4c5	133	uint32_t gserver_prop[] = {cpu_to_be32(i), 0}; /* HACK! */
9fdf0c29 DG	134	char *nodename;
	135	uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
	136	0xffffffff, 0xffffffff};
	137
	138	if (asprintf(&nodename, "%s@%x", modelname, i) < 0) {
	139	fprintf(stderr, "Allocation failure\n");
	140	exit(1);
	141	}
	142
	143	_FDT((fdt_begin_node(fdt, nodename)));
	144
	145	free(nodename);
	146
	147	_FDT((fdt_property_cell(fdt, "reg", i)));
	148	_FDT((fdt_property_string(fdt, "device_type", "cpu")));
	149
	150	_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
	151	_FDT((fdt_property_cell(fdt, "dcache-block-size",
	152	env->dcache_line_size)));
	153	_FDT((fdt_property_cell(fdt, "icache-block-size",
	154	env->icache_line_size)));
	155	_FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
	156	/* Hardcode CPU frequency for now. It's kind of arbitrary on
	157	* full emu, for kvm we should copy it from the host */
	158	_FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000)));
	159	_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
f43e3525 DG	160	_FDT((fdt_property(fdt, "ibm,pft-size",
f43e3525 DG	161	pft_size_prop, sizeof(pft_size_prop))));
9fdf0c29 DG	162	_FDT((fdt_property_string(fdt, "status", "okay")));
9fdf0c29 DG	163	_FDT((fdt_property(fdt, "64-bit", NULL, 0)));
b5cec4c5 DG	164	_FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", i)));
	165	_FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
	166	gserver_prop, sizeof(gserver_prop))));
9fdf0c29 DG	167
	168	if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) {
	169	_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
	170	segs, sizeof(segs))));
	171	}
	172
	173	_FDT((fdt_end_node(fdt)));
	174	}
	175
	176	qemu_free(modelname);
	177
	178	_FDT((fdt_end_node(fdt)));
	179
f43e3525 DG	180	/* RTAS */
	181	_FDT((fdt_begin_node(fdt, "rtas")));
	182
	183	_FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
	184	sizeof(hypertas_prop))));
	185
	186	_FDT((fdt_end_node(fdt)));
	187
b5cec4c5 DG	188	/* interrupt controller */
	189	_FDT((fdt_begin_node(fdt, "interrupt-controller@0")));
	190
	191	_FDT((fdt_property_string(fdt, "device_type",
	192	"PowerPC-External-Interrupt-Presentation")));
	193	_FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
	194	_FDT((fdt_property_cell(fdt, "reg", 0)));
	195	_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
	196	_FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
	197	interrupt_server_ranges_prop,
	198	sizeof(interrupt_server_ranges_prop))));
	199
	200	_FDT((fdt_end_node(fdt)));
	201
4040ab72 DG	202	/* vdevice */
	203	_FDT((fdt_begin_node(fdt, "vdevice")));
	204
	205	_FDT((fdt_property_string(fdt, "device_type", "vdevice")));
	206	_FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
	207	_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
	208	_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5 DG	209	_FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
b5cec4c5 DG	210	_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72 DG	211
	212	_FDT((fdt_end_node(fdt)));
	213
9fdf0c29 DG	214	_FDT((fdt_end_node(fdt))); /* close root node */
	215	_FDT((fdt_finish(fdt)));
	216
4040ab72 DG	217	/* re-expand to allow for further tweaks */
	218	_FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE)));
	219
	220	ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
	221	if (ret < 0) {
	222	fprintf(stderr, "couldn't setup vio devices in fdt\n");
	223	exit(1);
	224	}
	225
39ac8455 DG	226	/* RTAS */
	227	ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
	228	if (ret < 0) {
	229	fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
	230	}
	231
4040ab72 DG	232	_FDT((fdt_pack(fdt)));
4040ab72 DG	233
9fdf0c29 DG	234	*fdt_size = fdt_totalsize(fdt);
	235
	236	return fdt;
	237	}
	238
	239	static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
	240	{
	241	return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
	242	}
	243
	244	static void emulate_spapr_hypercall(CPUState *env)
	245	{
	246	env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
	247	}
	248
9fdf0c29 DG	249	/* pSeries LPAR / sPAPR hardware init */
	250	static void ppc_spapr_init(ram_addr_t ram_size,
	251	const char *boot_device,
	252	const char *kernel_filename,
	253	const char *kernel_cmdline,
	254	const char *initrd_filename,
	255	const char *cpu_model)
	256	{
	257	CPUState *envs[MAX_CPUS];
f43e3525	258	void fdt, htab;
9fdf0c29 DG	259	int i;
9fdf0c29 DG	260	ram_addr_t ram_offset;
39ac8455	261	target_phys_addr_t fdt_addr, rtas_addr;
9fdf0c29	262	uint32_t kernel_base, initrd_base;
39ac8455	263	long kernel_size, initrd_size, htab_size, rtas_size;
f43e3525	264	long pteg_shift = 17;
9fdf0c29	265	int fdt_size;
39ac8455	266	char *filename;
0201e2da	267	int irq = 16;
9fdf0c29 DG	268
	269	spapr = qemu_malloc(sizeof(*spapr));
	270	cpu_ppc_hypercall = emulate_spapr_hypercall;
	271
	272	/* We place the device tree just below either the top of RAM, or
	273	* 2GB, so that it can be processed with 32-bit code if
	274	* necessary */
	275	fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
39ac8455 DG	276	/* RTAS goes just below that */
39ac8455 DG	277	rtas_addr = fdt_addr - RTAS_MAX_SIZE;
9fdf0c29 DG	278
	279	/* init CPUs */
	280	if (cpu_model == NULL) {
	281	cpu_model = "POWER7";
	282	}
	283	for (i = 0; i < smp_cpus; i++) {
	284	CPUState *env = cpu_init(cpu_model);
	285
	286	if (!env) {
	287	fprintf(stderr, "Unable to find PowerPC CPU definition\n");
	288	exit(1);
	289	}
	290	/* Set time-base frequency to 512 MHz */
	291	cpu_ppc_tb_init(env, TIMEBASE_FREQ);
	292	qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
	293
	294	env->hreset_vector = 0x60;
	295	env->hreset_excp_prefix = 0;
	296	env->gpr[3] = i;
	297
	298	envs[i] = env;
	299	}
	300
	301	/* allocate RAM */
	302	ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size);
	303	cpu_register_physical_memory(0, ram_size, ram_offset);
	304
f43e3525 DG	305	/* allocate hash page table. For now we always make this 16mb,
	306	* later we should probably make it scale to the size of guest
	307	* RAM */
	308	htab_size = 1ULL << (pteg_shift + 7);
	309	htab = qemu_mallocz(htab_size);
	310
	311	for (i = 0; i < smp_cpus; i++) {
	312	envs[i]->external_htab = htab;
	313	envs[i]->htab_base = -1;
	314	envs[i]->htab_mask = htab_size - 1;
	315	}
	316
39ac8455 DG	317	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
	318	rtas_size = load_image_targphys(filename, rtas_addr, ram_size - rtas_addr);
	319	if (rtas_size < 0) {
	320	hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
	321	exit(1);
	322	}
	323	qemu_free(filename);
	324
b5cec4c5 DG	325	/* Set up Interrupt Controller */
	326	spapr->icp = xics_system_init(smp_cpus, envs, XICS_IRQS);
	327
	328	/* Set up VIO bus */
4040ab72 DG	329	spapr->vio_bus = spapr_vio_bus_init();
4040ab72 DG	330
0201e2da	331	for (i = 0; i < MAX_SERIAL_PORTS; i++, irq++) {
4040ab72	332	if (serial_hds[i]) {
0201e2da DG	333	spapr_vty_create(spapr->vio_bus, i, serial_hds[i],
0201e2da DG	334	xics_find_qirq(spapr->icp, irq), irq);
4040ab72 DG	335	}
4040ab72 DG	336	}
9fdf0c29	337
8d90ad90 DG	338	for (i = 0; i < nb_nics; i++, irq++) {
	339	NICInfo *nd = &nd_table[i];
	340
	341	if (!nd->model) {
	342	nd->model = qemu_strdup("ibmveth");
	343	}
	344
	345	if (strcmp(nd->model, "ibmveth") == 0) {
	346	spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd,
	347	xics_find_qirq(spapr->icp, irq), irq);
	348	} else {
	349	fprintf(stderr, "pSeries (sPAPR) platform does not support "
	350	"NIC model '%s' (only ibmveth is supported)\n",
	351	nd->model);
	352	exit(1);
	353	}
	354	}
	355
9fdf0c29 DG	356	if (kernel_filename) {
	357	uint64_t lowaddr = 0;
	358
	359	kernel_base = KERNEL_LOAD_ADDR;
	360
	361	kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
	362	NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
	363	if (kernel_size < 0) {
	364	kernel_size = load_image_targphys(kernel_filename, kernel_base,
	365	ram_size - kernel_base);
	366	}
	367	if (kernel_size < 0) {
	368	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	369	kernel_filename);
	370	exit(1);
	371	}
	372
	373	/* load initrd */
	374	if (initrd_filename) {
	375	initrd_base = INITRD_LOAD_ADDR;
	376	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	377	ram_size - initrd_base);
	378	if (initrd_size < 0) {
	379	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	380	initrd_filename);
	381	exit(1);
	382	}
	383	} else {
	384	initrd_base = 0;
	385	initrd_size = 0;
	386	}
9fdf0c29 DG	387	} else {
	388	fprintf(stderr, "pSeries machine needs -kernel for now");
	389	exit(1);
	390	}
	391
	392	/* Prepare the device tree */
	393	fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr,
f43e3525	394	initrd_base, initrd_size, kernel_cmdline,
39ac8455	395	rtas_addr, rtas_size, pteg_shift + 7);
9fdf0c29 DG	396	assert(fdt != NULL);
	397
	398	cpu_physical_memory_write(fdt_addr, fdt, fdt_size);
	399
	400	qemu_free(fdt);
	401
	402	envs[0]->gpr[3] = fdt_addr;
	403	envs[0]->gpr[5] = 0;
	404	envs[0]->hreset_vector = kernel_base;
	405	}
	406
	407	static QEMUMachine spapr_machine = {
	408	.name = "pseries",
	409	.desc = "pSeries Logical Partition (PAPR compliant)",
	410	.init = ppc_spapr_init,
	411	.max_cpus = MAX_CPUS,
	412	.no_vga = 1,
	413	.no_parallel = 1,
	414	};
	415
	416	static void spapr_machine_init(void)
	417	{
	418	qemu_register_machine(&spapr_machine);
	419	}
	420
	421	machine_init(spapr_machine_init);