[mirror_qemu.git] / hw / spapr.c

/*
 * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
 *
 * Copyright (c) 2004-2007 Fabrice Bellard
 * Copyright (c) 2007 Jocelyn Mayer
 * Copyright (c) 2010 David Gibson, IBM Corporation.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 *
 */
#include "sysemu.h"
#include "hw.h"
#include "elf.h"
#include "net.h"
#include "blockdev.h"

#include "hw/boards.h"
#include "hw/ppc.h"
#include "hw/loader.h"

#include "hw/spapr.h"
#include "hw/spapr_vio.h"
#include "hw/xics.h"

#include <libfdt.h>

#define KERNEL_LOAD_ADDR        0x00000000
#define INITRD_LOAD_ADDR        0x02800000
#define FDT_MAX_SIZE            0x10000
#define RTAS_MAX_SIZE           0x10000

#define TIMEBASE_FREQ           512000000ULL

#define MAX_CPUS                32
#define XICS_IRQS		1024

sPAPREnvironment *spapr;

static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize,
                              const char *cpu_model, CPUState *envs[],
                              sPAPREnvironment *spapr,
                              target_phys_addr_t initrd_base,
                              target_phys_addr_t initrd_size,
                              const char *kernel_cmdline,
                              target_phys_addr_t rtas_addr,
                              target_phys_addr_t rtas_size,
                              long hash_shift)
{
    void *fdt;
    uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
    uint32_t start_prop = cpu_to_be32(initrd_base);
    uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
    uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
    char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
        "\0hcall-tce\0hcall-vio\0hcall-splpar";
    uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
    int i;
    char *modelname;
    int ret;

#define _FDT(exp) \
    do { \
        int ret = (exp);                                           \
        if (ret < 0) {                                             \
            fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
                    #exp, fdt_strerror(ret));                      \
            exit(1);                                               \
        }                                                          \
    } while (0)

    fdt = qemu_mallocz(FDT_MAX_SIZE);
    _FDT((fdt_create(fdt, FDT_MAX_SIZE)));

    _FDT((fdt_finish_reservemap(fdt)));

    /* Root node */
    _FDT((fdt_begin_node(fdt, "")));
    _FDT((fdt_property_string(fdt, "device_type", "chrp")));
    _FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));

    /* /chosen */
    _FDT((fdt_begin_node(fdt, "chosen")));

    _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
    _FDT((fdt_property(fdt, "linux,initrd-start",
                       &start_prop, sizeof(start_prop))));
    _FDT((fdt_property(fdt, "linux,initrd-end",
                       &end_prop, sizeof(end_prop))));

    _FDT((fdt_end_node(fdt)));

    /* memory node */
    _FDT((fdt_begin_node(fdt, "memory@0")));

    _FDT((fdt_property_string(fdt, "device_type", "memory")));
    _FDT((fdt_property(fdt, "reg",
                       mem_reg_property, sizeof(mem_reg_property))));

    _FDT((fdt_end_node(fdt)));

    /* cpus */
    _FDT((fdt_begin_node(fdt, "cpus")));

    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));

    modelname = qemu_strdup(cpu_model);

    for (i = 0; i < strlen(modelname); i++) {
        modelname[i] = toupper(modelname[i]);
    }

    for (i = 0; i < smp_cpus; i++) {
        CPUState *env = envs[i];
        uint32_t gserver_prop[] = {cpu_to_be32(i), 0}; /* HACK! */
        char *nodename;
        uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
                           0xffffffff, 0xffffffff};

        if (asprintf(&nodename, "%s@%x", modelname, i) < 0) {
            fprintf(stderr, "Allocation failure\n");
            exit(1);
        }

        _FDT((fdt_begin_node(fdt, nodename)));

        free(nodename);

        _FDT((fdt_property_cell(fdt, "reg", i)));
        _FDT((fdt_property_string(fdt, "device_type", "cpu")));

        _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
        _FDT((fdt_property_cell(fdt, "dcache-block-size",
                                env->dcache_line_size)));
        _FDT((fdt_property_cell(fdt, "icache-block-size",
                                env->icache_line_size)));
        _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
        /* Hardcode CPU frequency for now.  It's kind of arbitrary on
         * full emu, for kvm we should copy it from the host */
        _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000)));
        _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
        _FDT((fdt_property(fdt, "ibm,pft-size",
                           pft_size_prop, sizeof(pft_size_prop))));
        _FDT((fdt_property_string(fdt, "status", "okay")));
        _FDT((fdt_property(fdt, "64-bit", NULL, 0)));
        _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", i)));
        _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
                           gserver_prop, sizeof(gserver_prop))));

        if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) {
            _FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
                               segs, sizeof(segs))));
        }

        _FDT((fdt_end_node(fdt)));
    }

    qemu_free(modelname);

    _FDT((fdt_end_node(fdt)));

    /* RTAS */
    _FDT((fdt_begin_node(fdt, "rtas")));

    _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
                       sizeof(hypertas_prop))));

    _FDT((fdt_end_node(fdt)));

    /* interrupt controller */
    _FDT((fdt_begin_node(fdt, "interrupt-controller@0")));

    _FDT((fdt_property_string(fdt, "device_type",
                              "PowerPC-External-Interrupt-Presentation")));
    _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
    _FDT((fdt_property_cell(fdt, "reg", 0)));
    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
    _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
                       interrupt_server_ranges_prop,
                       sizeof(interrupt_server_ranges_prop))));

    _FDT((fdt_end_node(fdt)));

    /* vdevice */
    _FDT((fdt_begin_node(fdt, "vdevice")));

    _FDT((fdt_property_string(fdt, "device_type", "vdevice")));
    _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
    _FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
    _FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
    _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
    _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));

    _FDT((fdt_end_node(fdt)));

    _FDT((fdt_end_node(fdt))); /* close root node */
    _FDT((fdt_finish(fdt)));

    /* re-expand to allow for further tweaks */
    _FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE)));

    ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
    if (ret < 0) {
        fprintf(stderr, "couldn't setup vio devices in fdt\n");
        exit(1);
    }

    /* RTAS */
    ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
    if (ret < 0) {
        fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
    }

    _FDT((fdt_pack(fdt)));

    *fdt_size = fdt_totalsize(fdt);

    return fdt;
}

static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
{
    return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
}

static void emulate_spapr_hypercall(CPUState *env)
{
    env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
}

/* pSeries LPAR / sPAPR hardware init */
static void ppc_spapr_init(ram_addr_t ram_size,
                           const char *boot_device,
                           const char *kernel_filename,
                           const char *kernel_cmdline,
                           const char *initrd_filename,
                           const char *cpu_model)
{
    CPUState *envs[MAX_CPUS];
    void *fdt, *htab;
    int i;
    ram_addr_t ram_offset;
    target_phys_addr_t fdt_addr, rtas_addr;
    uint32_t kernel_base, initrd_base;
    long kernel_size, initrd_size, htab_size, rtas_size;
    long pteg_shift = 17;
    int fdt_size;
    char *filename;
    int irq = 16;

    spapr = qemu_malloc(sizeof(*spapr));
    cpu_ppc_hypercall = emulate_spapr_hypercall;

    /* We place the device tree just below either the top of RAM, or
     * 2GB, so that it can be processed with 32-bit code if
     * necessary */
    fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
    /* RTAS goes just below that */
    rtas_addr = fdt_addr - RTAS_MAX_SIZE;

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "POWER7";
    }
    for (i = 0; i < smp_cpus; i++) {
        CPUState *env = cpu_init(cpu_model);

        if (!env) {
            fprintf(stderr, "Unable to find PowerPC CPU definition\n");
            exit(1);
        }
        /* Set time-base frequency to 512 MHz */
        cpu_ppc_tb_init(env, TIMEBASE_FREQ);
        qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);

        env->hreset_vector = 0x60;
        env->hreset_excp_prefix = 0;
        env->gpr[3] = i;

        envs[i] = env;
    }

    /* allocate RAM */
    ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size);
    cpu_register_physical_memory(0, ram_size, ram_offset);

    /* allocate hash page table.  For now we always make this 16mb,
     * later we should probably make it scale to the size of guest
     * RAM */
    htab_size = 1ULL << (pteg_shift + 7);
    htab = qemu_mallocz(htab_size);

    for (i = 0; i < smp_cpus; i++) {
        envs[i]->external_htab = htab;
        envs[i]->htab_base = -1;
        envs[i]->htab_mask = htab_size - 1;
    }

    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
    rtas_size = load_image_targphys(filename, rtas_addr, ram_size - rtas_addr);
    if (rtas_size < 0) {
        hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
        exit(1);
    }
    qemu_free(filename);

    /* Set up Interrupt Controller */
    spapr->icp = xics_system_init(smp_cpus, envs, XICS_IRQS);

    /* Set up VIO bus */
    spapr->vio_bus = spapr_vio_bus_init();

    for (i = 0; i < MAX_SERIAL_PORTS; i++, irq++) {
        if (serial_hds[i]) {
            spapr_vty_create(spapr->vio_bus, i, serial_hds[i],
                             xics_find_qirq(spapr->icp, irq), irq);
        }
    }

    for (i = 0; i < nb_nics; i++, irq++) {
        NICInfo *nd = &nd_table[i];

        if (!nd->model) {
            nd->model = qemu_strdup("ibmveth");
        }

        if (strcmp(nd->model, "ibmveth") == 0) {
            spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd,
                              xics_find_qirq(spapr->icp, irq), irq);
        } else {
            fprintf(stderr, "pSeries (sPAPR) platform does not support "
                    "NIC model '%s' (only ibmveth is supported)\n",
                    nd->model);
            exit(1);
        }
    }

    for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
        spapr_vscsi_create(spapr->vio_bus, 0x2000 + i,
                           xics_find_qirq(spapr->icp, irq), irq);
        irq++;
    }

    if (kernel_filename) {
        uint64_t lowaddr = 0;

        kernel_base = KERNEL_LOAD_ADDR;

        kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
                               NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, kernel_base,
                                              ram_size - kernel_base);
        }
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }

        /* load initrd */
        if (initrd_filename) {
            initrd_base = INITRD_LOAD_ADDR;
            initrd_size = load_image_targphys(initrd_filename, initrd_base,
                                              ram_size - initrd_base);
            if (initrd_size < 0) {
                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
                        initrd_filename);
                exit(1);
            }
        } else {
            initrd_base = 0;
            initrd_size = 0;
        }
    } else {
        fprintf(stderr, "pSeries machine needs -kernel for now");
        exit(1);
    }

    /* Prepare the device tree */
    fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr,
                           initrd_base, initrd_size, kernel_cmdline,
                           rtas_addr, rtas_size, pteg_shift + 7);
    assert(fdt != NULL);

    cpu_physical_memory_write(fdt_addr, fdt, fdt_size);

    qemu_free(fdt);

    envs[0]->gpr[3] = fdt_addr;
    envs[0]->gpr[5] = 0;
    envs[0]->hreset_vector = kernel_base;
}

static QEMUMachine spapr_machine = {
    .name = "pseries",
    .desc = "pSeries Logical Partition (PAPR compliant)",
    .init = ppc_spapr_init,
    .max_cpus = MAX_CPUS,
    .no_vga = 1,
    .no_parallel = 1,
    .use_scsi = 1,
};

static void spapr_machine_init(void)
{
    qemu_register_machine(&spapr_machine);
}

machine_init(spapr_machine_init);
Commit	Line	Data
9fdf0c29 DG	1	/*
	2	* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
	3	*
	4	* Copyright (c) 2004-2007 Fabrice Bellard
	5	* Copyright (c) 2007 Jocelyn Mayer
	6	* Copyright (c) 2010 David Gibson, IBM Corporation.
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*
	26	*/
	27	#include "sysemu.h"
9fdf0c29 DG	28	#include "hw.h"
9fdf0c29 DG	29	#include "elf.h"
8d90ad90	30	#include "net.h"
6e270446	31	#include "blockdev.h"
9fdf0c29 DG	32
	33	#include "hw/boards.h"
	34	#include "hw/ppc.h"
	35	#include "hw/loader.h"
	36
	37	#include "hw/spapr.h"
4040ab72	38	#include "hw/spapr_vio.h"
b5cec4c5	39	#include "hw/xics.h"
9fdf0c29 DG	40
	41	#include <libfdt.h>
	42
	43	#define KERNEL_LOAD_ADDR 0x00000000
	44	#define INITRD_LOAD_ADDR 0x02800000
	45	#define FDT_MAX_SIZE 0x10000
39ac8455	46	#define RTAS_MAX_SIZE 0x10000
9fdf0c29 DG	47
	48	#define TIMEBASE_FREQ 512000000ULL
	49
	50	#define MAX_CPUS 32
b5cec4c5	51	#define XICS_IRQS 1024
9fdf0c29 DG	52
	53	sPAPREnvironment *spapr;
	54
	55	static void spapr_create_fdt(int fdt_size, ram_addr_t ramsize,
	56	const char cpu_model, CPUState envs[],
	57	sPAPREnvironment *spapr,
	58	target_phys_addr_t initrd_base,
	59	target_phys_addr_t initrd_size,
f43e3525	60	const char *kernel_cmdline,
39ac8455 DG	61	target_phys_addr_t rtas_addr,
39ac8455 DG	62	target_phys_addr_t rtas_size,
f43e3525	63	long hash_shift)
9fdf0c29 DG	64	{
	65	void *fdt;
	66	uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
	67	uint32_t start_prop = cpu_to_be32(initrd_base);
	68	uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
f43e3525	69	uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)};
ee86dfee	70	char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt"
ed120055	71	"\0hcall-tce\0hcall-vio\0hcall-splpar";
b5cec4c5	72	uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)};
9fdf0c29 DG	73	int i;
9fdf0c29 DG	74	char *modelname;
4040ab72	75	int ret;
9fdf0c29 DG	76
	77	#define _FDT(exp) \
	78	do { \
	79	int ret = (exp); \
	80	if (ret < 0) { \
	81	fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
	82	#exp, fdt_strerror(ret)); \
	83	exit(1); \
	84	} \
	85	} while (0)
	86
	87	fdt = qemu_mallocz(FDT_MAX_SIZE);
	88	_FDT((fdt_create(fdt, FDT_MAX_SIZE)));
	89
	90	_FDT((fdt_finish_reservemap(fdt)));
	91
	92	/* Root node */
	93	_FDT((fdt_begin_node(fdt, "")));
	94	_FDT((fdt_property_string(fdt, "device_type", "chrp")));
	95	_FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR")));
	96
	97	_FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
	98	_FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
	99
	100	/* /chosen */
	101	_FDT((fdt_begin_node(fdt, "chosen")));
	102
	103	_FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
	104	_FDT((fdt_property(fdt, "linux,initrd-start",
	105	&start_prop, sizeof(start_prop))));
	106	_FDT((fdt_property(fdt, "linux,initrd-end",
	107	&end_prop, sizeof(end_prop))));
	108
	109	_FDT((fdt_end_node(fdt)));
	110
	111	/* memory node */
	112	_FDT((fdt_begin_node(fdt, "memory@0")));
	113
	114	_FDT((fdt_property_string(fdt, "device_type", "memory")));
	115	_FDT((fdt_property(fdt, "reg",
	116	mem_reg_property, sizeof(mem_reg_property))));
	117
	118	_FDT((fdt_end_node(fdt)));
	119
	120	/* cpus */
	121	_FDT((fdt_begin_node(fdt, "cpus")));
	122
	123	_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
	124	_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
	125
	126	modelname = qemu_strdup(cpu_model);
	127
	128	for (i = 0; i < strlen(modelname); i++) {
	129	modelname[i] = toupper(modelname[i]);
	130	}
	131
	132	for (i = 0; i < smp_cpus; i++) {
	133	CPUState *env = envs[i];
b5cec4c5	134	uint32_t gserver_prop[] = {cpu_to_be32(i), 0}; /* HACK! */
9fdf0c29 DG	135	char *nodename;
	136	uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
	137	0xffffffff, 0xffffffff};
	138
	139	if (asprintf(&nodename, "%s@%x", modelname, i) < 0) {
	140	fprintf(stderr, "Allocation failure\n");
	141	exit(1);
	142	}
	143
	144	_FDT((fdt_begin_node(fdt, nodename)));
	145
	146	free(nodename);
	147
	148	_FDT((fdt_property_cell(fdt, "reg", i)));
	149	_FDT((fdt_property_string(fdt, "device_type", "cpu")));
	150
	151	_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
	152	_FDT((fdt_property_cell(fdt, "dcache-block-size",
	153	env->dcache_line_size)));
	154	_FDT((fdt_property_cell(fdt, "icache-block-size",
	155	env->icache_line_size)));
	156	_FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
	157	/* Hardcode CPU frequency for now. It's kind of arbitrary on
	158	* full emu, for kvm we should copy it from the host */
	159	_FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000)));
	160	_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
f43e3525 DG	161	_FDT((fdt_property(fdt, "ibm,pft-size",
f43e3525 DG	162	pft_size_prop, sizeof(pft_size_prop))));
9fdf0c29 DG	163	_FDT((fdt_property_string(fdt, "status", "okay")));
9fdf0c29 DG	164	_FDT((fdt_property(fdt, "64-bit", NULL, 0)));
b5cec4c5 DG	165	_FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", i)));
	166	_FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s",
	167	gserver_prop, sizeof(gserver_prop))));
9fdf0c29 DG	168
	169	if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) {
	170	_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
	171	segs, sizeof(segs))));
	172	}
	173
	174	_FDT((fdt_end_node(fdt)));
	175	}
	176
	177	qemu_free(modelname);
	178
	179	_FDT((fdt_end_node(fdt)));
	180
f43e3525 DG	181	/* RTAS */
	182	_FDT((fdt_begin_node(fdt, "rtas")));
	183
	184	_FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop,
	185	sizeof(hypertas_prop))));
	186
	187	_FDT((fdt_end_node(fdt)));
	188
b5cec4c5 DG	189	/* interrupt controller */
	190	_FDT((fdt_begin_node(fdt, "interrupt-controller@0")));
	191
	192	_FDT((fdt_property_string(fdt, "device_type",
	193	"PowerPC-External-Interrupt-Presentation")));
	194	_FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp")));
	195	_FDT((fdt_property_cell(fdt, "reg", 0)));
	196	_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
	197	_FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
	198	interrupt_server_ranges_prop,
	199	sizeof(interrupt_server_ranges_prop))));
	200
	201	_FDT((fdt_end_node(fdt)));
	202
4040ab72 DG	203	/* vdevice */
	204	_FDT((fdt_begin_node(fdt, "vdevice")));
	205
	206	_FDT((fdt_property_string(fdt, "device_type", "vdevice")));
	207	_FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice")));
	208	_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
	209	_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
b5cec4c5 DG	210	_FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2)));
b5cec4c5 DG	211	_FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
4040ab72 DG	212
	213	_FDT((fdt_end_node(fdt)));
	214
9fdf0c29 DG	215	_FDT((fdt_end_node(fdt))); /* close root node */
	216	_FDT((fdt_finish(fdt)));
	217
4040ab72 DG	218	/* re-expand to allow for further tweaks */
	219	_FDT((fdt_open_into(fdt, fdt, FDT_MAX_SIZE)));
	220
	221	ret = spapr_populate_vdevice(spapr->vio_bus, fdt);
	222	if (ret < 0) {
	223	fprintf(stderr, "couldn't setup vio devices in fdt\n");
	224	exit(1);
	225	}
	226
39ac8455 DG	227	/* RTAS */
	228	ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size);
	229	if (ret < 0) {
	230	fprintf(stderr, "Couldn't set up RTAS device tree properties\n");
	231	}
	232
4040ab72 DG	233	_FDT((fdt_pack(fdt)));
4040ab72 DG	234
9fdf0c29 DG	235	*fdt_size = fdt_totalsize(fdt);
	236
	237	return fdt;
	238	}
	239
	240	static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
	241	{
	242	return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
	243	}
	244
	245	static void emulate_spapr_hypercall(CPUState *env)
	246	{
	247	env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
	248	}
	249
9fdf0c29 DG	250	/* pSeries LPAR / sPAPR hardware init */
	251	static void ppc_spapr_init(ram_addr_t ram_size,
	252	const char *boot_device,
	253	const char *kernel_filename,
	254	const char *kernel_cmdline,
	255	const char *initrd_filename,
	256	const char *cpu_model)
	257	{
	258	CPUState *envs[MAX_CPUS];
f43e3525	259	void fdt, htab;
9fdf0c29 DG	260	int i;
9fdf0c29 DG	261	ram_addr_t ram_offset;
39ac8455	262	target_phys_addr_t fdt_addr, rtas_addr;
9fdf0c29	263	uint32_t kernel_base, initrd_base;
39ac8455	264	long kernel_size, initrd_size, htab_size, rtas_size;
f43e3525	265	long pteg_shift = 17;
9fdf0c29	266	int fdt_size;
39ac8455	267	char *filename;
0201e2da	268	int irq = 16;
9fdf0c29 DG	269
	270	spapr = qemu_malloc(sizeof(*spapr));
	271	cpu_ppc_hypercall = emulate_spapr_hypercall;
	272
	273	/* We place the device tree just below either the top of RAM, or
	274	* 2GB, so that it can be processed with 32-bit code if
	275	* necessary */
	276	fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
39ac8455 DG	277	/* RTAS goes just below that */
39ac8455 DG	278	rtas_addr = fdt_addr - RTAS_MAX_SIZE;
9fdf0c29 DG	279
	280	/* init CPUs */
	281	if (cpu_model == NULL) {
	282	cpu_model = "POWER7";
	283	}
	284	for (i = 0; i < smp_cpus; i++) {
	285	CPUState *env = cpu_init(cpu_model);
	286
	287	if (!env) {
	288	fprintf(stderr, "Unable to find PowerPC CPU definition\n");
	289	exit(1);
	290	}
	291	/* Set time-base frequency to 512 MHz */
	292	cpu_ppc_tb_init(env, TIMEBASE_FREQ);
	293	qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
	294
	295	env->hreset_vector = 0x60;
	296	env->hreset_excp_prefix = 0;
	297	env->gpr[3] = i;
	298
	299	envs[i] = env;
	300	}
	301
	302	/* allocate RAM */
	303	ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size);
	304	cpu_register_physical_memory(0, ram_size, ram_offset);
	305
f43e3525 DG	306	/* allocate hash page table. For now we always make this 16mb,
	307	* later we should probably make it scale to the size of guest
	308	* RAM */
	309	htab_size = 1ULL << (pteg_shift + 7);
	310	htab = qemu_mallocz(htab_size);
	311
	312	for (i = 0; i < smp_cpus; i++) {
	313	envs[i]->external_htab = htab;
	314	envs[i]->htab_base = -1;
	315	envs[i]->htab_mask = htab_size - 1;
	316	}
	317
39ac8455 DG	318	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin");
	319	rtas_size = load_image_targphys(filename, rtas_addr, ram_size - rtas_addr);
	320	if (rtas_size < 0) {
	321	hw_error("qemu: could not load LPAR rtas '%s'\n", filename);
	322	exit(1);
	323	}
	324	qemu_free(filename);
	325
b5cec4c5 DG	326	/* Set up Interrupt Controller */
	327	spapr->icp = xics_system_init(smp_cpus, envs, XICS_IRQS);
	328
	329	/* Set up VIO bus */
4040ab72 DG	330	spapr->vio_bus = spapr_vio_bus_init();
4040ab72 DG	331
0201e2da	332	for (i = 0; i < MAX_SERIAL_PORTS; i++, irq++) {
4040ab72	333	if (serial_hds[i]) {
0201e2da DG	334	spapr_vty_create(spapr->vio_bus, i, serial_hds[i],
0201e2da DG	335	xics_find_qirq(spapr->icp, irq), irq);
4040ab72 DG	336	}
4040ab72 DG	337	}
9fdf0c29	338
8d90ad90 DG	339	for (i = 0; i < nb_nics; i++, irq++) {
	340	NICInfo *nd = &nd_table[i];
	341
	342	if (!nd->model) {
	343	nd->model = qemu_strdup("ibmveth");
	344	}
	345
	346	if (strcmp(nd->model, "ibmveth") == 0) {
	347	spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd,
	348	xics_find_qirq(spapr->icp, irq), irq);
	349	} else {
	350	fprintf(stderr, "pSeries (sPAPR) platform does not support "
	351	"NIC model '%s' (only ibmveth is supported)\n",
	352	nd->model);
	353	exit(1);
	354	}
	355	}
	356
6e270446 BH	357	for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) {
	358	spapr_vscsi_create(spapr->vio_bus, 0x2000 + i,
	359	xics_find_qirq(spapr->icp, irq), irq);
	360	irq++;
	361	}
	362
9fdf0c29 DG	363	if (kernel_filename) {
	364	uint64_t lowaddr = 0;
	365
	366	kernel_base = KERNEL_LOAD_ADDR;
	367
	368	kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
	369	NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
	370	if (kernel_size < 0) {
	371	kernel_size = load_image_targphys(kernel_filename, kernel_base,
	372	ram_size - kernel_base);
	373	}
	374	if (kernel_size < 0) {
	375	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	376	kernel_filename);
	377	exit(1);
	378	}
	379
	380	/* load initrd */
	381	if (initrd_filename) {
	382	initrd_base = INITRD_LOAD_ADDR;
	383	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	384	ram_size - initrd_base);
	385	if (initrd_size < 0) {
	386	fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
	387	initrd_filename);
	388	exit(1);
	389	}
	390	} else {
	391	initrd_base = 0;
	392	initrd_size = 0;
	393	}
9fdf0c29 DG	394	} else {
	395	fprintf(stderr, "pSeries machine needs -kernel for now");
	396	exit(1);
	397	}
	398
	399	/* Prepare the device tree */
	400	fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr,
f43e3525	401	initrd_base, initrd_size, kernel_cmdline,
39ac8455	402	rtas_addr, rtas_size, pteg_shift + 7);
9fdf0c29 DG	403	assert(fdt != NULL);
	404
	405	cpu_physical_memory_write(fdt_addr, fdt, fdt_size);
	406
	407	qemu_free(fdt);
	408
	409	envs[0]->gpr[3] = fdt_addr;
	410	envs[0]->gpr[5] = 0;
	411	envs[0]->hreset_vector = kernel_base;
	412	}
	413
	414	static QEMUMachine spapr_machine = {
	415	.name = "pseries",
	416	.desc = "pSeries Logical Partition (PAPR compliant)",
	417	.init = ppc_spapr_init,
	418	.max_cpus = MAX_CPUS,
	419	.no_vga = 1,
	420	.no_parallel = 1,
6e270446	421	.use_scsi = 1,
9fdf0c29 DG	422	};
	423
	424	static void spapr_machine_init(void)
	425	{
	426	qemu_register_machine(&spapr_machine);
	427	}
	428
	429	machine_init(spapr_machine_init);