]>
Commit | Line | Data |
---|---|---|
9fdf0c29 DG |
1 | /* |
2 | * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator | |
3 | * | |
4 | * Copyright (c) 2004-2007 Fabrice Bellard | |
5 | * Copyright (c) 2007 Jocelyn Mayer | |
6 | * Copyright (c) 2010 David Gibson, IBM Corporation. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
9 | * of this software and associated documentation files (the "Software"), to deal | |
10 | * in the Software without restriction, including without limitation the rights | |
11 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
12 | * copies of the Software, and to permit persons to whom the Software is | |
13 | * furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
23 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
24 | * THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | #include "sysemu.h" | |
9fdf0c29 DG |
28 | #include "hw.h" |
29 | #include "elf.h" | |
8d90ad90 | 30 | #include "net.h" |
6e270446 | 31 | #include "blockdev.h" |
9fdf0c29 DG |
32 | |
33 | #include "hw/boards.h" | |
34 | #include "hw/ppc.h" | |
35 | #include "hw/loader.h" | |
36 | ||
37 | #include "hw/spapr.h" | |
4040ab72 | 38 | #include "hw/spapr_vio.h" |
b5cec4c5 | 39 | #include "hw/xics.h" |
9fdf0c29 | 40 | |
f61b4bed AG |
41 | #include "kvm.h" |
42 | #include "kvm_ppc.h" | |
43 | ||
9fdf0c29 DG |
44 | #include <libfdt.h> |
45 | ||
46 | #define KERNEL_LOAD_ADDR 0x00000000 | |
47 | #define INITRD_LOAD_ADDR 0x02800000 | |
48 | #define FDT_MAX_SIZE 0x10000 | |
39ac8455 | 49 | #define RTAS_MAX_SIZE 0x10000 |
a9f8ad8f DG |
50 | #define FW_MAX_SIZE 0x400000 |
51 | #define FW_FILE_NAME "slof.bin" | |
52 | ||
53 | #define MIN_RAM_SLOF 512UL | |
9fdf0c29 DG |
54 | |
55 | #define TIMEBASE_FREQ 512000000ULL | |
56 | ||
41019fec | 57 | #define MAX_CPUS 256 |
b5cec4c5 | 58 | #define XICS_IRQS 1024 |
9fdf0c29 DG |
59 | |
60 | sPAPREnvironment *spapr; | |
61 | ||
a3467baa DG |
62 | static void *spapr_create_fdt_skel(const char *cpu_model, |
63 | target_phys_addr_t initrd_base, | |
64 | target_phys_addr_t initrd_size, | |
65 | const char *boot_device, | |
66 | const char *kernel_cmdline, | |
67 | long hash_shift) | |
9fdf0c29 DG |
68 | { |
69 | void *fdt; | |
c7a5c0c9 | 70 | CPUState *env; |
a3467baa | 71 | uint64_t mem_reg_property[] = { 0, cpu_to_be64(ram_size) }; |
9fdf0c29 DG |
72 | uint32_t start_prop = cpu_to_be32(initrd_base); |
73 | uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size); | |
f43e3525 | 74 | uint32_t pft_size_prop[] = {0, cpu_to_be32(hash_shift)}; |
ee86dfee | 75 | char hypertas_prop[] = "hcall-pft\0hcall-term\0hcall-dabr\0hcall-interrupt" |
ed120055 | 76 | "\0hcall-tce\0hcall-vio\0hcall-splpar"; |
b5cec4c5 | 77 | uint32_t interrupt_server_ranges_prop[] = {0, cpu_to_be32(smp_cpus)}; |
9fdf0c29 DG |
78 | int i; |
79 | char *modelname; | |
80 | ||
81 | #define _FDT(exp) \ | |
82 | do { \ | |
83 | int ret = (exp); \ | |
84 | if (ret < 0) { \ | |
85 | fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \ | |
86 | #exp, fdt_strerror(ret)); \ | |
87 | exit(1); \ | |
88 | } \ | |
89 | } while (0) | |
90 | ||
7267c094 | 91 | fdt = g_malloc0(FDT_MAX_SIZE); |
9fdf0c29 DG |
92 | _FDT((fdt_create(fdt, FDT_MAX_SIZE))); |
93 | ||
94 | _FDT((fdt_finish_reservemap(fdt))); | |
95 | ||
96 | /* Root node */ | |
97 | _FDT((fdt_begin_node(fdt, ""))); | |
98 | _FDT((fdt_property_string(fdt, "device_type", "chrp"))); | |
5d73dd66 | 99 | _FDT((fdt_property_string(fdt, "model", "IBM pSeries (emulated by qemu)"))); |
9fdf0c29 DG |
100 | |
101 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x2))); | |
102 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x2))); | |
103 | ||
104 | /* /chosen */ | |
105 | _FDT((fdt_begin_node(fdt, "chosen"))); | |
106 | ||
107 | _FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline))); | |
108 | _FDT((fdt_property(fdt, "linux,initrd-start", | |
109 | &start_prop, sizeof(start_prop)))); | |
110 | _FDT((fdt_property(fdt, "linux,initrd-end", | |
111 | &end_prop, sizeof(end_prop)))); | |
a9f8ad8f | 112 | _FDT((fdt_property_string(fdt, "qemu,boot-device", boot_device))); |
9fdf0c29 DG |
113 | |
114 | _FDT((fdt_end_node(fdt))); | |
115 | ||
116 | /* memory node */ | |
117 | _FDT((fdt_begin_node(fdt, "memory@0"))); | |
118 | ||
119 | _FDT((fdt_property_string(fdt, "device_type", "memory"))); | |
120 | _FDT((fdt_property(fdt, "reg", | |
121 | mem_reg_property, sizeof(mem_reg_property)))); | |
122 | ||
123 | _FDT((fdt_end_node(fdt))); | |
124 | ||
125 | /* cpus */ | |
126 | _FDT((fdt_begin_node(fdt, "cpus"))); | |
127 | ||
128 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
129 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
130 | ||
7267c094 | 131 | modelname = g_strdup(cpu_model); |
9fdf0c29 DG |
132 | |
133 | for (i = 0; i < strlen(modelname); i++) { | |
134 | modelname[i] = toupper(modelname[i]); | |
135 | } | |
136 | ||
c7a5c0c9 DG |
137 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
138 | int index = env->cpu_index; | |
139 | uint32_t gserver_prop[] = {cpu_to_be32(index), 0}; /* HACK! */ | |
9fdf0c29 DG |
140 | char *nodename; |
141 | uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), | |
142 | 0xffffffff, 0xffffffff}; | |
143 | ||
c7a5c0c9 | 144 | if (asprintf(&nodename, "%s@%x", modelname, index) < 0) { |
9fdf0c29 DG |
145 | fprintf(stderr, "Allocation failure\n"); |
146 | exit(1); | |
147 | } | |
148 | ||
149 | _FDT((fdt_begin_node(fdt, nodename))); | |
150 | ||
151 | free(nodename); | |
152 | ||
c7a5c0c9 | 153 | _FDT((fdt_property_cell(fdt, "reg", index))); |
9fdf0c29 DG |
154 | _FDT((fdt_property_string(fdt, "device_type", "cpu"))); |
155 | ||
156 | _FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR]))); | |
157 | _FDT((fdt_property_cell(fdt, "dcache-block-size", | |
158 | env->dcache_line_size))); | |
159 | _FDT((fdt_property_cell(fdt, "icache-block-size", | |
160 | env->icache_line_size))); | |
161 | _FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ))); | |
162 | /* Hardcode CPU frequency for now. It's kind of arbitrary on | |
163 | * full emu, for kvm we should copy it from the host */ | |
164 | _FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000))); | |
165 | _FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr))); | |
f43e3525 DG |
166 | _FDT((fdt_property(fdt, "ibm,pft-size", |
167 | pft_size_prop, sizeof(pft_size_prop)))); | |
9fdf0c29 DG |
168 | _FDT((fdt_property_string(fdt, "status", "okay"))); |
169 | _FDT((fdt_property(fdt, "64-bit", NULL, 0))); | |
c7a5c0c9 | 170 | _FDT((fdt_property_cell(fdt, "ibm,ppc-interrupt-server#s", index))); |
b5cec4c5 DG |
171 | _FDT((fdt_property(fdt, "ibm,ppc-interrupt-gserver#s", |
172 | gserver_prop, sizeof(gserver_prop)))); | |
9fdf0c29 | 173 | |
c7a5c0c9 | 174 | if (env->mmu_model & POWERPC_MMU_1TSEG) { |
9fdf0c29 DG |
175 | _FDT((fdt_property(fdt, "ibm,processor-segment-sizes", |
176 | segs, sizeof(segs)))); | |
177 | } | |
178 | ||
179 | _FDT((fdt_end_node(fdt))); | |
180 | } | |
181 | ||
7267c094 | 182 | g_free(modelname); |
9fdf0c29 DG |
183 | |
184 | _FDT((fdt_end_node(fdt))); | |
185 | ||
f43e3525 DG |
186 | /* RTAS */ |
187 | _FDT((fdt_begin_node(fdt, "rtas"))); | |
188 | ||
189 | _FDT((fdt_property(fdt, "ibm,hypertas-functions", hypertas_prop, | |
190 | sizeof(hypertas_prop)))); | |
191 | ||
192 | _FDT((fdt_end_node(fdt))); | |
193 | ||
b5cec4c5 DG |
194 | /* interrupt controller */ |
195 | _FDT((fdt_begin_node(fdt, "interrupt-controller@0"))); | |
196 | ||
197 | _FDT((fdt_property_string(fdt, "device_type", | |
198 | "PowerPC-External-Interrupt-Presentation"))); | |
199 | _FDT((fdt_property_string(fdt, "compatible", "IBM,ppc-xicp"))); | |
200 | _FDT((fdt_property_cell(fdt, "reg", 0))); | |
201 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
202 | _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", | |
203 | interrupt_server_ranges_prop, | |
204 | sizeof(interrupt_server_ranges_prop)))); | |
205 | ||
206 | _FDT((fdt_end_node(fdt))); | |
207 | ||
4040ab72 DG |
208 | /* vdevice */ |
209 | _FDT((fdt_begin_node(fdt, "vdevice"))); | |
210 | ||
211 | _FDT((fdt_property_string(fdt, "device_type", "vdevice"))); | |
212 | _FDT((fdt_property_string(fdt, "compatible", "IBM,vdevice"))); | |
213 | _FDT((fdt_property_cell(fdt, "#address-cells", 0x1))); | |
214 | _FDT((fdt_property_cell(fdt, "#size-cells", 0x0))); | |
b5cec4c5 DG |
215 | _FDT((fdt_property_cell(fdt, "#interrupt-cells", 0x2))); |
216 | _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); | |
4040ab72 DG |
217 | |
218 | _FDT((fdt_end_node(fdt))); | |
219 | ||
9fdf0c29 DG |
220 | _FDT((fdt_end_node(fdt))); /* close root node */ |
221 | _FDT((fdt_finish(fdt))); | |
222 | ||
a3467baa DG |
223 | return fdt; |
224 | } | |
225 | ||
226 | static void spapr_finalize_fdt(sPAPREnvironment *spapr, | |
227 | target_phys_addr_t fdt_addr, | |
228 | target_phys_addr_t rtas_addr, | |
229 | target_phys_addr_t rtas_size) | |
230 | { | |
231 | int ret; | |
232 | void *fdt; | |
233 | ||
7267c094 | 234 | fdt = g_malloc(FDT_MAX_SIZE); |
a3467baa DG |
235 | |
236 | /* open out the base tree into a temp buffer for the final tweaks */ | |
237 | _FDT((fdt_open_into(spapr->fdt_skel, fdt, FDT_MAX_SIZE))); | |
4040ab72 DG |
238 | |
239 | ret = spapr_populate_vdevice(spapr->vio_bus, fdt); | |
240 | if (ret < 0) { | |
241 | fprintf(stderr, "couldn't setup vio devices in fdt\n"); | |
242 | exit(1); | |
243 | } | |
244 | ||
39ac8455 DG |
245 | /* RTAS */ |
246 | ret = spapr_rtas_device_tree_setup(fdt, rtas_addr, rtas_size); | |
247 | if (ret < 0) { | |
248 | fprintf(stderr, "Couldn't set up RTAS device tree properties\n"); | |
249 | } | |
250 | ||
4040ab72 DG |
251 | _FDT((fdt_pack(fdt))); |
252 | ||
a3467baa | 253 | cpu_physical_memory_write(fdt_addr, fdt, fdt_totalsize(fdt)); |
9fdf0c29 | 254 | |
7267c094 | 255 | g_free(fdt); |
9fdf0c29 DG |
256 | } |
257 | ||
258 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) | |
259 | { | |
260 | return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; | |
261 | } | |
262 | ||
263 | static void emulate_spapr_hypercall(CPUState *env) | |
264 | { | |
265 | env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); | |
266 | } | |
267 | ||
a3467baa DG |
268 | static void spapr_reset(void *opaque) |
269 | { | |
270 | sPAPREnvironment *spapr = (sPAPREnvironment *)opaque; | |
271 | ||
272 | fprintf(stderr, "sPAPR reset\n"); | |
273 | ||
274 | /* flush out the hash table */ | |
275 | memset(spapr->htab, 0, spapr->htab_size); | |
276 | ||
277 | /* Load the fdt */ | |
278 | spapr_finalize_fdt(spapr, spapr->fdt_addr, spapr->rtas_addr, | |
279 | spapr->rtas_size); | |
280 | ||
281 | /* Set up the entry state */ | |
282 | first_cpu->gpr[3] = spapr->fdt_addr; | |
283 | first_cpu->gpr[5] = 0; | |
284 | first_cpu->halted = 0; | |
285 | first_cpu->nip = spapr->entry_point; | |
286 | ||
287 | } | |
288 | ||
9fdf0c29 DG |
289 | /* pSeries LPAR / sPAPR hardware init */ |
290 | static void ppc_spapr_init(ram_addr_t ram_size, | |
291 | const char *boot_device, | |
292 | const char *kernel_filename, | |
293 | const char *kernel_cmdline, | |
294 | const char *initrd_filename, | |
295 | const char *cpu_model) | |
296 | { | |
c7a5c0c9 | 297 | CPUState *env; |
9fdf0c29 DG |
298 | int i; |
299 | ram_addr_t ram_offset; | |
a3467baa DG |
300 | uint32_t initrd_base; |
301 | long kernel_size, initrd_size, fw_size; | |
f43e3525 | 302 | long pteg_shift = 17; |
39ac8455 | 303 | char *filename; |
9fdf0c29 | 304 | |
7267c094 | 305 | spapr = g_malloc(sizeof(*spapr)); |
9fdf0c29 DG |
306 | cpu_ppc_hypercall = emulate_spapr_hypercall; |
307 | ||
308 | /* We place the device tree just below either the top of RAM, or | |
309 | * 2GB, so that it can be processed with 32-bit code if | |
310 | * necessary */ | |
a3467baa DG |
311 | spapr->fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE; |
312 | spapr->rtas_addr = spapr->fdt_addr - RTAS_MAX_SIZE; | |
9fdf0c29 DG |
313 | |
314 | /* init CPUs */ | |
315 | if (cpu_model == NULL) { | |
316 | cpu_model = "POWER7"; | |
317 | } | |
318 | for (i = 0; i < smp_cpus; i++) { | |
c7a5c0c9 | 319 | env = cpu_init(cpu_model); |
9fdf0c29 DG |
320 | |
321 | if (!env) { | |
322 | fprintf(stderr, "Unable to find PowerPC CPU definition\n"); | |
323 | exit(1); | |
324 | } | |
325 | /* Set time-base frequency to 512 MHz */ | |
326 | cpu_ppc_tb_init(env, TIMEBASE_FREQ); | |
327 | qemu_register_reset((QEMUResetHandler *)&cpu_reset, env); | |
328 | ||
329 | env->hreset_vector = 0x60; | |
330 | env->hreset_excp_prefix = 0; | |
c7a5c0c9 | 331 | env->gpr[3] = env->cpu_index; |
9fdf0c29 DG |
332 | } |
333 | ||
334 | /* allocate RAM */ | |
335 | ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size); | |
336 | cpu_register_physical_memory(0, ram_size, ram_offset); | |
337 | ||
f43e3525 DG |
338 | /* allocate hash page table. For now we always make this 16mb, |
339 | * later we should probably make it scale to the size of guest | |
340 | * RAM */ | |
a3467baa | 341 | spapr->htab_size = 1ULL << (pteg_shift + 7); |
f61b4bed | 342 | spapr->htab = qemu_memalign(spapr->htab_size, spapr->htab_size); |
f43e3525 | 343 | |
c7a5c0c9 | 344 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
a3467baa | 345 | env->external_htab = spapr->htab; |
c7a5c0c9 | 346 | env->htab_base = -1; |
a3467baa | 347 | env->htab_mask = spapr->htab_size - 1; |
f61b4bed AG |
348 | |
349 | /* Tell KVM that we're in PAPR mode */ | |
350 | env->spr[SPR_SDR1] = (unsigned long)spapr->htab | | |
351 | ((pteg_shift + 7) - 18); | |
352 | env->spr[SPR_HIOR] = 0; | |
353 | ||
354 | if (kvm_enabled()) { | |
355 | kvmppc_set_papr(env); | |
356 | } | |
f43e3525 DG |
357 | } |
358 | ||
39ac8455 | 359 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "spapr-rtas.bin"); |
a3467baa DG |
360 | spapr->rtas_size = load_image_targphys(filename, spapr->rtas_addr, |
361 | ram_size - spapr->rtas_addr); | |
362 | if (spapr->rtas_size < 0) { | |
39ac8455 DG |
363 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); |
364 | exit(1); | |
365 | } | |
7267c094 | 366 | g_free(filename); |
39ac8455 | 367 | |
b5cec4c5 | 368 | /* Set up Interrupt Controller */ |
c7a5c0c9 | 369 | spapr->icp = xics_system_init(XICS_IRQS); |
b5cec4c5 DG |
370 | |
371 | /* Set up VIO bus */ | |
4040ab72 DG |
372 | spapr->vio_bus = spapr_vio_bus_init(); |
373 | ||
277f9acf | 374 | for (i = 0; i < MAX_SERIAL_PORTS; i++) { |
4040ab72 | 375 | if (serial_hds[i]) { |
b4a78527 | 376 | spapr_vty_create(spapr->vio_bus, SPAPR_VTY_BASE_ADDRESS + i, |
277f9acf | 377 | serial_hds[i]); |
4040ab72 DG |
378 | } |
379 | } | |
9fdf0c29 | 380 | |
277f9acf | 381 | for (i = 0; i < nb_nics; i++) { |
8d90ad90 DG |
382 | NICInfo *nd = &nd_table[i]; |
383 | ||
384 | if (!nd->model) { | |
7267c094 | 385 | nd->model = g_strdup("ibmveth"); |
8d90ad90 DG |
386 | } |
387 | ||
388 | if (strcmp(nd->model, "ibmveth") == 0) { | |
277f9acf | 389 | spapr_vlan_create(spapr->vio_bus, 0x1000 + i, nd); |
8d90ad90 DG |
390 | } else { |
391 | fprintf(stderr, "pSeries (sPAPR) platform does not support " | |
392 | "NIC model '%s' (only ibmveth is supported)\n", | |
393 | nd->model); | |
394 | exit(1); | |
395 | } | |
396 | } | |
397 | ||
6e270446 | 398 | for (i = 0; i <= drive_get_max_bus(IF_SCSI); i++) { |
277f9acf | 399 | spapr_vscsi_create(spapr->vio_bus, 0x2000 + i); |
6e270446 BH |
400 | } |
401 | ||
9fdf0c29 DG |
402 | if (kernel_filename) { |
403 | uint64_t lowaddr = 0; | |
404 | ||
9fdf0c29 DG |
405 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
406 | NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0); | |
407 | if (kernel_size < 0) { | |
a3467baa DG |
408 | kernel_size = load_image_targphys(kernel_filename, |
409 | KERNEL_LOAD_ADDR, | |
410 | ram_size - KERNEL_LOAD_ADDR); | |
9fdf0c29 DG |
411 | } |
412 | if (kernel_size < 0) { | |
413 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
414 | kernel_filename); | |
415 | exit(1); | |
416 | } | |
417 | ||
418 | /* load initrd */ | |
419 | if (initrd_filename) { | |
420 | initrd_base = INITRD_LOAD_ADDR; | |
421 | initrd_size = load_image_targphys(initrd_filename, initrd_base, | |
422 | ram_size - initrd_base); | |
423 | if (initrd_size < 0) { | |
424 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
425 | initrd_filename); | |
426 | exit(1); | |
427 | } | |
428 | } else { | |
429 | initrd_base = 0; | |
430 | initrd_size = 0; | |
431 | } | |
a3467baa DG |
432 | |
433 | spapr->entry_point = KERNEL_LOAD_ADDR; | |
9fdf0c29 | 434 | } else { |
a9f8ad8f DG |
435 | if (ram_size < (MIN_RAM_SLOF << 20)) { |
436 | fprintf(stderr, "qemu: pSeries SLOF firmware requires >= " | |
437 | "%ldM guest RAM\n", MIN_RAM_SLOF); | |
438 | exit(1); | |
439 | } | |
440 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "slof.bin"); | |
441 | fw_size = load_image_targphys(filename, 0, FW_MAX_SIZE); | |
442 | if (fw_size < 0) { | |
443 | hw_error("qemu: could not load LPAR rtas '%s'\n", filename); | |
444 | exit(1); | |
445 | } | |
7267c094 | 446 | g_free(filename); |
a3467baa | 447 | spapr->entry_point = 0x100; |
a9f8ad8f DG |
448 | initrd_base = 0; |
449 | initrd_size = 0; | |
450 | ||
451 | /* SLOF will startup the secondary CPUs using RTAS, | |
452 | rather than expecting a kexec() style entry */ | |
c7a5c0c9 DG |
453 | for (env = first_cpu; env != NULL; env = env->next_cpu) { |
454 | env->halted = 1; | |
a9f8ad8f | 455 | } |
9fdf0c29 DG |
456 | } |
457 | ||
458 | /* Prepare the device tree */ | |
a3467baa DG |
459 | spapr->fdt_skel = spapr_create_fdt_skel(cpu_model, |
460 | initrd_base, initrd_size, | |
461 | boot_device, kernel_cmdline, | |
462 | pteg_shift + 7); | |
463 | assert(spapr->fdt_skel != NULL); | |
9fdf0c29 | 464 | |
a3467baa | 465 | qemu_register_reset(spapr_reset, spapr); |
9fdf0c29 DG |
466 | } |
467 | ||
468 | static QEMUMachine spapr_machine = { | |
469 | .name = "pseries", | |
470 | .desc = "pSeries Logical Partition (PAPR compliant)", | |
471 | .init = ppc_spapr_init, | |
472 | .max_cpus = MAX_CPUS, | |
473 | .no_vga = 1, | |
474 | .no_parallel = 1, | |
6e270446 | 475 | .use_scsi = 1, |
9fdf0c29 DG |
476 | }; |
477 | ||
478 | static void spapr_machine_init(void) | |
479 | { | |
480 | qemu_register_machine(&spapr_machine); | |
481 | } | |
482 | ||
483 | machine_init(spapr_machine_init); |