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Commit | Line | Data |
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9fdf0c29 DG |
1 | #include "sysemu.h" |
2 | #include "cpu.h" | |
3 | #include "qemu-char.h" | |
f43e3525 DG |
4 | #include "sysemu.h" |
5 | #include "qemu-char.h" | |
ed120055 | 6 | #include "helper_regs.h" |
9fdf0c29 DG |
7 | #include "hw/spapr.h" |
8 | ||
f43e3525 DG |
9 | #define HPTES_PER_GROUP 8 |
10 | ||
11 | #define HPTE_V_SSIZE_SHIFT 62 | |
12 | #define HPTE_V_AVPN_SHIFT 7 | |
13 | #define HPTE_V_AVPN 0x3fffffffffffff80ULL | |
14 | #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) | |
15 | #define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) | |
16 | #define HPTE_V_BOLTED 0x0000000000000010ULL | |
17 | #define HPTE_V_LOCK 0x0000000000000008ULL | |
18 | #define HPTE_V_LARGE 0x0000000000000004ULL | |
19 | #define HPTE_V_SECONDARY 0x0000000000000002ULL | |
20 | #define HPTE_V_VALID 0x0000000000000001ULL | |
21 | ||
22 | #define HPTE_R_PP0 0x8000000000000000ULL | |
23 | #define HPTE_R_TS 0x4000000000000000ULL | |
24 | #define HPTE_R_KEY_HI 0x3000000000000000ULL | |
25 | #define HPTE_R_RPN_SHIFT 12 | |
26 | #define HPTE_R_RPN 0x3ffffffffffff000ULL | |
27 | #define HPTE_R_FLAGS 0x00000000000003ffULL | |
28 | #define HPTE_R_PP 0x0000000000000003ULL | |
29 | #define HPTE_R_N 0x0000000000000004ULL | |
30 | #define HPTE_R_G 0x0000000000000008ULL | |
31 | #define HPTE_R_M 0x0000000000000010ULL | |
32 | #define HPTE_R_I 0x0000000000000020ULL | |
33 | #define HPTE_R_W 0x0000000000000040ULL | |
34 | #define HPTE_R_WIMG 0x0000000000000078ULL | |
35 | #define HPTE_R_C 0x0000000000000080ULL | |
36 | #define HPTE_R_R 0x0000000000000100ULL | |
37 | #define HPTE_R_KEY_LO 0x0000000000000e00ULL | |
38 | ||
39 | #define HPTE_V_1TB_SEG 0x4000000000000000ULL | |
40 | #define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL | |
41 | ||
f43e3525 DG |
42 | static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, |
43 | target_ulong pte_index) | |
44 | { | |
45 | target_ulong rb, va_low; | |
46 | ||
47 | rb = (v & ~0x7fULL) << 16; /* AVA field */ | |
48 | va_low = pte_index >> 3; | |
49 | if (v & HPTE_V_SECONDARY) { | |
50 | va_low = ~va_low; | |
51 | } | |
52 | /* xor vsid from AVA */ | |
53 | if (!(v & HPTE_V_1TB_SEG)) { | |
54 | va_low ^= v >> 12; | |
55 | } else { | |
56 | va_low ^= v >> 24; | |
57 | } | |
58 | va_low &= 0x7ff; | |
59 | if (v & HPTE_V_LARGE) { | |
60 | rb |= 1; /* L field */ | |
61 | #if 0 /* Disable that P7 specific bit for now */ | |
62 | if (r & 0xff000) { | |
63 | /* non-16MB large page, must be 64k */ | |
64 | /* (masks depend on page size) */ | |
65 | rb |= 0x1000; /* page encoding in LP field */ | |
66 | rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */ | |
67 | rb |= (va_low & 0xfe); /* AVAL field */ | |
68 | } | |
69 | #endif | |
70 | } else { | |
71 | /* 4kB page */ | |
72 | rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ | |
73 | } | |
74 | rb |= (v >> 54) & 0x300; /* B field */ | |
75 | return rb; | |
76 | } | |
77 | ||
b13ce26d | 78 | static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
f43e3525 DG |
79 | target_ulong opcode, target_ulong *args) |
80 | { | |
b13ce26d | 81 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
82 | target_ulong flags = args[0]; |
83 | target_ulong pte_index = args[1]; | |
84 | target_ulong pteh = args[2]; | |
85 | target_ulong ptel = args[3]; | |
f73a2575 DG |
86 | target_ulong page_shift = 12; |
87 | target_ulong raddr; | |
1235a9cf | 88 | target_ulong i; |
f43e3525 DG |
89 | uint8_t *hpte; |
90 | ||
91 | /* only handle 4k and 16M pages for now */ | |
f43e3525 DG |
92 | if (pteh & HPTE_V_LARGE) { |
93 | #if 0 /* We don't support 64k pages yet */ | |
94 | if ((ptel & 0xf000) == 0x1000) { | |
95 | /* 64k page */ | |
f43e3525 DG |
96 | } else |
97 | #endif | |
98 | if ((ptel & 0xff000) == 0) { | |
99 | /* 16M page */ | |
f73a2575 | 100 | page_shift = 24; |
f43e3525 DG |
101 | /* lowest AVA bit must be 0 for 16M pages */ |
102 | if (pteh & 0x80) { | |
103 | return H_PARAMETER; | |
104 | } | |
105 | } else { | |
106 | return H_PARAMETER; | |
107 | } | |
108 | } | |
109 | ||
f73a2575 | 110 | raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1); |
f43e3525 | 111 | |
f73a2575 DG |
112 | if (raddr < spapr->ram_limit) { |
113 | /* Regular RAM - should have WIMG=0010 */ | |
114 | if ((ptel & HPTE_R_WIMG) != HPTE_R_M) { | |
115 | return H_PARAMETER; | |
116 | } | |
117 | } else { | |
118 | /* Looks like an IO address */ | |
119 | /* FIXME: What WIMG combinations could be sensible for IO? | |
120 | * For now we allow WIMG=010x, but are there others? */ | |
121 | /* FIXME: Should we check against registered IO addresses? */ | |
122 | if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) { | |
123 | return H_PARAMETER; | |
124 | } | |
f43e3525 | 125 | } |
f73a2575 | 126 | |
f43e3525 DG |
127 | pteh &= ~0x60ULL; |
128 | ||
129 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
130 | return H_PARAMETER; | |
131 | } | |
132 | if (likely((flags & H_EXACT) == 0)) { | |
133 | pte_index &= ~7ULL; | |
134 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
135 | for (i = 0; ; ++i) { | |
136 | if (i == 8) { | |
137 | return H_PTEG_FULL; | |
138 | } | |
35f9304d | 139 | if ((ldq_p(hpte) & HPTE_V_VALID) == 0) { |
f43e3525 DG |
140 | break; |
141 | } | |
142 | hpte += HASH_PTE_SIZE_64; | |
143 | } | |
144 | } else { | |
145 | i = 0; | |
146 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
35f9304d | 147 | if (ldq_p(hpte) & HPTE_V_VALID) { |
f43e3525 DG |
148 | return H_PTEG_FULL; |
149 | } | |
150 | } | |
151 | stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel); | |
152 | /* eieio(); FIXME: need some sort of barrier for smp? */ | |
153 | stq_p(hpte, pteh); | |
154 | ||
f43e3525 DG |
155 | args[0] = pte_index + i; |
156 | return H_SUCCESS; | |
157 | } | |
158 | ||
a3d0abae DG |
159 | enum { |
160 | REMOVE_SUCCESS = 0, | |
161 | REMOVE_NOT_FOUND = 1, | |
162 | REMOVE_PARM = 2, | |
163 | REMOVE_HW = 3, | |
164 | }; | |
165 | ||
e2684c0b | 166 | static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex, |
a3d0abae DG |
167 | target_ulong avpn, |
168 | target_ulong flags, | |
169 | target_ulong *vp, target_ulong *rp) | |
f43e3525 | 170 | { |
f43e3525 DG |
171 | uint8_t *hpte; |
172 | target_ulong v, r, rb; | |
173 | ||
a3d0abae DG |
174 | if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) { |
175 | return REMOVE_PARM; | |
f43e3525 DG |
176 | } |
177 | ||
a3d0abae | 178 | hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64); |
f43e3525 DG |
179 | |
180 | v = ldq_p(hpte); | |
181 | r = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
182 | ||
183 | if ((v & HPTE_V_VALID) == 0 || | |
184 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn) || | |
185 | ((flags & H_ANDCOND) && (v & avpn) != 0)) { | |
a3d0abae | 186 | return REMOVE_NOT_FOUND; |
f43e3525 | 187 | } |
35f9304d | 188 | *vp = v; |
a3d0abae | 189 | *rp = r; |
f43e3525 | 190 | stq_p(hpte, 0); |
a3d0abae | 191 | rb = compute_tlbie_rb(v, r, ptex); |
f43e3525 | 192 | ppc_tlb_invalidate_one(env, rb); |
a3d0abae DG |
193 | return REMOVE_SUCCESS; |
194 | } | |
195 | ||
b13ce26d | 196 | static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
a3d0abae DG |
197 | target_ulong opcode, target_ulong *args) |
198 | { | |
b13ce26d | 199 | CPUPPCState *env = &cpu->env; |
a3d0abae DG |
200 | target_ulong flags = args[0]; |
201 | target_ulong pte_index = args[1]; | |
202 | target_ulong avpn = args[2]; | |
203 | int ret; | |
204 | ||
205 | ret = remove_hpte(env, pte_index, avpn, flags, | |
206 | &args[0], &args[1]); | |
207 | ||
208 | switch (ret) { | |
209 | case REMOVE_SUCCESS: | |
210 | return H_SUCCESS; | |
211 | ||
212 | case REMOVE_NOT_FOUND: | |
213 | return H_NOT_FOUND; | |
214 | ||
215 | case REMOVE_PARM: | |
216 | return H_PARAMETER; | |
217 | ||
218 | case REMOVE_HW: | |
219 | return H_HARDWARE; | |
220 | } | |
221 | ||
222 | assert(0); | |
223 | } | |
224 | ||
225 | #define H_BULK_REMOVE_TYPE 0xc000000000000000ULL | |
226 | #define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL | |
227 | #define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL | |
228 | #define H_BULK_REMOVE_END 0xc000000000000000ULL | |
229 | #define H_BULK_REMOVE_CODE 0x3000000000000000ULL | |
230 | #define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL | |
231 | #define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL | |
232 | #define H_BULK_REMOVE_PARM 0x2000000000000000ULL | |
233 | #define H_BULK_REMOVE_HW 0x3000000000000000ULL | |
234 | #define H_BULK_REMOVE_RC 0x0c00000000000000ULL | |
235 | #define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL | |
236 | #define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL | |
237 | #define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL | |
238 | #define H_BULK_REMOVE_AVPN 0x0200000000000000ULL | |
239 | #define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL | |
240 | ||
241 | #define H_BULK_REMOVE_MAX_BATCH 4 | |
242 | ||
b13ce26d | 243 | static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
a3d0abae DG |
244 | target_ulong opcode, target_ulong *args) |
245 | { | |
b13ce26d | 246 | CPUPPCState *env = &cpu->env; |
a3d0abae DG |
247 | int i; |
248 | ||
249 | for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { | |
250 | target_ulong *tsh = &args[i*2]; | |
251 | target_ulong tsl = args[i*2 + 1]; | |
252 | target_ulong v, r, ret; | |
253 | ||
254 | if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) { | |
255 | break; | |
256 | } else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { | |
257 | return H_PARAMETER; | |
258 | } | |
259 | ||
260 | *tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; | |
261 | *tsh |= H_BULK_REMOVE_RESPONSE; | |
262 | ||
263 | if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) { | |
264 | *tsh |= H_BULK_REMOVE_PARM; | |
265 | return H_PARAMETER; | |
266 | } | |
267 | ||
268 | ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl, | |
269 | (*tsh & H_BULK_REMOVE_FLAGS) >> 26, | |
270 | &v, &r); | |
271 | ||
272 | *tsh |= ret << 60; | |
273 | ||
274 | switch (ret) { | |
275 | case REMOVE_SUCCESS: | |
276 | *tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43; | |
277 | break; | |
278 | ||
279 | case REMOVE_PARM: | |
280 | return H_PARAMETER; | |
281 | ||
282 | case REMOVE_HW: | |
283 | return H_HARDWARE; | |
284 | } | |
285 | } | |
286 | ||
f43e3525 DG |
287 | return H_SUCCESS; |
288 | } | |
289 | ||
b13ce26d | 290 | static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
f43e3525 DG |
291 | target_ulong opcode, target_ulong *args) |
292 | { | |
b13ce26d | 293 | CPUPPCState *env = &cpu->env; |
f43e3525 DG |
294 | target_ulong flags = args[0]; |
295 | target_ulong pte_index = args[1]; | |
296 | target_ulong avpn = args[2]; | |
297 | uint8_t *hpte; | |
298 | target_ulong v, r, rb; | |
299 | ||
300 | if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) { | |
301 | return H_PARAMETER; | |
302 | } | |
303 | ||
304 | hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); | |
f43e3525 DG |
305 | |
306 | v = ldq_p(hpte); | |
307 | r = ldq_p(hpte + (HASH_PTE_SIZE_64/2)); | |
308 | ||
309 | if ((v & HPTE_V_VALID) == 0 || | |
310 | ((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) { | |
f43e3525 DG |
311 | return H_NOT_FOUND; |
312 | } | |
313 | ||
314 | r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N | | |
315 | HPTE_R_KEY_HI | HPTE_R_KEY_LO); | |
316 | r |= (flags << 55) & HPTE_R_PP0; | |
317 | r |= (flags << 48) & HPTE_R_KEY_HI; | |
318 | r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO); | |
319 | rb = compute_tlbie_rb(v, r, pte_index); | |
320 | stq_p(hpte, v & ~HPTE_V_VALID); | |
321 | ppc_tlb_invalidate_one(env, rb); | |
322 | stq_p(hpte + (HASH_PTE_SIZE_64/2), r); | |
323 | /* Don't need a memory barrier, due to qemu's global lock */ | |
35f9304d | 324 | stq_p(hpte, v); |
f43e3525 DG |
325 | return H_SUCCESS; |
326 | } | |
327 | ||
b13ce26d | 328 | static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
821303f5 DG |
329 | target_ulong opcode, target_ulong *args) |
330 | { | |
331 | /* FIXME: actually implement this */ | |
332 | return H_HARDWARE; | |
333 | } | |
334 | ||
ed120055 DG |
335 | #define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
336 | #define FLAGS_REGISTER_DTL 0x0000400000000000ULL | |
337 | #define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL | |
338 | #define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL | |
339 | #define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL | |
340 | #define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL | |
341 | ||
342 | #define VPA_MIN_SIZE 640 | |
343 | #define VPA_SIZE_OFFSET 0x4 | |
344 | #define VPA_SHARED_PROC_OFFSET 0x9 | |
345 | #define VPA_SHARED_PROC_VAL 0x2 | |
346 | ||
e2684c0b | 347 | static target_ulong register_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 DG |
348 | { |
349 | uint16_t size; | |
350 | uint8_t tmp; | |
351 | ||
352 | if (vpa == 0) { | |
353 | hcall_dprintf("Can't cope with registering a VPA at logical 0\n"); | |
354 | return H_HARDWARE; | |
355 | } | |
356 | ||
357 | if (vpa % env->dcache_line_size) { | |
358 | return H_PARAMETER; | |
359 | } | |
360 | /* FIXME: bounds check the address */ | |
361 | ||
06c46bba | 362 | size = lduw_be_phys(vpa + 0x4); |
ed120055 DG |
363 | |
364 | if (size < VPA_MIN_SIZE) { | |
365 | return H_PARAMETER; | |
366 | } | |
367 | ||
368 | /* VPA is not allowed to cross a page boundary */ | |
369 | if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { | |
370 | return H_PARAMETER; | |
371 | } | |
372 | ||
1bfb37d1 | 373 | env->vpa_addr = vpa; |
ed120055 | 374 | |
1bfb37d1 | 375 | tmp = ldub_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET); |
ed120055 | 376 | tmp |= VPA_SHARED_PROC_VAL; |
1bfb37d1 | 377 | stb_phys(env->vpa_addr + VPA_SHARED_PROC_OFFSET, tmp); |
ed120055 DG |
378 | |
379 | return H_SUCCESS; | |
380 | } | |
381 | ||
e2684c0b | 382 | static target_ulong deregister_vpa(CPUPPCState *env, target_ulong vpa) |
ed120055 | 383 | { |
1bfb37d1 | 384 | if (env->slb_shadow_addr) { |
ed120055 DG |
385 | return H_RESOURCE; |
386 | } | |
387 | ||
1bfb37d1 | 388 | if (env->dtl_addr) { |
ed120055 DG |
389 | return H_RESOURCE; |
390 | } | |
391 | ||
1bfb37d1 | 392 | env->vpa_addr = 0; |
ed120055 DG |
393 | return H_SUCCESS; |
394 | } | |
395 | ||
e2684c0b | 396 | static target_ulong register_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 DG |
397 | { |
398 | uint32_t size; | |
399 | ||
400 | if (addr == 0) { | |
401 | hcall_dprintf("Can't cope with SLB shadow at logical 0\n"); | |
402 | return H_HARDWARE; | |
403 | } | |
404 | ||
06c46bba | 405 | size = ldl_be_phys(addr + 0x4); |
ed120055 DG |
406 | if (size < 0x8) { |
407 | return H_PARAMETER; | |
408 | } | |
409 | ||
410 | if ((addr / 4096) != ((addr + size - 1) / 4096)) { | |
411 | return H_PARAMETER; | |
412 | } | |
413 | ||
1bfb37d1 | 414 | if (!env->vpa_addr) { |
ed120055 DG |
415 | return H_RESOURCE; |
416 | } | |
417 | ||
1bfb37d1 DG |
418 | env->slb_shadow_addr = addr; |
419 | env->slb_shadow_size = size; | |
ed120055 DG |
420 | |
421 | return H_SUCCESS; | |
422 | } | |
423 | ||
e2684c0b | 424 | static target_ulong deregister_slb_shadow(CPUPPCState *env, target_ulong addr) |
ed120055 | 425 | { |
1bfb37d1 DG |
426 | env->slb_shadow_addr = 0; |
427 | env->slb_shadow_size = 0; | |
ed120055 DG |
428 | return H_SUCCESS; |
429 | } | |
430 | ||
e2684c0b | 431 | static target_ulong register_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 DG |
432 | { |
433 | uint32_t size; | |
434 | ||
435 | if (addr == 0) { | |
436 | hcall_dprintf("Can't cope with DTL at logical 0\n"); | |
437 | return H_HARDWARE; | |
438 | } | |
439 | ||
06c46bba | 440 | size = ldl_be_phys(addr + 0x4); |
ed120055 DG |
441 | |
442 | if (size < 48) { | |
443 | return H_PARAMETER; | |
444 | } | |
445 | ||
1bfb37d1 | 446 | if (!env->vpa_addr) { |
ed120055 DG |
447 | return H_RESOURCE; |
448 | } | |
449 | ||
1bfb37d1 | 450 | env->dtl_addr = addr; |
ed120055 DG |
451 | env->dtl_size = size; |
452 | ||
453 | return H_SUCCESS; | |
454 | } | |
455 | ||
73f7821b | 456 | static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) |
ed120055 | 457 | { |
1bfb37d1 | 458 | env->dtl_addr = 0; |
ed120055 DG |
459 | env->dtl_size = 0; |
460 | ||
461 | return H_SUCCESS; | |
462 | } | |
463 | ||
b13ce26d | 464 | static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
ed120055 DG |
465 | target_ulong opcode, target_ulong *args) |
466 | { | |
467 | target_ulong flags = args[0]; | |
468 | target_ulong procno = args[1]; | |
469 | target_ulong vpa = args[2]; | |
470 | target_ulong ret = H_PARAMETER; | |
e2684c0b | 471 | CPUPPCState *tenv; |
ed120055 DG |
472 | |
473 | for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) { | |
474 | if (tenv->cpu_index == procno) { | |
475 | break; | |
476 | } | |
477 | } | |
478 | ||
479 | if (!tenv) { | |
480 | return H_PARAMETER; | |
481 | } | |
482 | ||
483 | switch (flags) { | |
484 | case FLAGS_REGISTER_VPA: | |
485 | ret = register_vpa(tenv, vpa); | |
486 | break; | |
487 | ||
488 | case FLAGS_DEREGISTER_VPA: | |
489 | ret = deregister_vpa(tenv, vpa); | |
490 | break; | |
491 | ||
492 | case FLAGS_REGISTER_SLBSHADOW: | |
493 | ret = register_slb_shadow(tenv, vpa); | |
494 | break; | |
495 | ||
496 | case FLAGS_DEREGISTER_SLBSHADOW: | |
497 | ret = deregister_slb_shadow(tenv, vpa); | |
498 | break; | |
499 | ||
500 | case FLAGS_REGISTER_DTL: | |
501 | ret = register_dtl(tenv, vpa); | |
502 | break; | |
503 | ||
504 | case FLAGS_DEREGISTER_DTL: | |
505 | ret = deregister_dtl(tenv, vpa); | |
506 | break; | |
507 | } | |
508 | ||
509 | return ret; | |
510 | } | |
511 | ||
b13ce26d | 512 | static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
ed120055 DG |
513 | target_ulong opcode, target_ulong *args) |
514 | { | |
b13ce26d AF |
515 | CPUPPCState *env = &cpu->env; |
516 | ||
ed120055 DG |
517 | env->msr |= (1ULL << MSR_EE); |
518 | hreg_compute_hflags(env); | |
3993c6bd | 519 | if (!cpu_has_work(CPU(cpu))) { |
ed120055 | 520 | env->halted = 1; |
1dd08894 DG |
521 | env->exception_index = EXCP_HLT; |
522 | env->exit_request = 1; | |
ed120055 DG |
523 | } |
524 | return H_SUCCESS; | |
525 | } | |
526 | ||
b13ce26d | 527 | static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
39ac8455 DG |
528 | target_ulong opcode, target_ulong *args) |
529 | { | |
530 | target_ulong rtas_r3 = args[0]; | |
06c46bba AG |
531 | uint32_t token = ldl_be_phys(rtas_r3); |
532 | uint32_t nargs = ldl_be_phys(rtas_r3 + 4); | |
533 | uint32_t nret = ldl_be_phys(rtas_r3 + 8); | |
39ac8455 DG |
534 | |
535 | return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12, | |
536 | nret, rtas_r3 + 12 + 4*nargs); | |
537 | } | |
538 | ||
b13ce26d | 539 | static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
540 | target_ulong opcode, target_ulong *args) |
541 | { | |
542 | target_ulong size = args[0]; | |
543 | target_ulong addr = args[1]; | |
544 | ||
545 | switch (size) { | |
546 | case 1: | |
547 | args[0] = ldub_phys(addr); | |
548 | return H_SUCCESS; | |
549 | case 2: | |
550 | args[0] = lduw_phys(addr); | |
551 | return H_SUCCESS; | |
552 | case 4: | |
553 | args[0] = ldl_phys(addr); | |
554 | return H_SUCCESS; | |
555 | case 8: | |
556 | args[0] = ldq_phys(addr); | |
557 | return H_SUCCESS; | |
558 | } | |
559 | return H_PARAMETER; | |
560 | } | |
561 | ||
b13ce26d | 562 | static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
563 | target_ulong opcode, target_ulong *args) |
564 | { | |
565 | target_ulong size = args[0]; | |
566 | target_ulong addr = args[1]; | |
567 | target_ulong val = args[2]; | |
568 | ||
569 | switch (size) { | |
570 | case 1: | |
571 | stb_phys(addr, val); | |
572 | return H_SUCCESS; | |
573 | case 2: | |
574 | stw_phys(addr, val); | |
575 | return H_SUCCESS; | |
576 | case 4: | |
577 | stl_phys(addr, val); | |
578 | return H_SUCCESS; | |
579 | case 8: | |
580 | stq_phys(addr, val); | |
581 | return H_SUCCESS; | |
582 | } | |
583 | return H_PARAMETER; | |
584 | } | |
585 | ||
b13ce26d | 586 | static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
c73e3771 BH |
587 | target_ulong opcode, target_ulong *args) |
588 | { | |
589 | target_ulong dst = args[0]; /* Destination address */ | |
590 | target_ulong src = args[1]; /* Source address */ | |
591 | target_ulong esize = args[2]; /* Element size (0=1,1=2,2=4,3=8) */ | |
592 | target_ulong count = args[3]; /* Element count */ | |
593 | target_ulong op = args[4]; /* 0 = copy, 1 = invert */ | |
594 | uint64_t tmp; | |
595 | unsigned int mask = (1 << esize) - 1; | |
596 | int step = 1 << esize; | |
597 | ||
598 | if (count > 0x80000000) { | |
599 | return H_PARAMETER; | |
600 | } | |
601 | ||
602 | if ((dst & mask) || (src & mask) || (op > 1)) { | |
603 | return H_PARAMETER; | |
604 | } | |
605 | ||
606 | if (dst >= src && dst < (src + (count << esize))) { | |
607 | dst = dst + ((count - 1) << esize); | |
608 | src = src + ((count - 1) << esize); | |
609 | step = -step; | |
610 | } | |
611 | ||
612 | while (count--) { | |
613 | switch (esize) { | |
614 | case 0: | |
615 | tmp = ldub_phys(src); | |
616 | break; | |
617 | case 1: | |
618 | tmp = lduw_phys(src); | |
619 | break; | |
620 | case 2: | |
621 | tmp = ldl_phys(src); | |
622 | break; | |
623 | case 3: | |
624 | tmp = ldq_phys(src); | |
625 | break; | |
626 | default: | |
627 | return H_PARAMETER; | |
628 | } | |
629 | if (op == 1) { | |
630 | tmp = ~tmp; | |
631 | } | |
632 | switch (esize) { | |
633 | case 0: | |
634 | stb_phys(dst, tmp); | |
635 | break; | |
636 | case 1: | |
637 | stw_phys(dst, tmp); | |
638 | break; | |
639 | case 2: | |
640 | stl_phys(dst, tmp); | |
641 | break; | |
642 | case 3: | |
643 | stq_phys(dst, tmp); | |
644 | break; | |
645 | } | |
646 | dst = dst + step; | |
647 | src = src + step; | |
648 | } | |
649 | ||
650 | return H_SUCCESS; | |
651 | } | |
652 | ||
b13ce26d | 653 | static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
654 | target_ulong opcode, target_ulong *args) |
655 | { | |
656 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
657 | return H_SUCCESS; | |
658 | } | |
659 | ||
b13ce26d | 660 | static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr, |
827200a2 DG |
661 | target_ulong opcode, target_ulong *args) |
662 | { | |
663 | /* Nothing to do on emulation, KVM will trap this in the kernel */ | |
664 | return H_SUCCESS; | |
665 | } | |
666 | ||
7d7ba3fe DG |
667 | static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
668 | static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; | |
9fdf0c29 DG |
669 | |
670 | void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) | |
671 | { | |
39ac8455 DG |
672 | spapr_hcall_fn *slot; |
673 | ||
674 | if (opcode <= MAX_HCALL_OPCODE) { | |
675 | assert((opcode & 0x3) == 0); | |
9fdf0c29 | 676 | |
39ac8455 DG |
677 | slot = &papr_hypercall_table[opcode / 4]; |
678 | } else { | |
679 | assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); | |
9fdf0c29 | 680 | |
39ac8455 DG |
681 | slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
682 | } | |
9fdf0c29 | 683 | |
c89d5299 | 684 | assert(!(*slot)); |
39ac8455 | 685 | *slot = fn; |
9fdf0c29 DG |
686 | } |
687 | ||
aa100fa4 | 688 | target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, |
9fdf0c29 DG |
689 | target_ulong *args) |
690 | { | |
9fdf0c29 DG |
691 | if ((opcode <= MAX_HCALL_OPCODE) |
692 | && ((opcode & 0x3) == 0)) { | |
39ac8455 DG |
693 | spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; |
694 | ||
695 | if (fn) { | |
b13ce26d | 696 | return fn(cpu, spapr, opcode, args); |
39ac8455 DG |
697 | } |
698 | } else if ((opcode >= KVMPPC_HCALL_BASE) && | |
699 | (opcode <= KVMPPC_HCALL_MAX)) { | |
700 | spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; | |
9fdf0c29 DG |
701 | |
702 | if (fn) { | |
b13ce26d | 703 | return fn(cpu, spapr, opcode, args); |
9fdf0c29 DG |
704 | } |
705 | } | |
706 | ||
707 | hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); | |
708 | return H_FUNCTION; | |
709 | } | |
f43e3525 | 710 | |
83f7d43a | 711 | static void hypercall_register_types(void) |
f43e3525 DG |
712 | { |
713 | /* hcall-pft */ | |
714 | spapr_register_hypercall(H_ENTER, h_enter); | |
715 | spapr_register_hypercall(H_REMOVE, h_remove); | |
716 | spapr_register_hypercall(H_PROTECT, h_protect); | |
39ac8455 | 717 | |
a3d0abae DG |
718 | /* hcall-bulk */ |
719 | spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); | |
720 | ||
821303f5 DG |
721 | /* hcall-dabr */ |
722 | spapr_register_hypercall(H_SET_DABR, h_set_dabr); | |
723 | ||
ed120055 DG |
724 | /* hcall-splpar */ |
725 | spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); | |
726 | spapr_register_hypercall(H_CEDE, h_cede); | |
727 | ||
827200a2 DG |
728 | /* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate |
729 | * here between the "CI" and the "CACHE" variants, they will use whatever | |
730 | * mapping attributes qemu is using. When using KVM, the kernel will | |
731 | * enforce the attributes more strongly | |
732 | */ | |
733 | spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); | |
734 | spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); | |
735 | spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); | |
736 | spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); | |
737 | spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); | |
738 | spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); | |
c73e3771 | 739 | spapr_register_hypercall(KVMPPC_H_LOGICAL_MEMOP, h_logical_memop); |
827200a2 | 740 | |
39ac8455 DG |
741 | /* qemu/KVM-PPC specific hcalls */ |
742 | spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); | |
f43e3525 | 743 | } |
83f7d43a AF |
744 | |
745 | type_init(hypercall_register_types) |