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3384f95c DG |
1 | /* |
2 | * QEMU sPAPR PCI host originated from Uninorth PCI host | |
3 | * | |
4 | * Copyright (c) 2011 Alexey Kardashevskiy, IBM Corporation. | |
5 | * Copyright (C) 2011 David Gibson, IBM Corporation. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | #include "hw.h" | |
26 | #include "pci.h" | |
27 | #include "pci_host.h" | |
28 | #include "hw/spapr.h" | |
29 | #include "hw/spapr_pci.h" | |
30 | #include "exec-memory.h" | |
31 | #include <libfdt.h> | |
32 | ||
33 | #include "hw/pci_internals.h" | |
34 | ||
3384f95c DG |
35 | static PCIDevice *find_dev(sPAPREnvironment *spapr, |
36 | uint64_t buid, uint32_t config_addr) | |
37 | { | |
38 | DeviceState *qdev; | |
39 | int devfn = (config_addr >> 8) & 0xFF; | |
40 | sPAPRPHBState *phb; | |
41 | ||
42 | QLIST_FOREACH(phb, &spapr->phbs, list) { | |
43 | if (phb->buid != buid) { | |
44 | continue; | |
45 | } | |
46 | ||
3a26360d | 47 | QTAILQ_FOREACH(qdev, &phb->host_state.bus->qbus.children, sibling) { |
3384f95c DG |
48 | PCIDevice *dev = (PCIDevice *)qdev; |
49 | if (dev->devfn == devfn) { | |
50 | return dev; | |
51 | } | |
52 | } | |
53 | } | |
54 | ||
55 | return NULL; | |
56 | } | |
57 | ||
3f7565c9 BH |
58 | static uint32_t rtas_pci_cfgaddr(uint32_t arg) |
59 | { | |
92615a5a | 60 | /* This handles the encoding of extended config space addresses */ |
3f7565c9 BH |
61 | return ((arg >> 20) & 0xf00) | (arg & 0xff); |
62 | } | |
63 | ||
92615a5a DG |
64 | static void finish_read_pci_config(sPAPREnvironment *spapr, uint64_t buid, |
65 | uint32_t addr, uint32_t size, | |
66 | target_ulong rets) | |
88045ac5 | 67 | { |
92615a5a DG |
68 | PCIDevice *pci_dev; |
69 | uint32_t val; | |
70 | ||
71 | if ((size != 1) && (size != 2) && (size != 4)) { | |
72 | /* access must be 1, 2 or 4 bytes */ | |
73 | rtas_st(rets, 0, -1); | |
74 | return; | |
88045ac5 | 75 | } |
88045ac5 | 76 | |
92615a5a DG |
77 | pci_dev = find_dev(spapr, buid, addr); |
78 | addr = rtas_pci_cfgaddr(addr); | |
79 | ||
80 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
81 | /* Access must be to a valid device, within bounds and | |
82 | * naturally aligned */ | |
83 | rtas_st(rets, 0, -1); | |
84 | return; | |
88045ac5 | 85 | } |
92615a5a DG |
86 | |
87 | val = pci_host_config_read_common(pci_dev, addr, | |
88 | pci_config_size(pci_dev), size); | |
89 | ||
90 | rtas_st(rets, 0, 0); | |
91 | rtas_st(rets, 1, val); | |
88045ac5 AG |
92 | } |
93 | ||
3384f95c DG |
94 | static void rtas_ibm_read_pci_config(sPAPREnvironment *spapr, |
95 | uint32_t token, uint32_t nargs, | |
96 | target_ulong args, | |
97 | uint32_t nret, target_ulong rets) | |
98 | { | |
92615a5a DG |
99 | uint64_t buid; |
100 | uint32_t size, addr; | |
3384f95c | 101 | |
92615a5a | 102 | if ((nargs != 4) || (nret != 2)) { |
3384f95c DG |
103 | rtas_st(rets, 0, -1); |
104 | return; | |
105 | } | |
92615a5a DG |
106 | |
107 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c | 108 | size = rtas_ld(args, 3); |
92615a5a DG |
109 | addr = rtas_ld(args, 0); |
110 | ||
111 | finish_read_pci_config(spapr, buid, addr, size, rets); | |
3384f95c DG |
112 | } |
113 | ||
114 | static void rtas_read_pci_config(sPAPREnvironment *spapr, | |
115 | uint32_t token, uint32_t nargs, | |
116 | target_ulong args, | |
117 | uint32_t nret, target_ulong rets) | |
118 | { | |
92615a5a | 119 | uint32_t size, addr; |
3384f95c | 120 | |
92615a5a | 121 | if ((nargs != 2) || (nret != 2)) { |
3384f95c DG |
122 | rtas_st(rets, 0, -1); |
123 | return; | |
124 | } | |
92615a5a | 125 | |
3384f95c | 126 | size = rtas_ld(args, 1); |
92615a5a DG |
127 | addr = rtas_ld(args, 0); |
128 | ||
129 | finish_read_pci_config(spapr, 0, addr, size, rets); | |
130 | } | |
131 | ||
132 | static void finish_write_pci_config(sPAPREnvironment *spapr, uint64_t buid, | |
133 | uint32_t addr, uint32_t size, | |
134 | uint32_t val, target_ulong rets) | |
135 | { | |
136 | PCIDevice *pci_dev; | |
137 | ||
138 | if ((size != 1) && (size != 2) && (size != 4)) { | |
139 | /* access must be 1, 2 or 4 bytes */ | |
140 | rtas_st(rets, 0, -1); | |
141 | return; | |
142 | } | |
143 | ||
144 | pci_dev = find_dev(spapr, buid, addr); | |
145 | addr = rtas_pci_cfgaddr(addr); | |
146 | ||
147 | if (!pci_dev || (addr % size) || (addr >= pci_config_size(pci_dev))) { | |
148 | /* Access must be to a valid device, within bounds and | |
149 | * naturally aligned */ | |
150 | rtas_st(rets, 0, -1); | |
151 | return; | |
152 | } | |
153 | ||
154 | pci_host_config_write_common(pci_dev, addr, pci_config_size(pci_dev), | |
155 | val, size); | |
156 | ||
3384f95c | 157 | rtas_st(rets, 0, 0); |
3384f95c DG |
158 | } |
159 | ||
160 | static void rtas_ibm_write_pci_config(sPAPREnvironment *spapr, | |
161 | uint32_t token, uint32_t nargs, | |
162 | target_ulong args, | |
163 | uint32_t nret, target_ulong rets) | |
164 | { | |
92615a5a | 165 | uint64_t buid; |
3384f95c | 166 | uint32_t val, size, addr; |
3384f95c | 167 | |
92615a5a | 168 | if ((nargs != 5) || (nret != 1)) { |
3384f95c DG |
169 | rtas_st(rets, 0, -1); |
170 | return; | |
171 | } | |
92615a5a DG |
172 | |
173 | buid = ((uint64_t)rtas_ld(args, 1) << 32) | rtas_ld(args, 2); | |
3384f95c DG |
174 | val = rtas_ld(args, 4); |
175 | size = rtas_ld(args, 3); | |
92615a5a DG |
176 | addr = rtas_ld(args, 0); |
177 | ||
178 | finish_write_pci_config(spapr, buid, addr, size, val, rets); | |
3384f95c DG |
179 | } |
180 | ||
181 | static void rtas_write_pci_config(sPAPREnvironment *spapr, | |
182 | uint32_t token, uint32_t nargs, | |
183 | target_ulong args, | |
184 | uint32_t nret, target_ulong rets) | |
185 | { | |
186 | uint32_t val, size, addr; | |
3384f95c | 187 | |
92615a5a | 188 | if ((nargs != 3) || (nret != 1)) { |
3384f95c DG |
189 | rtas_st(rets, 0, -1); |
190 | return; | |
191 | } | |
92615a5a DG |
192 | |
193 | ||
3384f95c DG |
194 | val = rtas_ld(args, 2); |
195 | size = rtas_ld(args, 1); | |
92615a5a DG |
196 | addr = rtas_ld(args, 0); |
197 | ||
198 | finish_write_pci_config(spapr, 0, addr, size, val, rets); | |
3384f95c DG |
199 | } |
200 | ||
201 | static int pci_spapr_map_irq(PCIDevice *pci_dev, int irq_num) | |
202 | { | |
203 | /* | |
204 | * Here we need to convert pci_dev + irq_num to some unique value | |
205 | * which is less than number of IRQs on the specific bus (now it | |
206 | * is 16). At the moment irq_num == device_id (number of the | |
207 | * slot?) | |
208 | * FIXME: we should swizzle in fn and irq_num | |
209 | */ | |
210 | return (pci_dev->devfn >> 3) % SPAPR_PCI_NUM_LSI; | |
211 | } | |
212 | ||
213 | static void pci_spapr_set_irq(void *opaque, int irq_num, int level) | |
214 | { | |
215 | /* | |
216 | * Here we use the number returned by pci_spapr_map_irq to find a | |
217 | * corresponding qemu_irq. | |
218 | */ | |
219 | sPAPRPHBState *phb = opaque; | |
220 | ||
221 | qemu_set_irq(phb->lsi_table[irq_num].qirq, level); | |
222 | } | |
223 | ||
3384f95c DG |
224 | static uint64_t spapr_io_read(void *opaque, target_phys_addr_t addr, |
225 | unsigned size) | |
226 | { | |
227 | switch (size) { | |
228 | case 1: | |
229 | return cpu_inb(addr); | |
230 | case 2: | |
231 | return cpu_inw(addr); | |
232 | case 4: | |
233 | return cpu_inl(addr); | |
234 | } | |
235 | assert(0); | |
236 | } | |
237 | ||
238 | static void spapr_io_write(void *opaque, target_phys_addr_t addr, | |
239 | uint64_t data, unsigned size) | |
240 | { | |
241 | switch (size) { | |
242 | case 1: | |
243 | cpu_outb(addr, data); | |
244 | return; | |
245 | case 2: | |
246 | cpu_outw(addr, data); | |
247 | return; | |
248 | case 4: | |
249 | cpu_outl(addr, data); | |
250 | return; | |
251 | } | |
252 | assert(0); | |
253 | } | |
254 | ||
a348f108 | 255 | static const MemoryRegionOps spapr_io_ops = { |
3384f95c DG |
256 | .endianness = DEVICE_LITTLE_ENDIAN, |
257 | .read = spapr_io_read, | |
258 | .write = spapr_io_write | |
259 | }; | |
260 | ||
298a9710 DG |
261 | /* |
262 | * PHB PCI device | |
263 | */ | |
264 | static int spapr_phb_init(SysBusDevice *s) | |
3384f95c | 265 | { |
298a9710 DG |
266 | sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s); |
267 | char *namebuf; | |
268 | int i; | |
3384f95c | 269 | PCIBus *bus; |
3384f95c | 270 | |
298a9710 DG |
271 | phb->dtbusname = g_strdup_printf("pci@%" PRIx64, phb->buid); |
272 | namebuf = alloca(strlen(phb->dtbusname) + 32); | |
3384f95c | 273 | |
298a9710 DG |
274 | /* Initialize memory regions */ |
275 | sprintf(namebuf, "%s.mmio", phb->dtbusname); | |
3384f95c DG |
276 | memory_region_init(&phb->memspace, namebuf, INT64_MAX); |
277 | ||
298a9710 | 278 | sprintf(namebuf, "%s.mmio-alias", phb->dtbusname); |
3384f95c | 279 | memory_region_init_alias(&phb->memwindow, namebuf, &phb->memspace, |
298a9710 DG |
280 | SPAPR_PCI_MEM_WIN_BUS_OFFSET, phb->mem_win_size); |
281 | memory_region_add_subregion(get_system_memory(), phb->mem_win_addr, | |
3384f95c DG |
282 | &phb->memwindow); |
283 | ||
3384f95c DG |
284 | /* On ppc, we only have MMIO no specific IO space from the CPU |
285 | * perspective. In theory we ought to be able to embed the PCI IO | |
286 | * memory region direction in the system memory space. However, | |
287 | * if any of the IO BAR subregions use the old_portio mechanism, | |
288 | * that won't be processed properly unless accessed from the | |
289 | * system io address space. This hack to bounce things via | |
290 | * system_io works around the problem until all the users of | |
291 | * old_portion are updated */ | |
298a9710 | 292 | sprintf(namebuf, "%s.io", phb->dtbusname); |
3384f95c DG |
293 | memory_region_init(&phb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE); |
294 | /* FIXME: fix to support multiple PHBs */ | |
295 | memory_region_add_subregion(get_system_io(), 0, &phb->iospace); | |
296 | ||
298a9710 | 297 | sprintf(namebuf, "%s.io-alias", phb->dtbusname); |
3384f95c DG |
298 | memory_region_init_io(&phb->iowindow, &spapr_io_ops, phb, |
299 | namebuf, SPAPR_PCI_IO_WIN_SIZE); | |
298a9710 | 300 | memory_region_add_subregion(get_system_memory(), phb->io_win_addr, |
3384f95c DG |
301 | &phb->iowindow); |
302 | ||
298a9710 DG |
303 | bus = pci_register_bus(&phb->busdev.qdev, |
304 | phb->busname ? phb->busname : phb->dtbusname, | |
305 | pci_spapr_set_irq, pci_spapr_map_irq, phb, | |
306 | &phb->memspace, &phb->iospace, | |
307 | PCI_DEVFN(0, 0), SPAPR_PCI_NUM_LSI); | |
308 | phb->host_state.bus = bus; | |
309 | ||
310 | QLIST_INSERT_HEAD(&spapr->phbs, phb, list); | |
311 | ||
312 | /* Initialize the LSI table */ | |
313 | for (i = 0; i < SPAPR_PCI_NUM_LSI; i++) { | |
314 | qemu_irq qirq; | |
315 | uint32_t num; | |
316 | ||
317 | qirq = spapr_allocate_lsi(0, &num); | |
318 | if (!qirq) { | |
319 | return -1; | |
320 | } | |
321 | ||
322 | phb->lsi_table[i].dt_irq = num; | |
323 | phb->lsi_table[i].qirq = qirq; | |
324 | } | |
325 | ||
326 | return 0; | |
327 | } | |
328 | ||
329 | static Property spapr_phb_properties[] = { | |
330 | DEFINE_PROP_HEX64("buid", sPAPRPHBState, buid, 0), | |
331 | DEFINE_PROP_STRING("busname", sPAPRPHBState, busname), | |
332 | DEFINE_PROP_HEX64("mem_win_addr", sPAPRPHBState, mem_win_addr, 0), | |
333 | DEFINE_PROP_HEX64("mem_win_size", sPAPRPHBState, mem_win_size, 0x20000000), | |
334 | DEFINE_PROP_HEX64("io_win_addr", sPAPRPHBState, io_win_addr, 0), | |
335 | DEFINE_PROP_HEX64("io_win_size", sPAPRPHBState, io_win_size, 0x10000), | |
336 | DEFINE_PROP_END_OF_LIST(), | |
337 | }; | |
338 | ||
339 | static void spapr_phb_class_init(ObjectClass *klass, void *data) | |
340 | { | |
341 | SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass); | |
342 | DeviceClass *dc = DEVICE_CLASS(klass); | |
343 | ||
344 | sdc->init = spapr_phb_init; | |
345 | dc->props = spapr_phb_properties; | |
3384f95c DG |
346 | |
347 | spapr_rtas_register("read-pci-config", rtas_read_pci_config); | |
348 | spapr_rtas_register("write-pci-config", rtas_write_pci_config); | |
349 | spapr_rtas_register("ibm,read-pci-config", rtas_ibm_read_pci_config); | |
350 | spapr_rtas_register("ibm,write-pci-config", rtas_ibm_write_pci_config); | |
298a9710 | 351 | } |
3384f95c | 352 | |
298a9710 DG |
353 | static TypeInfo spapr_phb_info = { |
354 | .name = "spapr-pci-host-bridge", | |
355 | .parent = TYPE_SYS_BUS_DEVICE, | |
356 | .instance_size = sizeof(sPAPRPHBState), | |
357 | .class_init = spapr_phb_class_init, | |
358 | }; | |
359 | ||
360 | void spapr_create_phb(sPAPREnvironment *spapr, | |
361 | const char *busname, uint64_t buid, | |
362 | uint64_t mem_win_addr, uint64_t mem_win_size, | |
363 | uint64_t io_win_addr) | |
364 | { | |
365 | DeviceState *dev; | |
366 | ||
367 | dev = qdev_create(NULL, spapr_phb_info.name); | |
3384f95c | 368 | |
298a9710 DG |
369 | if (busname) { |
370 | qdev_prop_set_string(dev, "busname", g_strdup(busname)); | |
371 | } | |
372 | qdev_prop_set_uint64(dev, "buid", buid); | |
373 | qdev_prop_set_uint64(dev, "mem_win_addr", mem_win_addr); | |
374 | qdev_prop_set_uint64(dev, "mem_win_size", mem_win_size); | |
375 | qdev_prop_set_uint64(dev, "io_win_addr", io_win_addr); | |
376 | ||
377 | qdev_init_nofail(dev); | |
3384f95c DG |
378 | } |
379 | ||
380 | /* Macros to operate with address in OF binding to PCI */ | |
381 | #define b_x(x, p, l) (((x) & ((1<<(l))-1)) << (p)) | |
382 | #define b_n(x) b_x((x), 31, 1) /* 0 if relocatable */ | |
383 | #define b_p(x) b_x((x), 30, 1) /* 1 if prefetchable */ | |
384 | #define b_t(x) b_x((x), 29, 1) /* 1 if the address is aliased */ | |
385 | #define b_ss(x) b_x((x), 24, 2) /* the space code */ | |
386 | #define b_bbbbbbbb(x) b_x((x), 16, 8) /* bus number */ | |
387 | #define b_ddddd(x) b_x((x), 11, 5) /* device number */ | |
388 | #define b_fff(x) b_x((x), 8, 3) /* function number */ | |
389 | #define b_rrrrrrrr(x) b_x((x), 0, 8) /* register number */ | |
390 | ||
3384f95c DG |
391 | int spapr_populate_pci_devices(sPAPRPHBState *phb, |
392 | uint32_t xics_phandle, | |
393 | void *fdt) | |
394 | { | |
395 | PCIBus *bus = phb->host_state.bus; | |
4d8d5467 | 396 | int bus_off, i; |
3384f95c | 397 | char nodename[256]; |
3384f95c DG |
398 | uint32_t bus_range[] = { cpu_to_be32(0), cpu_to_be32(0xff) }; |
399 | struct { | |
400 | uint32_t hi; | |
401 | uint64_t child; | |
402 | uint64_t parent; | |
403 | uint64_t size; | |
404 | } __attribute__((packed)) ranges[] = { | |
405 | { | |
406 | cpu_to_be32(b_ss(1)), cpu_to_be64(0), | |
407 | cpu_to_be64(phb->io_win_addr), | |
408 | cpu_to_be64(memory_region_size(&phb->iospace)), | |
409 | }, | |
410 | { | |
411 | cpu_to_be32(b_ss(2)), cpu_to_be64(SPAPR_PCI_MEM_WIN_BUS_OFFSET), | |
412 | cpu_to_be64(phb->mem_win_addr), | |
413 | cpu_to_be64(memory_region_size(&phb->memwindow)), | |
414 | }, | |
415 | }; | |
416 | uint64_t bus_reg[] = { cpu_to_be64(phb->buid), 0 }; | |
417 | uint32_t interrupt_map_mask[] = { | |
4d8d5467 | 418 | cpu_to_be32(b_ddddd(-1)|b_fff(0)), 0x0, 0x0, 0x0}; |
3384f95c DG |
419 | uint32_t interrupt_map[bus->nirq][7]; |
420 | ||
421 | /* Start populating the FDT */ | |
422 | sprintf(nodename, "pci@%" PRIx64, phb->buid); | |
423 | bus_off = fdt_add_subnode(fdt, 0, nodename); | |
424 | if (bus_off < 0) { | |
425 | return bus_off; | |
426 | } | |
427 | ||
428 | #define _FDT(exp) \ | |
429 | do { \ | |
430 | int ret = (exp); \ | |
431 | if (ret < 0) { \ | |
432 | return ret; \ | |
433 | } \ | |
434 | } while (0) | |
435 | ||
436 | /* Write PHB properties */ | |
437 | _FDT(fdt_setprop_string(fdt, bus_off, "device_type", "pci")); | |
438 | _FDT(fdt_setprop_string(fdt, bus_off, "compatible", "IBM,Logical_PHB")); | |
439 | _FDT(fdt_setprop_cell(fdt, bus_off, "#address-cells", 0x3)); | |
440 | _FDT(fdt_setprop_cell(fdt, bus_off, "#size-cells", 0x2)); | |
441 | _FDT(fdt_setprop_cell(fdt, bus_off, "#interrupt-cells", 0x1)); | |
442 | _FDT(fdt_setprop(fdt, bus_off, "used-by-rtas", NULL, 0)); | |
443 | _FDT(fdt_setprop(fdt, bus_off, "bus-range", &bus_range, sizeof(bus_range))); | |
444 | _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof(ranges))); | |
445 | _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg))); | |
3f7565c9 | 446 | _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1)); |
3384f95c | 447 | |
4d8d5467 BH |
448 | /* Build the interrupt-map, this must matches what is done |
449 | * in pci_spapr_map_irq | |
450 | */ | |
451 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map-mask", | |
452 | &interrupt_map_mask, sizeof(interrupt_map_mask))); | |
453 | for (i = 0; i < 7; i++) { | |
454 | uint32_t *irqmap = interrupt_map[i]; | |
455 | irqmap[0] = cpu_to_be32(b_ddddd(i)|b_fff(0)); | |
3384f95c DG |
456 | irqmap[1] = 0; |
457 | irqmap[2] = 0; | |
458 | irqmap[3] = 0; | |
459 | irqmap[4] = cpu_to_be32(xics_phandle); | |
4d8d5467 | 460 | irqmap[5] = cpu_to_be32(phb->lsi_table[i % SPAPR_PCI_NUM_LSI].dt_irq); |
3384f95c | 461 | irqmap[6] = cpu_to_be32(0x8); |
3384f95c | 462 | } |
3384f95c DG |
463 | /* Write interrupt map */ |
464 | _FDT(fdt_setprop(fdt, bus_off, "interrupt-map", &interrupt_map, | |
4d8d5467 | 465 | 7 * sizeof(interrupt_map[0]))); |
3384f95c DG |
466 | |
467 | return 0; | |
468 | } | |
298a9710 DG |
469 | |
470 | static void register_types(void) | |
471 | { | |
472 | type_register_static(&spapr_phb_info); | |
473 | } | |
474 | type_init(register_types) |