[mirror_qemu.git] / hw / sparc / leon3.c

/*
 * QEMU Leon3 System Emulator
 *
 * Copyright (c) 2010-2019 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qapi/error.h"
#include "qemu/datadir.h"
#include "cpu.h"
#include "hw/irq.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "sysemu/sysemu.h"
#include "sysemu/qtest.h"
#include "sysemu/reset.h"
#include "hw/boards.h"
#include "hw/loader.h"
#include "elf.h"
#include "trace.h"

#include "hw/sparc/grlib.h"
#include "hw/misc/grlib_ahb_apb_pnp.h"

/* Default system clock.  */
#define CPU_CLK (40 * 1000 * 1000)

#define LEON3_PROM_FILENAME "u-boot.bin"
#define LEON3_PROM_OFFSET    (0x00000000)
#define LEON3_RAM_OFFSET     (0x40000000)

#define LEON3_UART_OFFSET  (0x80000100)
#define LEON3_UART_IRQ     (3)

#define LEON3_IRQMP_OFFSET (0x80000200)

#define LEON3_TIMER_OFFSET (0x80000300)
#define LEON3_TIMER_IRQ    (6)
#define LEON3_TIMER_COUNT  (2)

#define LEON3_APB_PNP_OFFSET (0x800FF000)
#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)

typedef struct ResetData {
    SPARCCPU *cpu;
    uint32_t  entry;            /* save kernel entry in case of reset */
    target_ulong sp;            /* initial stack pointer */
} ResetData;

static uint32_t *gen_store_u32(uint32_t *code, hwaddr addr, uint32_t val)
{
    stl_p(code++, 0x82100000); /* mov %g0, %g1                */
    stl_p(code++, 0x84100000); /* mov %g0, %g2                */
    stl_p(code++, 0x03000000 +
      extract32(addr, 10, 22));
                               /* sethi %hi(addr), %g1        */
    stl_p(code++, 0x82106000 +
      extract32(addr, 0, 10));
                               /* or %g1, addr, %g1           */
    stl_p(code++, 0x05000000 +
      extract32(val, 10, 22));
                               /* sethi %hi(val), %g2         */
    stl_p(code++, 0x8410a000 +
      extract32(val, 0, 10));
                               /* or %g2, val, %g2            */
    stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ]             */

    return code;
}

/*
 * When loading a kernel in RAM the machine is expected to be in a different
 * state (eg: initialized by the bootloader). This little code reproduces
 * this behavior.
 */
static void write_bootloader(CPUSPARCState *env, uint8_t *base,
                             hwaddr kernel_addr)
{
    uint32_t *p = (uint32_t *) base;

    /* Initialize the UARTs                                        */
    /* *UART_CONTROL = UART_RECEIVE_ENABLE | UART_TRANSMIT_ENABLE; */
    p = gen_store_u32(p, 0x80000108, 3);

    /* Initialize the TIMER 0                                      */
    /* *GPTIMER_SCALER_RELOAD = 40 - 1;                            */
    p = gen_store_u32(p, 0x80000304, 39);
    /* *GPTIMER0_COUNTER_RELOAD = 0xFFFE;                          */
    p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
    /* *GPTIMER0_CONFIG = GPTIMER_ENABLE | GPTIMER_RESTART;        */
    p = gen_store_u32(p, 0x80000318, 3);

    /* JUMP to the entry point                                     */
    stl_p(p++, 0x82100000); /* mov %g0, %g1 */
    stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
                            /* sethi %hi(kernel_addr), %g1 */
    stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
                            /* or kernel_addr, %g1 */
    stl_p(p++, 0x81c04000); /* jmp  %g1 */
    stl_p(p++, 0x01000000); /* nop */
}

static void main_cpu_reset(void *opaque)
{
    ResetData *s   = (ResetData *)opaque;
    CPUState *cpu = CPU(s->cpu);
    CPUSPARCState  *env = &s->cpu->env;

    cpu_reset(cpu);

    cpu->halted = 0;
    env->pc     = s->entry;
    env->npc    = s->entry + 4;
    env->regbase[6] = s->sp;
}

static void leon3_cache_control_int(CPUSPARCState *env)
{
    uint32_t state = 0;

    if (env->cache_control & CACHE_CTRL_IF) {
        /* Instruction cache state */
        state = env->cache_control & CACHE_STATE_MASK;
        if (state == CACHE_ENABLED) {
            state = CACHE_FROZEN;
            trace_int_helper_icache_freeze();
        }

        env->cache_control &= ~CACHE_STATE_MASK;
        env->cache_control |= state;
    }

    if (env->cache_control & CACHE_CTRL_DF) {
        /* Data cache state */
        state = (env->cache_control >> 2) & CACHE_STATE_MASK;
        if (state == CACHE_ENABLED) {
            state = CACHE_FROZEN;
            trace_int_helper_dcache_freeze();
        }

        env->cache_control &= ~(CACHE_STATE_MASK << 2);
        env->cache_control |= (state << 2);
    }
}

static void leon3_irq_ack(CPUSPARCState *env, int intno)
{
    grlib_irqmp_ack(env->irq_manager, intno);
}

/*
 * This device assumes that the incoming 'level' value on the
 * qemu_irq is the interrupt number, not just a simple 0/1 level.
 */
static void leon3_set_pil_in(void *opaque, int n, int level)
{
    CPUSPARCState *env = opaque;
    uint32_t pil_in = level;
    CPUState *cs;

    assert(env != NULL);

    env->pil_in = pil_in;

    if (env->pil_in && (env->interrupt_index == 0 ||
                        (env->interrupt_index & ~15) == TT_EXTINT)) {
        unsigned int i;

        for (i = 15; i > 0; i--) {
            if (env->pil_in & (1 << i)) {
                int old_interrupt = env->interrupt_index;

                env->interrupt_index = TT_EXTINT | i;
                if (old_interrupt != env->interrupt_index) {
                    cs = env_cpu(env);
                    trace_leon3_set_irq(i);
                    cpu_interrupt(cs, CPU_INTERRUPT_HARD);
                }
                break;
            }
        }
    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
        cs = env_cpu(env);
        trace_leon3_reset_irq(env->interrupt_index & 15);
        env->interrupt_index = 0;
        cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
    }
}

static void leon3_irq_manager(CPUSPARCState *env, int intno)
{
    leon3_irq_ack(env, intno);
    leon3_cache_control_int(env);
}

static void leon3_generic_hw_init(MachineState *machine)
{
    ram_addr_t ram_size = machine->ram_size;
    const char *bios_name = machine->firmware ?: LEON3_PROM_FILENAME;
    const char *kernel_filename = machine->kernel_filename;
    SPARCCPU *cpu;
    CPUSPARCState   *env;
    MemoryRegion *address_space_mem = get_system_memory();
    MemoryRegion *prom = g_new(MemoryRegion, 1);
    int         ret;
    char       *filename;
    int         bios_size;
    int         prom_size;
    ResetData  *reset_info;
    DeviceState *dev, *irqmpdev;
    int i;
    AHBPnp *ahb_pnp;
    APBPnp *apb_pnp;

    /* Init CPU */
    cpu = SPARC_CPU(cpu_create(machine->cpu_type));
    env = &cpu->env;

    cpu_sparc_set_id(env, 0);

    /* Reset data */
    reset_info        = g_new0(ResetData, 1);
    reset_info->cpu   = cpu;
    reset_info->sp    = LEON3_RAM_OFFSET + ram_size;
    qemu_register_reset(main_cpu_reset, reset_info);

    ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
    sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
    grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
                            GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
                            GRLIB_CPU_AREA);

    apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP));
    sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
    grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
                            GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
                            GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);

    /* Allocate IRQ manager */
    irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
    qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
                                        env, "pil", 1);
    qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0,
                                qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
    sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
    env->irq_manager = irqmpdev;
    env->qemu_irq_ack = leon3_irq_manager;
    grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
                            GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
                            2, 0, GRLIB_APBIO_AREA);

    /* Allocate RAM */
    if (ram_size > 1 * GiB) {
        error_report("Too much memory for this machine: %" PRId64 "MB,"
                     " maximum 1G",
                     ram_size / MiB);
        exit(1);
    }

    memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET,
                                machine->ram);

    /* Allocate BIOS */
    prom_size = 8 * MiB;
    memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
    memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);

    /* Load boot prom */
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);

    if (filename) {
        bios_size = get_image_size(filename);
    } else {
        bios_size = -1;
    }

    if (bios_size > prom_size) {
        error_report("could not load prom '%s': file too big", filename);
        exit(1);
    }

    if (bios_size > 0) {
        ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
        if (ret < 0 || ret > prom_size) {
            error_report("could not load prom '%s'", filename);
            exit(1);
        }
    } else if (kernel_filename == NULL && !qtest_enabled()) {
        error_report("Can't read bios image '%s'", filename
                                                   ? filename
                                                   : LEON3_PROM_FILENAME);
        exit(1);
    }
    g_free(filename);

    /* Can directly load an application. */
    if (kernel_filename != NULL) {
        long     kernel_size;
        uint64_t entry;

        kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
                               &entry, NULL, NULL, NULL,
                               1 /* big endian */, EM_SPARC, 0, 0);
        if (kernel_size < 0) {
            kernel_size = load_uimage(kernel_filename, NULL, &entry,
                                      NULL, NULL, NULL);
        }
        if (kernel_size < 0) {
            error_report("could not load kernel '%s'", kernel_filename);
            exit(1);
        }
        if (bios_size <= 0) {
            /*
             * If there is no bios/monitor just start the application but put
             * the machine in an initialized state through a little
             * bootloader.
             */
            uint8_t *bootloader_entry;

            bootloader_entry = memory_region_get_ram_ptr(prom);
            write_bootloader(env, bootloader_entry, entry);
            env->pc = LEON3_PROM_OFFSET;
            env->npc = LEON3_PROM_OFFSET + 4;
            reset_info->entry = LEON3_PROM_OFFSET;
        }
    }

    /* Allocate timers */
    dev = qdev_new(TYPE_GRLIB_GPTIMER);
    qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
    qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
    qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);

    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
    for (i = 0; i < LEON3_TIMER_COUNT; i++) {
        sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
                           qdev_get_gpio_in(irqmpdev, LEON3_TIMER_IRQ + i));
    }

    grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
                            GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
                            0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);

    /* Allocate uart */
    dev = qdev_new(TYPE_GRLIB_APB_UART);
    qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
    sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
    sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
    sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
                       qdev_get_gpio_in(irqmpdev, LEON3_UART_IRQ));
    grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
                            GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
                            LEON3_UART_IRQ, GRLIB_APBIO_AREA);
}

static void leon3_generic_machine_init(MachineClass *mc)
{
    mc->desc = "Leon-3 generic";
    mc->init = leon3_generic_hw_init;
    mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
    mc->default_ram_id = "leon3.ram";
}

DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)
Commit	Line	Data
b04d9890 FC	1	/*
	2	* QEMU Leon3 System Emulator
	3	*
bd30132c	4	* Copyright (c) 2010-2019 AdaCore
b04d9890 FC	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
71e8a915	24
db5ebe5f	25	#include "qemu/osdep.h"
0a2e467b	26	#include "qemu/units.h"
29bd7231	27	#include "qemu/error-report.h"
da34e65c	28	#include "qapi/error.h"
2c65db5e	29	#include "qemu/datadir.h"
4771d756	30	#include "cpu.h"
64552b6b	31	#include "hw/irq.h"
1de7afc9	32	#include "qemu/timer.h"
83c9f4ca	33	#include "hw/ptimer.h"
a27bd6c7	34	#include "hw/qdev-properties.h"
9c17d615	35	#include "sysemu/sysemu.h"
77612541	36	#include "sysemu/qtest.h"
71e8a915	37	#include "sysemu/reset.h"
83c9f4ca PB	38	#include "hw/boards.h"
83c9f4ca PB	39	#include "hw/loader.h"
b04d9890 FC	40	#include "elf.h"
	41	#include "trace.h"
	42
0d09e41a	43	#include "hw/sparc/grlib.h"
162abf1a	44	#include "hw/misc/grlib_ahb_apb_pnp.h"
b04d9890 FC	45
	46	/* Default system clock. */
	47	#define CPU_CLK (40 * 1000 * 1000)
	48
bd30132c	49	#define LEON3_PROM_FILENAME "u-boot.bin"
dbed0d2d KF	50	#define LEON3_PROM_OFFSET (0x00000000)
dbed0d2d KF	51	#define LEON3_RAM_OFFSET (0x40000000)
b04d9890	52
b70447aa KF	53	#define LEON3_UART_OFFSET (0x80000100)
	54	#define LEON3_UART_IRQ (3)
	55
ea005dae KF	56	#define LEON3_IRQMP_OFFSET (0x80000200)
ea005dae KF	57
948caec8 KF	58	#define LEON3_TIMER_OFFSET (0x80000300)
	59	#define LEON3_TIMER_IRQ (6)
	60	#define LEON3_TIMER_COUNT (2)
	61
162abf1a KF	62	#define LEON3_APB_PNP_OFFSET (0x800FF000)
	63	#define LEON3_AHB_PNP_OFFSET (0xFFFFF000)
	64
b04d9890	65	typedef struct ResetData {
c537d79c	66	SPARCCPU *cpu;
b04d9890	67	uint32_t entry; /* save kernel entry in case of reset */
c1570e2a	68	target_ulong sp; /* initial stack pointer */
b04d9890 FC	69	} ResetData;
b04d9890 FC	70
dbed0d2d KF	71	static uint32_t gen_store_u32(uint32_t code, hwaddr addr, uint32_t val)
	72	{
	73	stl_p(code++, 0x82100000); /* mov %g0, %g1 */
	74	stl_p(code++, 0x84100000); /* mov %g0, %g2 */
	75	stl_p(code++, 0x03000000 +
	76	extract32(addr, 10, 22));
	77	/* sethi %hi(addr), %g1 */
	78	stl_p(code++, 0x82106000 +
	79	extract32(addr, 0, 10));
	80	/* or %g1, addr, %g1 */
	81	stl_p(code++, 0x05000000 +
	82	extract32(val, 10, 22));
	83	/* sethi %hi(val), %g2 */
	84	stl_p(code++, 0x8410a000 +
	85	extract32(val, 0, 10));
	86	/* or %g2, val, %g2 */
	87	stl_p(code++, 0xc4204000); /* st %g2, [ %g1 ] */
	88
	89	return code;
	90	}
	91
	92	/*
	93	* When loading a kernel in RAM the machine is expected to be in a different
	94	* state (eg: initialized by the bootloader). This little code reproduces
	95	* this behavior.
	96	*/
	97	static void write_bootloader(CPUSPARCState env, uint8_t base,
	98	hwaddr kernel_addr)
	99	{
	100	uint32_t p = (uint32_t ) base;
	101
	102	/* Initialize the UARTs */
	103	/* UART_CONTROL = UART_RECEIVE_ENABLE \| UART_TRANSMIT_ENABLE; /
	104	p = gen_store_u32(p, 0x80000108, 3);
	105
	106	/* Initialize the TIMER 0 */
	107	/* GPTIMER_SCALER_RELOAD = 40 - 1; /
	108	p = gen_store_u32(p, 0x80000304, 39);
	109	/* GPTIMER0_COUNTER_RELOAD = 0xFFFE; /
	110	p = gen_store_u32(p, 0x80000314, 0xFFFFFFFE);
	111	/* GPTIMER0_CONFIG = GPTIMER_ENABLE \| GPTIMER_RESTART; /
	112	p = gen_store_u32(p, 0x80000318, 3);
	113
	114	/* JUMP to the entry point */
	115	stl_p(p++, 0x82100000); /* mov %g0, %g1 */
	116	stl_p(p++, 0x03000000 + extract32(kernel_addr, 10, 22));
	117	/* sethi %hi(kernel_addr), %g1 */
	118	stl_p(p++, 0x82106000 + extract32(kernel_addr, 0, 10));
	119	/* or kernel_addr, %g1 */
	120	stl_p(p++, 0x81c04000); /* jmp %g1 */
	121	stl_p(p++, 0x01000000); /* nop */
	122	}
	123
b04d9890 FC	124	static void main_cpu_reset(void *opaque)
	125	{
	126	ResetData s = (ResetData )opaque;
259186a7	127	CPUState *cpu = CPU(s->cpu);
c537d79c	128	CPUSPARCState *env = &s->cpu->env;
b04d9890	129
259186a7	130	cpu_reset(cpu);
b04d9890	131
259186a7	132	cpu->halted = 0;
b04d9890 FC	133	env->pc = s->entry;
b04d9890 FC	134	env->npc = s->entry + 4;
c1570e2a	135	env->regbase[6] = s->sp;
b04d9890 FC	136	}
b04d9890 FC	137
12841199 PMD	138	static void leon3_cache_control_int(CPUSPARCState *env)
	139	{
	140	uint32_t state = 0;
	141
	142	if (env->cache_control & CACHE_CTRL_IF) {
	143	/* Instruction cache state */
	144	state = env->cache_control & CACHE_STATE_MASK;
	145	if (state == CACHE_ENABLED) {
	146	state = CACHE_FROZEN;
	147	trace_int_helper_icache_freeze();
	148	}
	149
	150	env->cache_control &= ~CACHE_STATE_MASK;
	151	env->cache_control \|= state;
	152	}
	153
	154	if (env->cache_control & CACHE_CTRL_DF) {
	155	/* Data cache state */
	156	state = (env->cache_control >> 2) & CACHE_STATE_MASK;
	157	if (state == CACHE_ENABLED) {
	158	state = CACHE_FROZEN;
	159	trace_int_helper_dcache_freeze();
	160	}
	161
	162	env->cache_control &= ~(CACHE_STATE_MASK << 2);
	163	env->cache_control \|= (state << 2);
	164	}
	165	}
	166
a318da6b	167	static void leon3_irq_ack(CPUSPARCState *env, int intno)
b04d9890	168	{
a318da6b	169	grlib_irqmp_ack(env->irq_manager, intno);
b04d9890 FC	170	}
b04d9890 FC	171
ab4c072d MAL	172	/*
	173	* This device assumes that the incoming 'level' value on the
	174	* qemu_irq is the interrupt number, not just a simple 0/1 level.
	175	*/
	176	static void leon3_set_pil_in(void *opaque, int n, int level)
b04d9890	177	{
ab4c072d MAL	178	CPUSPARCState *env = opaque;
ab4c072d MAL	179	uint32_t pil_in = level;
d8ed887b	180	CPUState *cs;
b04d9890 FC	181
	182	assert(env != NULL);
	183
	184	env->pil_in = pil_in;
	185
	186	if (env->pil_in && (env->interrupt_index == 0 \|\|
	187	(env->interrupt_index & ~15) == TT_EXTINT)) {
	188	unsigned int i;
	189
	190	for (i = 15; i > 0; i--) {
	191	if (env->pil_in & (1 << i)) {
	192	int old_interrupt = env->interrupt_index;
	193
	194	env->interrupt_index = TT_EXTINT \| i;
	195	if (old_interrupt != env->interrupt_index) {
5a59fbce	196	cs = env_cpu(env);
b04d9890	197	trace_leon3_set_irq(i);
c3affe56	198	cpu_interrupt(cs, CPU_INTERRUPT_HARD);
b04d9890 FC	199	}
	200	break;
	201	}
	202	}
	203	} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
5a59fbce	204	cs = env_cpu(env);
b04d9890 FC	205	trace_leon3_reset_irq(env->interrupt_index & 15);
b04d9890 FC	206	env->interrupt_index = 0;
d8ed887b	207	cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
b04d9890 FC	208	}
	209	}
	210
a318da6b	211	static void leon3_irq_manager(CPUSPARCState *env, int intno)
12841199	212	{
a318da6b	213	leon3_irq_ack(env, intno);
12841199 PMD	214	leon3_cache_control_int(env);
	215	}
	216
3ef96221	217	static void leon3_generic_hw_init(MachineState *machine)
b04d9890	218	{
3ef96221	219	ram_addr_t ram_size = machine->ram_size;
377ce9cb	220	const char *bios_name = machine->firmware ?: LEON3_PROM_FILENAME;
3ef96221	221	const char *kernel_filename = machine->kernel_filename;
60ad0733	222	SPARCCPU *cpu;
98cec4a2	223	CPUSPARCState *env;
a4911d64	224	MemoryRegion *address_space_mem = get_system_memory();
a4911d64	225	MemoryRegion *prom = g_new(MemoryRegion, 1);
b04d9890 FC	226	int ret;
b04d9890 FC	227	char *filename;
b04d9890 FC	228	int bios_size;
	229	int prom_size;
	230	ResetData *reset_info;
33919536	231	DeviceState dev, irqmpdev;
948caec8	232	int i;
162abf1a KF	233	AHBPnp *ahb_pnp;
162abf1a KF	234	APBPnp *apb_pnp;
b04d9890 FC	235
b04d9890 FC	236	/* Init CPU */
e9135ab3	237	cpu = SPARC_CPU(cpu_create(machine->cpu_type));
60ad0733	238	env = &cpu->env;
b04d9890 FC	239
	240	cpu_sparc_set_id(env, 0);
	241
	242	/* Reset data */
b21e2380	243	reset_info = g_new0(ResetData, 1);
c537d79c	244	reset_info->cpu = cpu;
dbed0d2d	245	reset_info->sp = LEON3_RAM_OFFSET + ram_size;
b04d9890 FC	246	qemu_register_reset(main_cpu_reset, reset_info);
b04d9890 FC	247
df707969	248	ahb_pnp = GRLIB_AHB_PNP(qdev_new(TYPE_GRLIB_AHB_PNP));
3c6ef471	249	sysbus_realize_and_unref(SYS_BUS_DEVICE(ahb_pnp), &error_fatal);
162abf1a KF	250	sysbus_mmio_map(SYS_BUS_DEVICE(ahb_pnp), 0, LEON3_AHB_PNP_OFFSET);
	251	grlib_ahb_pnp_add_entry(ahb_pnp, 0, 0, GRLIB_VENDOR_GAISLER,
	252	GRLIB_LEON3_DEV, GRLIB_AHB_MASTER,
	253	GRLIB_CPU_AREA);
	254
df707969	255	apb_pnp = GRLIB_APB_PNP(qdev_new(TYPE_GRLIB_APB_PNP));
3c6ef471	256	sysbus_realize_and_unref(SYS_BUS_DEVICE(apb_pnp), &error_fatal);
162abf1a KF	257	sysbus_mmio_map(SYS_BUS_DEVICE(apb_pnp), 0, LEON3_APB_PNP_OFFSET);
	258	grlib_ahb_pnp_add_entry(ahb_pnp, LEON3_APB_PNP_OFFSET, 0xFFF,
	259	GRLIB_VENDOR_GAISLER, GRLIB_APBMST_DEV,
	260	GRLIB_AHB_SLAVE, GRLIB_AHBMEM_AREA);
	261
b04d9890	262	/* Allocate IRQ manager */
33919536	263	irqmpdev = qdev_new(TYPE_GRLIB_IRQMP);
e23ae617 MAL	264	qdev_init_gpio_in_named_with_opaque(DEVICE(cpu), leon3_set_pil_in,
e23ae617 MAL	265	env, "pil", 1);
33919536	266	qdev_connect_gpio_out_named(irqmpdev, "grlib-irq", 0,
e23ae617	267	qdev_get_gpio_in_named(DEVICE(cpu), "pil", 0));
33919536 PM	268	sysbus_realize_and_unref(SYS_BUS_DEVICE(irqmpdev), &error_fatal);
	269	sysbus_mmio_map(SYS_BUS_DEVICE(irqmpdev), 0, LEON3_IRQMP_OFFSET);
	270	env->irq_manager = irqmpdev;
60f356e8	271	env->qemu_irq_ack = leon3_irq_manager;
162abf1a KF	272	grlib_apb_pnp_add_entry(apb_pnp, LEON3_IRQMP_OFFSET, 0xFFF,
	273	GRLIB_VENDOR_GAISLER, GRLIB_IRQMP_DEV,
	274	2, 0, GRLIB_APBIO_AREA);
b04d9890 FC	275
b04d9890 FC	276	/* Allocate RAM */
0a2e467b PMD	277	if (ram_size > 1 * GiB) {
	278	error_report("Too much memory for this machine: %" PRId64 "MB,"
	279	" maximum 1G",
	280	ram_size / MiB);
b04d9890 FC	281	exit(1);
	282	}
	283
fe3e7b71 IM	284	memory_region_add_subregion(address_space_mem, LEON3_RAM_OFFSET,
fe3e7b71 IM	285	machine->ram);
b04d9890 FC	286
b04d9890 FC	287	/* Allocate BIOS */
0a2e467b	288	prom_size = 8 * MiB;
ec7b2175	289	memory_region_init_rom(prom, NULL, "Leon3.bios", prom_size, &error_fatal);
dbed0d2d	290	memory_region_add_subregion(address_space_mem, LEON3_PROM_OFFSET, prom);
b04d9890 FC	291
b04d9890 FC	292	/* Load boot prom */
b04d9890 FC	293	filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
b04d9890 FC	294
47dc0ec5 PM	295	if (filename) {
	296	bios_size = get_image_size(filename);
	297	} else {
	298	bios_size = -1;
	299	}
b04d9890 FC	300
b04d9890 FC	301	if (bios_size > prom_size) {
29bd7231	302	error_report("could not load prom '%s': file too big", filename);
b04d9890 FC	303	exit(1);
	304	}
	305
	306	if (bios_size > 0) {
dbed0d2d	307	ret = load_image_targphys(filename, LEON3_PROM_OFFSET, bios_size);
b04d9890	308	if (ret < 0 \|\| ret > prom_size) {
29bd7231	309	error_report("could not load prom '%s'", filename);
b04d9890 FC	310	exit(1);
b04d9890 FC	311	}
77612541	312	} else if (kernel_filename == NULL && !qtest_enabled()) {
bd30132c KF	313	error_report("Can't read bios image '%s'", filename
	314	? filename
	315	: LEON3_PROM_FILENAME);
b04d9890 FC	316	exit(1);
b04d9890 FC	317	}
d71cdbfd	318	g_free(filename);
b04d9890 FC	319
	320	/* Can directly load an application. */
	321	if (kernel_filename != NULL) {
	322	long kernel_size;
	323	uint64_t entry;
	324
4366e1db	325	kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
6cdda0ff	326	&entry, NULL, NULL, NULL,
7ef295ea	327	1 /* big endian */, EM_SPARC, 0, 0);
9176a580 PMD	328	if (kernel_size < 0) {
	329	kernel_size = load_uimage(kernel_filename, NULL, &entry,
	330	NULL, NULL, NULL);
	331	}
b04d9890	332	if (kernel_size < 0) {
29bd7231	333	error_report("could not load kernel '%s'", kernel_filename);
b04d9890 FC	334	exit(1);
	335	}
	336	if (bios_size <= 0) {
dbed0d2d KF	337	/*
	338	* If there is no bios/monitor just start the application but put
	339	* the machine in an initialized state through a little
	340	* bootloader.
	341	*/
	342	uint8_t *bootloader_entry;
	343
	344	bootloader_entry = memory_region_get_ram_ptr(prom);
	345	write_bootloader(env, bootloader_entry, entry);
	346	env->pc = LEON3_PROM_OFFSET;
	347	env->npc = LEON3_PROM_OFFSET + 4;
	348	reset_info->entry = LEON3_PROM_OFFSET;
b04d9890 FC	349	}
	350	}
	351
	352	/* Allocate timers */
3e80f690	353	dev = qdev_new(TYPE_GRLIB_GPTIMER);
948caec8 KF	354	qdev_prop_set_uint32(dev, "nr-timers", LEON3_TIMER_COUNT);
	355	qdev_prop_set_uint32(dev, "frequency", CPU_CLK);
	356	qdev_prop_set_uint32(dev, "irq-line", LEON3_TIMER_IRQ);
3c6ef471	357	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
948caec8 KF	358
	359	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_TIMER_OFFSET);
	360	for (i = 0; i < LEON3_TIMER_COUNT; i++) {
	361	sysbus_connect_irq(SYS_BUS_DEVICE(dev), i,
33919536	362	qdev_get_gpio_in(irqmpdev, LEON3_TIMER_IRQ + i));
948caec8	363	}
b04d9890	364
162abf1a KF	365	grlib_apb_pnp_add_entry(apb_pnp, LEON3_TIMER_OFFSET, 0xFFF,
	366	GRLIB_VENDOR_GAISLER, GRLIB_GPTIMER_DEV,
	367	0, LEON3_TIMER_IRQ, GRLIB_APBIO_AREA);
	368
b04d9890	369	/* Allocate uart */
3e80f690	370	dev = qdev_new(TYPE_GRLIB_APB_UART);
acd2a001	371	qdev_prop_set_chr(dev, "chrdev", serial_hd(0));
3c6ef471	372	sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
acd2a001	373	sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, LEON3_UART_OFFSET);
33919536 PM	374	sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
33919536 PM	375	qdev_get_gpio_in(irqmpdev, LEON3_UART_IRQ));
acd2a001 PMD	376	grlib_apb_pnp_add_entry(apb_pnp, LEON3_UART_OFFSET, 0xFFF,
	377	GRLIB_VENDOR_GAISLER, GRLIB_APBUART_DEV, 1,
	378	LEON3_UART_IRQ, GRLIB_APBIO_AREA);
b04d9890 FC	379	}
b04d9890 FC	380
e264d29d	381	static void leon3_generic_machine_init(MachineClass *mc)
b04d9890	382	{
e264d29d EH	383	mc->desc = "Leon-3 generic";
e264d29d EH	384	mc->init = leon3_generic_hw_init;
e9135ab3	385	mc->default_cpu_type = SPARC_CPU_TYPE_NAME("LEON3");
fe3e7b71	386	mc->default_ram_id = "leon3.ram";
b04d9890 FC	387	}
b04d9890 FC	388
e264d29d	389	DEFINE_MACHINE("leon3_generic", leon3_generic_machine_init)