]>
Commit | Line | Data |
---|---|---|
420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
71e8a915 | 24 | |
db5ebe5f | 25 | #include "qemu/osdep.h" |
0a2e467b | 26 | #include "qemu/units.h" |
da34e65c | 27 | #include "qapi/error.h" |
2c65db5e | 28 | #include "qemu/datadir.h" |
4771d756 | 29 | #include "cpu.h" |
83c9f4ca | 30 | #include "hw/sysbus.h" |
af87bf29 | 31 | #include "qemu/error-report.h" |
1de7afc9 | 32 | #include "qemu/timer.h" |
1527f488 | 33 | #include "hw/sparc/sun4m_iommu.h" |
819ce6b2 | 34 | #include "hw/rtc/m48t59.h" |
d6454270 | 35 | #include "migration/vmstate.h" |
0d09e41a PB |
36 | #include "hw/sparc/sparc32_dma.h" |
37 | #include "hw/block/fdc.h" | |
71e8a915 | 38 | #include "sysemu/reset.h" |
54d31236 | 39 | #include "sysemu/runstate.h" |
9c17d615 | 40 | #include "sysemu/sysemu.h" |
1422e32d | 41 | #include "net/net.h" |
83c9f4ca | 42 | #include "hw/boards.h" |
0d09e41a | 43 | #include "hw/scsi/esp.h" |
c6363bae | 44 | #include "hw/nvram/sun_nvram.h" |
a27bd6c7 | 45 | #include "hw/qdev-properties.h" |
2024c014 | 46 | #include "hw/nvram/chrp_nvram.h" |
0d09e41a PB |
47 | #include "hw/nvram/fw_cfg.h" |
48 | #include "hw/char/escc.h" | |
6007523a | 49 | #include "hw/misc/empty_slot.h" |
077f0f3d | 50 | #include "hw/misc/unimp.h" |
64552b6b | 51 | #include "hw/irq.h" |
a879306c | 52 | #include "hw/or-irq.h" |
83c9f4ca | 53 | #include "hw/loader.h" |
ca20cf32 | 54 | #include "elf.h" |
97bf4851 | 55 | #include "trace.h" |
db1015e9 | 56 | #include "qom/object.h" |
420557e8 | 57 | |
36cd9210 BS |
58 | /* |
59 | * Sun4m architecture was used in the following machines: | |
60 | * | |
61 | * SPARCserver 6xxMP/xx | |
77f193da BS |
62 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
63 | * SPARCclassic X (4/10) | |
36cd9210 BS |
64 | * SPARCstation LX/ZX (4/30) |
65 | * SPARCstation Voyager | |
66 | * SPARCstation 10/xx, SPARCserver 10/xx | |
67 | * SPARCstation 5, SPARCserver 5 | |
68 | * SPARCstation 20/xx, SPARCserver 20 | |
69 | * SPARCstation 4 | |
70 | * | |
71 | * See for example: http://www.sunhelp.org/faq/sunref1.html | |
72 | */ | |
73 | ||
420557e8 | 74 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 75 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 76 | #define INITRD_LOAD_ADDR 0x00800000 |
0a2e467b | 77 | #define PROM_SIZE_MAX (1 * MiB) |
40ce0a9a | 78 | #define PROM_VADDR 0xffd00000 |
f930d07e | 79 | #define PROM_FILENAME "openbios-sparc32" |
3cce6243 | 80 | #define CFG_ADDR 0xd00000510ULL |
fbfcf955 | 81 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
b96919e0 MCA |
82 | #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) |
83 | #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) | |
b8174937 | 84 | |
ba3c64fb | 85 | #define MAX_CPUS 16 |
b3a23197 | 86 | #define MAX_PILS 16 |
9a62fb24 | 87 | #define MAX_VSIMMS 4 |
420557e8 | 88 | |
b4ed08e0 BS |
89 | #define ESCC_CLOCK 4915200 |
90 | ||
8137cde8 | 91 | struct sun4m_hwdef { |
a8170e5e AK |
92 | hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
93 | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; | |
94 | hwaddr serial_base, fd_base; | |
95 | hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; | |
96 | hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; | |
97 | hwaddr bpp_base, dbri_base, sx_base; | |
9a62fb24 | 98 | struct { |
a8170e5e | 99 | hwaddr reg_base, vram_base; |
9a62fb24 | 100 | } vsimm[MAX_VSIMMS]; |
a8170e5e | 101 | hwaddr ecc_base; |
3ebf5aaf | 102 | uint64_t max_mem; |
61999750 BS |
103 | uint32_t ecc_version; |
104 | uint32_t iommu_version; | |
105 | uint16_t machine_id; | |
106 | uint8_t nvram_machine_id; | |
36cd9210 BS |
107 | }; |
108 | ||
95bc47de PMD |
109 | struct Sun4mMachineClass { |
110 | /*< private >*/ | |
111 | MachineClass parent_obj; | |
112 | /*< public >*/ | |
113 | const struct sun4m_hwdef *hwdef; | |
114 | }; | |
115 | typedef struct Sun4mMachineClass Sun4mMachineClass; | |
116 | ||
828d01b7 | 117 | #define TYPE_SUN4M_MACHINE MACHINE_TYPE_NAME("sun4m-common") |
95bc47de | 118 | DECLARE_CLASS_CHECKERS(Sun4mMachineClass, SUN4M_MACHINE, TYPE_SUN4M_MACHINE) |
828d01b7 | 119 | |
d5a42d19 PMD |
120 | const char *fw_cfg_arch_key_name(uint16_t key) |
121 | { | |
122 | static const struct { | |
123 | uint16_t key; | |
124 | const char *name; | |
125 | } fw_cfg_arch_wellknown_keys[] = { | |
126 | {FW_CFG_SUN4M_DEPTH, "depth"}, | |
127 | {FW_CFG_SUN4M_WIDTH, "width"}, | |
128 | {FW_CFG_SUN4M_HEIGHT, "height"}, | |
129 | }; | |
130 | ||
131 | for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) { | |
132 | if (fw_cfg_arch_wellknown_keys[i].key == key) { | |
133 | return fw_cfg_arch_wellknown_keys[i].name; | |
134 | } | |
135 | } | |
136 | return NULL; | |
137 | } | |
138 | ||
ddcd5531 GA |
139 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
140 | Error **errp) | |
81864572 | 141 | { |
48779e50 | 142 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
143 | } |
144 | ||
31688246 | 145 | static void nvram_init(Nvram *nvram, uint8_t *macaddr, |
43a34704 BS |
146 | const char *cmdline, const char *boot_devices, |
147 | ram_addr_t RAM_size, uint32_t kernel_size, | |
f930d07e | 148 | int width, int height, int depth, |
905fdcb5 | 149 | int nvram_machine_id, const char *arch) |
e80cfcfc | 150 | { |
d2c63fc1 | 151 | unsigned int i; |
2024c014 | 152 | int sysp_end; |
d2c63fc1 | 153 | uint8_t image[0x1ff0]; |
31688246 | 154 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
155 | |
156 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 157 | |
2024c014 | 158 | /* OpenBIOS nvram variables partition */ |
37035df5 | 159 | sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0); |
b6f479d3 | 160 | |
2024c014 TH |
161 | /* Free space partition */ |
162 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 163 | |
905fdcb5 BS |
164 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
165 | nvram_machine_id); | |
d2c63fc1 | 166 | |
31688246 HP |
167 | for (i = 0; i < sizeof(image); i++) { |
168 | (k->write)(nvram, i, image[i]); | |
169 | } | |
e80cfcfc FB |
170 | } |
171 | ||
38c66cf2 | 172 | static void cpu_kick_irq(SPARCCPU *cpu) |
94ad5b00 | 173 | { |
38c66cf2 | 174 | CPUSPARCState *env = &cpu->env; |
259186a7 | 175 | CPUState *cs = CPU(cpu); |
38c66cf2 | 176 | |
259186a7 | 177 | cs->halted = 0; |
94ad5b00 | 178 | cpu_check_irqs(env); |
259186a7 | 179 | qemu_cpu_kick(cs); |
94ad5b00 PB |
180 | } |
181 | ||
b3a23197 BS |
182 | static void cpu_set_irq(void *opaque, int irq, int level) |
183 | { | |
e0bbf9b5 AF |
184 | SPARCCPU *cpu = opaque; |
185 | CPUSPARCState *env = &cpu->env; | |
b3a23197 BS |
186 | |
187 | if (level) { | |
97bf4851 | 188 | trace_sun4m_cpu_set_irq_raise(irq); |
327ac2e7 | 189 | env->pil_in |= 1 << irq; |
38c66cf2 | 190 | cpu_kick_irq(cpu); |
b3a23197 | 191 | } else { |
97bf4851 | 192 | trace_sun4m_cpu_set_irq_lower(irq); |
327ac2e7 BS |
193 | env->pil_in &= ~(1 << irq); |
194 | cpu_check_irqs(env); | |
b3a23197 BS |
195 | } |
196 | } | |
197 | ||
198 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
199 | { | |
200 | } | |
201 | ||
24f675cd | 202 | static void sun4m_cpu_reset(void *opaque) |
c68ea704 | 203 | { |
5414dec6 | 204 | SPARCCPU *cpu = opaque; |
259186a7 | 205 | CPUState *cs = CPU(cpu); |
3d29fbef | 206 | |
259186a7 | 207 | cpu_reset(cs); |
3d29fbef BS |
208 | } |
209 | ||
6d0c293d BS |
210 | static void cpu_halt_signal(void *opaque, int irq, int level) |
211 | { | |
4917cf44 AF |
212 | if (level && current_cpu) { |
213 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); | |
c3affe56 | 214 | } |
6d0c293d BS |
215 | } |
216 | ||
409dbce5 AJ |
217 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
218 | { | |
219 | return addr - 0xf0000000ULL; | |
220 | } | |
221 | ||
3ebf5aaf | 222 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
293f78bc | 223 | const char *initrd_filename, |
6031ff8b MCA |
224 | ram_addr_t RAM_size, |
225 | uint32_t *initrd_size) | |
3ebf5aaf BS |
226 | { |
227 | int linux_boot; | |
228 | unsigned int i; | |
6031ff8b | 229 | long kernel_size; |
3c178e72 | 230 | uint8_t *ptr; |
3ebf5aaf BS |
231 | |
232 | linux_boot = (kernel_filename != NULL); | |
233 | ||
234 | kernel_size = 0; | |
235 | if (linux_boot) { | |
ca20cf32 BS |
236 | int bswap_needed; |
237 | ||
238 | #ifdef BSWAP_NEEDED | |
239 | bswap_needed = 1; | |
240 | #else | |
241 | bswap_needed = 0; | |
242 | #endif | |
4366e1db LM |
243 | kernel_size = load_elf(kernel_filename, NULL, |
244 | translate_kernel_address, NULL, | |
6cdda0ff | 245 | NULL, NULL, NULL, NULL, 1, EM_SPARC, 0, 0); |
3ebf5aaf | 246 | if (kernel_size < 0) |
293f78bc | 247 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
248 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
249 | TARGET_PAGE_SIZE); | |
3ebf5aaf | 250 | if (kernel_size < 0) |
293f78bc BS |
251 | kernel_size = load_image_targphys(kernel_filename, |
252 | KERNEL_LOAD_ADDR, | |
253 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf | 254 | if (kernel_size < 0) { |
29bd7231 | 255 | error_report("could not load kernel '%s'", kernel_filename); |
3ebf5aaf BS |
256 | exit(1); |
257 | } | |
258 | ||
259 | /* load initrd */ | |
6031ff8b | 260 | *initrd_size = 0; |
3ebf5aaf | 261 | if (initrd_filename) { |
6031ff8b MCA |
262 | *initrd_size = load_image_targphys(initrd_filename, |
263 | INITRD_LOAD_ADDR, | |
264 | RAM_size - INITRD_LOAD_ADDR); | |
265 | if ((int)*initrd_size < 0) { | |
29bd7231 AF |
266 | error_report("could not load initial ram disk '%s'", |
267 | initrd_filename); | |
3ebf5aaf BS |
268 | exit(1); |
269 | } | |
270 | } | |
6031ff8b | 271 | if (*initrd_size > 0) { |
3ebf5aaf | 272 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { |
0f0f8b61 TH |
273 | ptr = rom_ptr(KERNEL_LOAD_ADDR + i, 24); |
274 | if (ptr && ldl_p(ptr) == 0x48647253) { /* HdrS */ | |
3c178e72 | 275 | stl_p(ptr + 16, INITRD_LOAD_ADDR); |
6031ff8b | 276 | stl_p(ptr + 20, *initrd_size); |
3ebf5aaf BS |
277 | break; |
278 | } | |
279 | } | |
280 | } | |
281 | } | |
282 | return kernel_size; | |
283 | } | |
284 | ||
a8170e5e | 285 | static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
4b48bf05 BS |
286 | { |
287 | DeviceState *dev; | |
288 | SysBusDevice *s; | |
289 | ||
3e80f690 | 290 | dev = qdev_new(TYPE_SUN4M_IOMMU); |
4b48bf05 | 291 | qdev_prop_set_uint32(dev, "version", version); |
1356b98d | 292 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 293 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
294 | sysbus_connect_irq(s, 0, irq); |
295 | sysbus_mmio_map(s, 0, addr); | |
296 | ||
297 | return s; | |
298 | } | |
299 | ||
6aa62ed6 MCA |
300 | static void *sparc32_dma_init(hwaddr dma_base, |
301 | hwaddr esp_base, qemu_irq espdma_irq, | |
ae0b175b DW |
302 | hwaddr le_base, qemu_irq ledma_irq, |
303 | MACAddr *mac) | |
74ff8d90 | 304 | { |
6aa62ed6 MCA |
305 | DeviceState *dma; |
306 | ESPDMADeviceState *espdma; | |
307 | LEDMADeviceState *ledma; | |
308 | SysBusESPState *esp; | |
309 | SysBusPCNetState *lance; | |
ae0b175b | 310 | NICInfo *nd = qemu_find_nic_info("lance", true, NULL); |
74ff8d90 | 311 | |
3e80f690 | 312 | dma = qdev_new(TYPE_SPARC32_DMA); |
6aa62ed6 MCA |
313 | espdma = SPARC32_ESPDMA_DEVICE(object_resolve_path_component( |
314 | OBJECT(dma), "espdma")); | |
6aa62ed6 | 315 | |
84fbefed | 316 | esp = SYSBUS_ESP(object_resolve_path_component(OBJECT(espdma), "esp")); |
6aa62ed6 MCA |
317 | |
318 | ledma = SPARC32_LEDMA_DEVICE(object_resolve_path_component( | |
319 | OBJECT(dma), "ledma")); | |
6aa62ed6 MCA |
320 | |
321 | lance = SYSBUS_PCNET(object_resolve_path_component( | |
322 | OBJECT(ledma), "lance")); | |
ae0b175b DW |
323 | |
324 | if (nd) { | |
325 | qdev_set_nic_properties(DEVICE(lance), nd); | |
326 | memcpy(mac->a, nd->macaddr.a, sizeof(mac->a)); | |
327 | } else { | |
328 | qemu_macaddr_default_if_unset(mac); | |
329 | qdev_prop_set_macaddr(DEVICE(lance), "mac", mac->a); | |
330 | } | |
c4210bc1 MCA |
331 | |
332 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); | |
73a143b3 PMD |
333 | |
334 | sysbus_connect_irq(SYS_BUS_DEVICE(espdma), 0, espdma_irq); | |
335 | ||
336 | sysbus_connect_irq(SYS_BUS_DEVICE(ledma), 0, ledma_irq); | |
337 | ||
c4210bc1 MCA |
338 | sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, dma_base); |
339 | ||
340 | sysbus_mmio_map(SYS_BUS_DEVICE(esp), 0, esp_base); | |
341 | scsi_bus_legacy_handle_cmdline(&esp->esp.bus); | |
342 | ||
6aa62ed6 MCA |
343 | sysbus_mmio_map(SYS_BUS_DEVICE(lance), 0, le_base); |
344 | ||
345 | return dma; | |
74ff8d90 BS |
346 | } |
347 | ||
a8170e5e AK |
348 | static DeviceState *slavio_intctl_init(hwaddr addr, |
349 | hwaddr addrg, | |
462eda24 | 350 | qemu_irq **parent_irq) |
4b48bf05 BS |
351 | { |
352 | DeviceState *dev; | |
353 | SysBusDevice *s; | |
354 | unsigned int i, j; | |
355 | ||
3e80f690 | 356 | dev = qdev_new("slavio_intctl"); |
4b48bf05 | 357 | |
1356b98d | 358 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 359 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
360 | |
361 | for (i = 0; i < MAX_CPUS; i++) { | |
362 | for (j = 0; j < MAX_PILS; j++) { | |
363 | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); | |
364 | } | |
365 | } | |
366 | sysbus_mmio_map(s, 0, addrg); | |
367 | for (i = 0; i < MAX_CPUS; i++) { | |
368 | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); | |
369 | } | |
370 | ||
371 | return dev; | |
372 | } | |
373 | ||
374 | #define SYS_TIMER_OFFSET 0x10000ULL | |
375 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) | |
376 | ||
a8170e5e | 377 | static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
4b48bf05 BS |
378 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
379 | { | |
380 | DeviceState *dev; | |
381 | SysBusDevice *s; | |
382 | unsigned int i; | |
383 | ||
3e80f690 | 384 | dev = qdev_new("slavio_timer"); |
4b48bf05 | 385 | qdev_prop_set_uint32(dev, "num_cpus", num_cpus); |
1356b98d | 386 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 387 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
388 | sysbus_connect_irq(s, 0, master_irq); |
389 | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); | |
390 | ||
391 | for (i = 0; i < MAX_CPUS; i++) { | |
a8170e5e | 392 | sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); |
4b48bf05 BS |
393 | sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
394 | } | |
395 | } | |
396 | ||
bea42280 IM |
397 | static qemu_irq slavio_system_powerdown; |
398 | ||
399 | static void slavio_powerdown_req(Notifier *n, void *opaque) | |
400 | { | |
401 | qemu_irq_raise(slavio_system_powerdown); | |
402 | } | |
403 | ||
404 | static Notifier slavio_system_powerdown_notifier = { | |
405 | .notify = slavio_powerdown_req | |
406 | }; | |
407 | ||
4b48bf05 BS |
408 | #define MISC_LEDS 0x01600000 |
409 | #define MISC_CFG 0x01800000 | |
410 | #define MISC_DIAG 0x01a00000 | |
411 | #define MISC_MDM 0x01b00000 | |
412 | #define MISC_SYS 0x01f00000 | |
413 | ||
a8170e5e AK |
414 | static void slavio_misc_init(hwaddr base, |
415 | hwaddr aux1_base, | |
416 | hwaddr aux2_base, qemu_irq irq, | |
b2b6f6ec | 417 | qemu_irq fdc_tc) |
4b48bf05 BS |
418 | { |
419 | DeviceState *dev; | |
420 | SysBusDevice *s; | |
421 | ||
3e80f690 | 422 | dev = qdev_new("slavio_misc"); |
1356b98d | 423 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 424 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
425 | if (base) { |
426 | /* 8 bit registers */ | |
427 | /* Slavio control */ | |
428 | sysbus_mmio_map(s, 0, base + MISC_CFG); | |
429 | /* Diagnostics */ | |
430 | sysbus_mmio_map(s, 1, base + MISC_DIAG); | |
431 | /* Modem control */ | |
432 | sysbus_mmio_map(s, 2, base + MISC_MDM); | |
433 | /* 16 bit registers */ | |
434 | /* ss600mp diag LEDs */ | |
435 | sysbus_mmio_map(s, 3, base + MISC_LEDS); | |
436 | /* 32 bit registers */ | |
437 | /* System control */ | |
438 | sysbus_mmio_map(s, 4, base + MISC_SYS); | |
439 | } | |
440 | if (aux1_base) { | |
441 | /* AUX 1 (Misc System Functions) */ | |
442 | sysbus_mmio_map(s, 5, aux1_base); | |
443 | } | |
444 | if (aux2_base) { | |
445 | /* AUX 2 (Software Powerdown Control) */ | |
446 | sysbus_mmio_map(s, 6, aux2_base); | |
447 | } | |
448 | sysbus_connect_irq(s, 0, irq); | |
449 | sysbus_connect_irq(s, 1, fdc_tc); | |
bea42280 IM |
450 | slavio_system_powerdown = qdev_get_gpio_in(dev, 0); |
451 | qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); | |
4b48bf05 BS |
452 | } |
453 | ||
a8170e5e | 454 | static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
4b48bf05 BS |
455 | { |
456 | DeviceState *dev; | |
457 | SysBusDevice *s; | |
458 | ||
3e80f690 | 459 | dev = qdev_new("eccmemctl"); |
4b48bf05 | 460 | qdev_prop_set_uint32(dev, "version", version); |
1356b98d | 461 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 462 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
463 | sysbus_connect_irq(s, 0, irq); |
464 | sysbus_mmio_map(s, 0, base); | |
465 | if (version == 0) { // SS-600MP only | |
466 | sysbus_mmio_map(s, 1, base + 0x1000); | |
467 | } | |
468 | } | |
469 | ||
a8170e5e | 470 | static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
4b48bf05 BS |
471 | { |
472 | DeviceState *dev; | |
473 | SysBusDevice *s; | |
474 | ||
3e80f690 | 475 | dev = qdev_new("apc"); |
1356b98d | 476 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 477 | sysbus_realize_and_unref(s, &error_fatal); |
4b48bf05 BS |
478 | /* Power management (APC) XXX: not a Slavio device */ |
479 | sysbus_mmio_map(s, 0, power_base); | |
480 | sysbus_connect_irq(s, 0, cpu_halt); | |
481 | } | |
482 | ||
55d7bfe2 | 483 | static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
4b48bf05 BS |
484 | int height, int depth) |
485 | { | |
486 | DeviceState *dev; | |
487 | SysBusDevice *s; | |
488 | ||
e178113f | 489 | dev = qdev_new("sun-tcx"); |
4b48bf05 BS |
490 | qdev_prop_set_uint32(dev, "vram_size", vram_size); |
491 | qdev_prop_set_uint16(dev, "width", width); | |
492 | qdev_prop_set_uint16(dev, "height", height); | |
493 | qdev_prop_set_uint16(dev, "depth", depth); | |
1356b98d | 494 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 495 | sysbus_realize_and_unref(s, &error_fatal); |
55d7bfe2 MCA |
496 | |
497 | /* 10/ROM : FCode ROM */ | |
da87dd7b | 498 | sysbus_mmio_map(s, 0, addr); |
55d7bfe2 MCA |
499 | /* 2/STIP : Stipple */ |
500 | sysbus_mmio_map(s, 1, addr + 0x04000000ULL); | |
501 | /* 3/BLIT : Blitter */ | |
502 | sysbus_mmio_map(s, 2, addr + 0x06000000ULL); | |
503 | /* 5/RSTIP : Raw Stipple */ | |
504 | sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); | |
505 | /* 6/RBLIT : Raw Blitter */ | |
506 | sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); | |
507 | /* 7/TEC : Transform Engine */ | |
508 | sysbus_mmio_map(s, 5, addr + 0x00700000ULL); | |
509 | /* 8/CMAP : DAC */ | |
510 | sysbus_mmio_map(s, 6, addr + 0x00200000ULL); | |
511 | /* 9/THC : */ | |
512 | if (depth == 8) { | |
513 | sysbus_mmio_map(s, 7, addr + 0x00300000ULL); | |
4b48bf05 | 514 | } else { |
55d7bfe2 | 515 | sysbus_mmio_map(s, 7, addr + 0x00301000ULL); |
4b48bf05 | 516 | } |
55d7bfe2 MCA |
517 | /* 11/DHC : */ |
518 | sysbus_mmio_map(s, 8, addr + 0x00240000ULL); | |
519 | /* 12/ALT : */ | |
520 | sysbus_mmio_map(s, 9, addr + 0x00280000ULL); | |
521 | /* 0/DFB8 : 8-bit plane */ | |
522 | sysbus_mmio_map(s, 10, addr + 0x00800000ULL); | |
523 | /* 1/DFB24 : 24bit plane */ | |
524 | sysbus_mmio_map(s, 11, addr + 0x02000000ULL); | |
525 | /* 4/RDFB32: Raw framebuffer. Control plane */ | |
526 | sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); | |
527 | /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ | |
528 | if (depth == 8) { | |
529 | sysbus_mmio_map(s, 13, addr + 0x00301000ULL); | |
530 | } | |
531 | ||
532 | sysbus_connect_irq(s, 0, irq); | |
4b48bf05 BS |
533 | } |
534 | ||
af87bf29 MCA |
535 | static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
536 | int height, int depth) | |
537 | { | |
538 | DeviceState *dev; | |
539 | SysBusDevice *s; | |
540 | ||
3e80f690 | 541 | dev = qdev_new("cgthree"); |
af87bf29 MCA |
542 | qdev_prop_set_uint32(dev, "vram-size", vram_size); |
543 | qdev_prop_set_uint16(dev, "width", width); | |
544 | qdev_prop_set_uint16(dev, "height", height); | |
545 | qdev_prop_set_uint16(dev, "depth", depth); | |
af87bf29 | 546 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 547 | sysbus_realize_and_unref(s, &error_fatal); |
af87bf29 MCA |
548 | |
549 | /* FCode ROM */ | |
550 | sysbus_mmio_map(s, 0, addr); | |
551 | /* DAC */ | |
552 | sysbus_mmio_map(s, 1, addr + 0x400000ULL); | |
553 | /* 8-bit plane */ | |
554 | sysbus_mmio_map(s, 2, addr + 0x800000ULL); | |
555 | ||
556 | sysbus_connect_irq(s, 0, irq); | |
557 | } | |
558 | ||
325f2747 | 559 | /* NCR89C100/MACIO Internal ID register */ |
ef9dfa4c AF |
560 | |
561 | #define TYPE_MACIO_ID_REGISTER "macio_idreg" | |
562 | ||
325f2747 BS |
563 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
564 | ||
a8170e5e | 565 | static void idreg_init(hwaddr addr) |
325f2747 BS |
566 | { |
567 | DeviceState *dev; | |
568 | SysBusDevice *s; | |
569 | ||
3e80f690 | 570 | dev = qdev_new(TYPE_MACIO_ID_REGISTER); |
1356b98d | 571 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 572 | sysbus_realize_and_unref(s, &error_fatal); |
325f2747 BS |
573 | |
574 | sysbus_mmio_map(s, 0, addr); | |
3c8133f9 PM |
575 | address_space_write_rom(&address_space_memory, addr, |
576 | MEMTXATTRS_UNSPECIFIED, | |
577 | idreg_data, sizeof(idreg_data)); | |
325f2747 BS |
578 | } |
579 | ||
8063396b | 580 | OBJECT_DECLARE_SIMPLE_TYPE(IDRegState, MACIO_ID_REGISTER) |
ef9dfa4c | 581 | |
db1015e9 | 582 | struct IDRegState { |
ef9dfa4c AF |
583 | SysBusDevice parent_obj; |
584 | ||
3150fa50 | 585 | MemoryRegion mem; |
db1015e9 | 586 | }; |
3150fa50 | 587 | |
a2a5a7b5 | 588 | static void idreg_realize(DeviceState *ds, Error **errp) |
325f2747 | 589 | { |
a2a5a7b5 TH |
590 | IDRegState *s = MACIO_ID_REGISTER(ds); |
591 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
a2a5a7b5 | 592 | |
02e0ecb4 PMD |
593 | if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.idreg", |
594 | sizeof(idreg_data), errp)) { | |
a2a5a7b5 TH |
595 | return; |
596 | } | |
325f2747 | 597 | |
c5705a77 | 598 | vmstate_register_ram_global(&s->mem); |
3150fa50 | 599 | memory_region_set_readonly(&s->mem, true); |
750ecd44 | 600 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
601 | } |
602 | ||
a2a5a7b5 TH |
603 | static void idreg_class_init(ObjectClass *oc, void *data) |
604 | { | |
605 | DeviceClass *dc = DEVICE_CLASS(oc); | |
606 | ||
607 | dc->realize = idreg_realize; | |
608 | } | |
609 | ||
8c43a6f0 | 610 | static const TypeInfo idreg_info = { |
ef9dfa4c | 611 | .name = TYPE_MACIO_ID_REGISTER, |
39bffca2 AL |
612 | .parent = TYPE_SYS_BUS_DEVICE, |
613 | .instance_size = sizeof(IDRegState), | |
a2a5a7b5 | 614 | .class_init = idreg_class_init, |
325f2747 BS |
615 | }; |
616 | ||
b3a49965 | 617 | #define TYPE_TCX_AFX "tcx_afx" |
8063396b | 618 | OBJECT_DECLARE_SIMPLE_TYPE(AFXState, TCX_AFX) |
b3a49965 | 619 | |
db1015e9 | 620 | struct AFXState { |
b3a49965 AF |
621 | SysBusDevice parent_obj; |
622 | ||
3150fa50 | 623 | MemoryRegion mem; |
db1015e9 | 624 | }; |
3150fa50 | 625 | |
c5de386a | 626 | /* SS-5 TCX AFX register */ |
a8170e5e | 627 | static void afx_init(hwaddr addr) |
c5de386a AT |
628 | { |
629 | DeviceState *dev; | |
630 | SysBusDevice *s; | |
631 | ||
3e80f690 | 632 | dev = qdev_new(TYPE_TCX_AFX); |
1356b98d | 633 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 634 | sysbus_realize_and_unref(s, &error_fatal); |
c5de386a AT |
635 | |
636 | sysbus_mmio_map(s, 0, addr); | |
637 | } | |
638 | ||
a2a5a7b5 | 639 | static void afx_realize(DeviceState *ds, Error **errp) |
c5de386a | 640 | { |
a2a5a7b5 TH |
641 | AFXState *s = TCX_AFX(ds); |
642 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
a2a5a7b5 | 643 | |
02e0ecb4 PMD |
644 | if (!memory_region_init_ram_nomigrate(&s->mem, OBJECT(ds), "sun4m.afx", |
645 | 4, errp)) { | |
a2a5a7b5 TH |
646 | return; |
647 | } | |
c5de386a | 648 | |
c5705a77 | 649 | vmstate_register_ram_global(&s->mem); |
750ecd44 | 650 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
651 | } |
652 | ||
a2a5a7b5 TH |
653 | static void afx_class_init(ObjectClass *oc, void *data) |
654 | { | |
655 | DeviceClass *dc = DEVICE_CLASS(oc); | |
656 | ||
657 | dc->realize = afx_realize; | |
658 | } | |
659 | ||
8c43a6f0 | 660 | static const TypeInfo afx_info = { |
b3a49965 | 661 | .name = TYPE_TCX_AFX, |
39bffca2 AL |
662 | .parent = TYPE_SYS_BUS_DEVICE, |
663 | .instance_size = sizeof(AFXState), | |
a2a5a7b5 | 664 | .class_init = afx_class_init, |
c5de386a AT |
665 | }; |
666 | ||
e6f54c91 | 667 | #define TYPE_OPENPROM "openprom" |
db1015e9 | 668 | typedef struct PROMState PROMState; |
8110fa1d EH |
669 | DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM, |
670 | TYPE_OPENPROM) | |
e6f54c91 | 671 | |
db1015e9 | 672 | struct PROMState { |
e6f54c91 AF |
673 | SysBusDevice parent_obj; |
674 | ||
3150fa50 | 675 | MemoryRegion prom; |
db1015e9 | 676 | }; |
3150fa50 | 677 | |
f48f6569 | 678 | /* Boot PROM (OpenBIOS) */ |
409dbce5 AJ |
679 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
680 | { | |
a8170e5e | 681 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
682 | return addr + *base_addr - PROM_VADDR; |
683 | } | |
684 | ||
a8170e5e | 685 | static void prom_init(hwaddr addr, const char *bios_name) |
f48f6569 BS |
686 | { |
687 | DeviceState *dev; | |
688 | SysBusDevice *s; | |
689 | char *filename; | |
690 | int ret; | |
691 | ||
3e80f690 | 692 | dev = qdev_new(TYPE_OPENPROM); |
1356b98d | 693 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 694 | sysbus_realize_and_unref(s, &error_fatal); |
f48f6569 BS |
695 | |
696 | sysbus_mmio_map(s, 0, addr); | |
697 | ||
698 | /* load boot prom */ | |
699 | if (bios_name == NULL) { | |
700 | bios_name = PROM_FILENAME; | |
701 | } | |
702 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
703 | if (filename) { | |
4366e1db LM |
704 | ret = load_elf(filename, NULL, |
705 | translate_prom_address, &addr, NULL, | |
6cdda0ff | 706 | NULL, NULL, NULL, 1, EM_SPARC, 0, 0); |
f48f6569 BS |
707 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
708 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
709 | } | |
7267c094 | 710 | g_free(filename); |
f48f6569 BS |
711 | } else { |
712 | ret = -1; | |
713 | } | |
714 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
29bd7231 | 715 | error_report("could not load prom '%s'", bios_name); |
f48f6569 BS |
716 | exit(1); |
717 | } | |
718 | } | |
719 | ||
a2a5a7b5 | 720 | static void prom_realize(DeviceState *ds, Error **errp) |
f48f6569 | 721 | { |
a2a5a7b5 TH |
722 | PROMState *s = OPENPROM(ds); |
723 | SysBusDevice *dev = SYS_BUS_DEVICE(ds); | |
a2a5a7b5 | 724 | |
02e0ecb4 PMD |
725 | if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4m.prom", |
726 | PROM_SIZE_MAX, errp)) { | |
a2a5a7b5 TH |
727 | return; |
728 | } | |
f48f6569 | 729 | |
c5705a77 | 730 | vmstate_register_ram_global(&s->prom); |
3150fa50 | 731 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 732 | sysbus_init_mmio(dev, &s->prom); |
f48f6569 BS |
733 | } |
734 | ||
999e12bb AL |
735 | static Property prom_properties[] = { |
736 | {/* end of property list */}, | |
737 | }; | |
738 | ||
739 | static void prom_class_init(ObjectClass *klass, void *data) | |
740 | { | |
39bffca2 | 741 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 742 | |
4f67d30b | 743 | device_class_set_props(dc, prom_properties); |
a2a5a7b5 | 744 | dc->realize = prom_realize; |
999e12bb AL |
745 | } |
746 | ||
8c43a6f0 | 747 | static const TypeInfo prom_info = { |
e6f54c91 | 748 | .name = TYPE_OPENPROM, |
39bffca2 AL |
749 | .parent = TYPE_SYS_BUS_DEVICE, |
750 | .instance_size = sizeof(PROMState), | |
751 | .class_init = prom_class_init, | |
f48f6569 BS |
752 | }; |
753 | ||
5ab6b4c6 | 754 | #define TYPE_SUN4M_MEMORY "memory" |
db1015e9 | 755 | typedef struct RamDevice RamDevice; |
8110fa1d EH |
756 | DECLARE_INSTANCE_CHECKER(RamDevice, SUN4M_RAM, |
757 | TYPE_SUN4M_MEMORY) | |
5ab6b4c6 | 758 | |
db1015e9 | 759 | struct RamDevice { |
5ab6b4c6 | 760 | SysBusDevice parent_obj; |
b2554752 | 761 | HostMemoryBackend *memdev; |
db1015e9 | 762 | }; |
ee6847d1 | 763 | |
a350db85 | 764 | /* System RAM */ |
dc8b6dd9 | 765 | static void ram_realize(DeviceState *dev, Error **errp) |
a350db85 | 766 | { |
5ab6b4c6 | 767 | RamDevice *d = SUN4M_RAM(dev); |
b2554752 | 768 | MemoryRegion *ram = host_memory_backend_get_memory(d->memdev); |
a350db85 | 769 | |
b2554752 | 770 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), ram); |
a350db85 BS |
771 | } |
772 | ||
b2554752 | 773 | static void ram_initfn(Object *obj) |
a350db85 | 774 | { |
b2554752 IM |
775 | RamDevice *d = SUN4M_RAM(obj); |
776 | object_property_add_link(obj, "memdev", TYPE_MEMORY_BACKEND, | |
777 | (Object **)&d->memdev, | |
778 | object_property_allow_set_link, | |
d2623129 | 779 | OBJ_PROP_LINK_STRONG); |
b2554752 | 780 | object_property_set_description(obj, "memdev", "Set RAM backend" |
7eecec7d | 781 | "Valid value is ID of a hostmem backend"); |
a350db85 BS |
782 | } |
783 | ||
999e12bb AL |
784 | static void ram_class_init(ObjectClass *klass, void *data) |
785 | { | |
39bffca2 | 786 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 787 | |
dc8b6dd9 | 788 | dc->realize = ram_realize; |
999e12bb AL |
789 | } |
790 | ||
8c43a6f0 | 791 | static const TypeInfo ram_info = { |
5ab6b4c6 | 792 | .name = TYPE_SUN4M_MEMORY, |
39bffca2 AL |
793 | .parent = TYPE_SYS_BUS_DEVICE, |
794 | .instance_size = sizeof(RamDevice), | |
b2554752 | 795 | .instance_init = ram_initfn, |
39bffca2 | 796 | .class_init = ram_class_init, |
a350db85 BS |
797 | }; |
798 | ||
49cbd887 | 799 | static void cpu_devinit(const char *cpu_type, unsigned int id, |
89835363 | 800 | uint64_t prom_addr, qemu_irq **cpu_irqs) |
666713c0 | 801 | { |
8968f588 | 802 | SPARCCPU *cpu; |
98cec4a2 | 803 | CPUSPARCState *env; |
666713c0 | 804 | |
24f675cd | 805 | cpu = SPARC_CPU(object_new(cpu_type)); |
8968f588 | 806 | env = &cpu->env; |
666713c0 | 807 | |
24f675cd TJB |
808 | qemu_register_reset(sun4m_cpu_reset, cpu); |
809 | object_property_set_bool(OBJECT(cpu), "start-powered-off", id != 0, | |
287fa323 | 810 | &error_abort); |
24f675cd | 811 | qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); |
e97a8a59 | 812 | cpu_sparc_set_id(env, id); |
e0bbf9b5 | 813 | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); |
666713c0 | 814 | env->prom_addr = prom_addr; |
666713c0 BS |
815 | } |
816 | ||
acfbe712 BS |
817 | static void dummy_fdc_tc(void *opaque, int irq, int level) |
818 | { | |
819 | } | |
820 | ||
95bc47de | 821 | static void sun4m_hw_init(MachineState *machine) |
420557e8 | 822 | { |
95bc47de | 823 | const struct sun4m_hwdef *hwdef = SUN4M_MACHINE_GET_CLASS(machine)->hwdef; |
61b97833 | 824 | DeviceState *slavio_intctl; |
713c45fa | 825 | unsigned int i; |
cb0fa36b | 826 | Nvram *nvram; |
9540619d | 827 | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; |
2582cfa0 | 828 | qemu_irq fdc_tc; |
5c6602c5 | 829 | unsigned long kernel_size; |
6031ff8b | 830 | uint32_t initrd_size; |
fd8014e1 | 831 | DriveInfo *fd[MAX_FD]; |
a88b362c | 832 | FWCfgState *fw_cfg; |
a879306c | 833 | DeviceState *dev, *ms_kb_orgate, *serial_orgate; |
2cc75c32 | 834 | SysBusDevice *s; |
33decbd2 LX |
835 | unsigned int smp_cpus = machine->smp.cpus; |
836 | unsigned int max_cpus = machine->smp.max_cpus; | |
26f88d84 | 837 | HostMemoryBackend *ram_memdev = machine->memdev; |
ae0b175b | 838 | MACAddr hostid; |
b2554752 IM |
839 | |
840 | if (machine->ram_size > hwdef->max_mem) { | |
841 | error_report("Too much memory for this machine: %" PRId64 "," | |
842 | " maximum %" PRId64, | |
843 | machine->ram_size / MiB, hwdef->max_mem / MiB); | |
844 | exit(1); | |
845 | } | |
420557e8 | 846 | |
ba3c64fb FB |
847 | /* init CPUs */ |
848 | for(i = 0; i < smp_cpus; i++) { | |
49cbd887 | 849 | cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); |
ba3c64fb | 850 | } |
b3a23197 BS |
851 | |
852 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
853 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
854 | ||
b2554752 | 855 | /* Create and map RAM frontend */ |
3e80f690 | 856 | dev = qdev_new("memory"); |
26f88d84 | 857 | object_property_set_link(OBJECT(dev), "memdev", OBJECT(ram_memdev), &error_fatal); |
3c6ef471 | 858 | sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); |
b2554752 | 859 | sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0); |
3ebf5aaf | 860 | |
676d9b9b AT |
861 | /* models without ECC don't trap when missing ram is accessed */ |
862 | if (!hwdef->ecc_base) { | |
28c78fe8 PMD |
863 | empty_slot_init("ecc", machine->ram_size, |
864 | hwdef->max_mem - machine->ram_size); | |
676d9b9b | 865 | } |
a350db85 | 866 | |
377ce9cb | 867 | prom_init(hwdef->slavio_base, machine->firmware); |
f48f6569 | 868 | |
d453c2c3 BS |
869 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
870 | hwdef->intctl_base + 0x10000ULL, | |
462eda24 | 871 | cpu_irqs); |
a1961a4b BS |
872 | |
873 | for (i = 0; i < 32; i++) { | |
d453c2c3 | 874 | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
a1961a4b BS |
875 | } |
876 | for (i = 0; i < MAX_CPUS; i++) { | |
d453c2c3 | 877 | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); |
a1961a4b | 878 | } |
b3a23197 | 879 | |
fe096129 | 880 | if (hwdef->idreg_base) { |
325f2747 | 881 | idreg_init(hwdef->idreg_base); |
4c2485de BS |
882 | } |
883 | ||
c5de386a AT |
884 | if (hwdef->afx_base) { |
885 | afx_init(hwdef->afx_base); | |
886 | } | |
887 | ||
6aa62ed6 | 888 | iommu_init(hwdef->iommu_base, hwdef->iommu_version, slavio_irq[30]); |
ff403da6 | 889 | |
3386376c AT |
890 | if (hwdef->iommu_pad_base) { |
891 | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. | |
892 | Software shouldn't use aliased addresses, neither should it crash | |
893 | when does. Using empty_slot instead of aliasing can help with | |
894 | debugging such accesses */ | |
28c78fe8 PMD |
895 | empty_slot_init("iommu.alias", |
896 | hwdef->iommu_pad_base, hwdef->iommu_pad_len); | |
3386376c AT |
897 | } |
898 | ||
6aa62ed6 MCA |
899 | sparc32_dma_init(hwdef->dma_base, |
900 | hwdef->esp_base, slavio_irq[18], | |
ae0b175b | 901 | hwdef->le_base, slavio_irq[16], &hostid); |
e6ca02a4 | 902 | |
eee0b836 | 903 | if (graphic_depth != 8 && graphic_depth != 24) { |
af87bf29 | 904 | error_report("Unsupported depth: %d", graphic_depth); |
eee0b836 BS |
905 | exit (1); |
906 | } | |
6807874d | 907 | if (vga_interface_type != VGA_NONE) { |
af87bf29 MCA |
908 | if (vga_interface_type == VGA_CG3) { |
909 | if (graphic_depth != 8) { | |
910 | error_report("Unsupported depth: %d", graphic_depth); | |
911 | exit(1); | |
912 | } | |
913 | ||
914 | if (!(graphic_width == 1024 && graphic_height == 768) && | |
915 | !(graphic_width == 1152 && graphic_height == 900)) { | |
916 | error_report("Unsupported resolution: %d x %d", graphic_width, | |
917 | graphic_height); | |
918 | exit(1); | |
919 | } | |
920 | ||
921 | /* sbus irq 5 */ | |
922 | cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, | |
923 | graphic_width, graphic_height, graphic_depth); | |
f9bcb2d6 | 924 | vga_interface_created = true; |
af87bf29 MCA |
925 | } else { |
926 | /* If no display specified, default to TCX */ | |
927 | if (graphic_depth != 8 && graphic_depth != 24) { | |
928 | error_report("Unsupported depth: %d", graphic_depth); | |
929 | exit(1); | |
930 | } | |
931 | ||
932 | if (!(graphic_width == 1024 && graphic_height == 768)) { | |
933 | error_report("Unsupported resolution: %d x %d", | |
934 | graphic_width, graphic_height); | |
935 | exit(1); | |
936 | } | |
937 | ||
55d7bfe2 MCA |
938 | tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, |
939 | graphic_width, graphic_height, graphic_depth); | |
f9bcb2d6 | 940 | vga_interface_created = true; |
af87bf29 | 941 | } |
9a62fb24 BB |
942 | } |
943 | ||
6807874d | 944 | for (i = 0; i < MAX_VSIMMS; i++) { |
9a62fb24 BB |
945 | /* vsimm registers probed by OBP */ |
946 | if (hwdef->vsimm[i].reg_base) { | |
28c78fe8 PMD |
947 | char *name = g_strdup_printf("vsimm[%d]", i); |
948 | empty_slot_init(name, hwdef->vsimm[i].reg_base, 0x2000); | |
949 | g_free(name); | |
9a62fb24 BB |
950 | } |
951 | } | |
952 | ||
953 | if (hwdef->sx_base) { | |
e178113f | 954 | create_unimplemented_device("sun-sx", hwdef->sx_base, 0x2000); |
9a62fb24 | 955 | } |
dbe06e18 | 956 | |
cb0fa36b MCA |
957 | dev = qdev_new("sysbus-m48t08"); |
958 | qdev_prop_set_int32(dev, "base-year", 1968); | |
959 | s = SYS_BUS_DEVICE(dev); | |
960 | sysbus_realize_and_unref(s, &error_fatal); | |
961 | sysbus_connect_irq(s, 0, slavio_irq[0]); | |
962 | sysbus_mmio_map(s, 0, hwdef->nvram_base); | |
963 | nvram = NVRAM(dev); | |
81732d19 | 964 | |
c533e0b3 | 965 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); |
81732d19 | 966 | |
5cbdb3a3 SW |
967 | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device |
968 | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ | |
3e80f690 | 969 | dev = qdev_new(TYPE_ESCC); |
2cc75c32 LV |
970 | qdev_prop_set_uint32(dev, "disabled", !machine->enable_graphics); |
971 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); | |
972 | qdev_prop_set_uint32(dev, "it_shift", 1); | |
973 | qdev_prop_set_chr(dev, "chrB", NULL); | |
974 | qdev_prop_set_chr(dev, "chrA", NULL); | |
975 | qdev_prop_set_uint32(dev, "chnBtype", escc_mouse); | |
976 | qdev_prop_set_uint32(dev, "chnAtype", escc_kbd); | |
2cc75c32 | 977 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 978 | sysbus_realize_and_unref(s, &error_fatal); |
2cc75c32 LV |
979 | sysbus_mmio_map(s, 0, hwdef->ms_kb_base); |
980 | ||
a879306c MCA |
981 | /* Logically OR both its IRQs together */ |
982 | ms_kb_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | |
983 | object_property_set_int(OBJECT(ms_kb_orgate), "num-lines", 2, &error_fatal); | |
984 | qdev_realize_and_unref(ms_kb_orgate, NULL, &error_fatal); | |
985 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(ms_kb_orgate, 0)); | |
986 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(ms_kb_orgate, 1)); | |
7d5b0d68 | 987 | qdev_connect_gpio_out(ms_kb_orgate, 0, slavio_irq[14]); |
a879306c | 988 | |
3e80f690 | 989 | dev = qdev_new(TYPE_ESCC); |
2cc75c32 LV |
990 | qdev_prop_set_uint32(dev, "disabled", 0); |
991 | qdev_prop_set_uint32(dev, "frequency", ESCC_CLOCK); | |
992 | qdev_prop_set_uint32(dev, "it_shift", 1); | |
9bca0edb PM |
993 | qdev_prop_set_chr(dev, "chrB", serial_hd(1)); |
994 | qdev_prop_set_chr(dev, "chrA", serial_hd(0)); | |
2cc75c32 LV |
995 | qdev_prop_set_uint32(dev, "chnBtype", escc_serial); |
996 | qdev_prop_set_uint32(dev, "chnAtype", escc_serial); | |
2cc75c32 LV |
997 | |
998 | s = SYS_BUS_DEVICE(dev); | |
3c6ef471 | 999 | sysbus_realize_and_unref(s, &error_fatal); |
2cc75c32 | 1000 | sysbus_mmio_map(s, 0, hwdef->serial_base); |
741402f9 | 1001 | |
a879306c MCA |
1002 | /* Logically OR both its IRQs together */ |
1003 | serial_orgate = DEVICE(object_new(TYPE_OR_IRQ)); | |
1004 | object_property_set_int(OBJECT(serial_orgate), "num-lines", 2, | |
1005 | &error_fatal); | |
1006 | qdev_realize_and_unref(serial_orgate, NULL, &error_fatal); | |
1007 | sysbus_connect_irq(s, 0, qdev_get_gpio_in(serial_orgate, 0)); | |
1008 | sysbus_connect_irq(s, 1, qdev_get_gpio_in(serial_orgate, 1)); | |
7d5b0d68 | 1009 | qdev_connect_gpio_out(serial_orgate, 0, slavio_irq[15]); |
a879306c | 1010 | |
2582cfa0 | 1011 | if (hwdef->apc_base) { |
ca43b97b | 1012 | apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); |
2582cfa0 | 1013 | } |
2be17ebd | 1014 | |
fe096129 | 1015 | if (hwdef->fd_base) { |
e4bcb14c | 1016 | /* there is zero or one floppy drive */ |
309e60bd | 1017 | memset(fd, 0, sizeof(fd)); |
fd8014e1 | 1018 | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
c533e0b3 | 1019 | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, |
2582cfa0 | 1020 | &fdc_tc); |
acfbe712 | 1021 | } else { |
ca43b97b | 1022 | fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); |
e4bcb14c TS |
1023 | } |
1024 | ||
acfbe712 BS |
1025 | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
1026 | slavio_irq[30], fdc_tc); | |
1027 | ||
fa28ec52 | 1028 | if (hwdef->cs_base) { |
e178113f | 1029 | sysbus_create_simple("sun-CS4231", hwdef->cs_base, |
c533e0b3 | 1030 | slavio_irq[5]); |
fa28ec52 | 1031 | } |
b3ceef24 | 1032 | |
9a62fb24 BB |
1033 | if (hwdef->dbri_base) { |
1034 | /* ISDN chip with attached CS4215 audio codec */ | |
1035 | /* prom space */ | |
e178113f | 1036 | create_unimplemented_device("sun-DBRI.prom", |
077f0f3d | 1037 | hwdef->dbri_base + 0x1000, 0x30); |
9a62fb24 | 1038 | /* reg space */ |
e178113f | 1039 | create_unimplemented_device("sun-DBRI", |
077f0f3d | 1040 | hwdef->dbri_base + 0x10000, 0x100); |
9a62fb24 BB |
1041 | } |
1042 | ||
1043 | if (hwdef->bpp_base) { | |
1044 | /* parallel port */ | |
e178113f | 1045 | create_unimplemented_device("sun-bpp", hwdef->bpp_base, 0x20); |
9a62fb24 BB |
1046 | } |
1047 | ||
6031ff8b | 1048 | initrd_size = 0; |
3ef96221 MA |
1049 | kernel_size = sun4m_load_kernel(machine->kernel_filename, |
1050 | machine->initrd_filename, | |
6031ff8b | 1051 | machine->ram_size, &initrd_size); |
36cd9210 | 1052 | |
ae0b175b | 1053 | nvram_init(nvram, hostid.a, machine->kernel_cmdline, |
97ec4d21 | 1054 | machine->boot_config.order, machine->ram_size, kernel_size, |
3ef96221 MA |
1055 | graphic_width, graphic_height, graphic_depth, |
1056 | hwdef->nvram_machine_id, "Sun4m"); | |
7eb0c8e8 | 1057 | |
fe096129 | 1058 | if (hwdef->ecc_base) |
c533e0b3 | 1059 | ecc_init(hwdef->ecc_base, slavio_irq[28], |
e42c20b4 | 1060 | hwdef->ecc_version); |
3cce6243 | 1061 | |
3e80f690 | 1062 | dev = qdev_new(TYPE_FW_CFG_MEM); |
84983214 MCA |
1063 | fw_cfg = FW_CFG(dev); |
1064 | qdev_prop_set_uint32(dev, "data_width", 1); | |
1065 | qdev_prop_set_bit(dev, "dma_enabled", false); | |
1066 | object_property_add_child(OBJECT(qdev_get_machine()), TYPE_FW_CFG, | |
d2623129 | 1067 | OBJECT(fw_cfg)); |
84983214 | 1068 | s = SYS_BUS_DEVICE(dev); |
3c6ef471 | 1069 | sysbus_realize_and_unref(s, &error_fatal); |
84983214 MCA |
1070 | sysbus_mmio_map(s, 0, CFG_ADDR); |
1071 | sysbus_mmio_map(s, 1, CFG_ADDR + 2); | |
1072 | ||
5836d168 | 1073 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 1074 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
b2554752 | 1075 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size); |
905fdcb5 | 1076 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); |
fbfcf955 | 1077 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
b96919e0 MCA |
1078 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); |
1079 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); | |
513f789f BS |
1080 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1081 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 1082 | if (machine->kernel_cmdline) { |
513f789f | 1083 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
6b63ef4d | 1084 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, |
3ef96221 MA |
1085 | machine->kernel_cmdline); |
1086 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
748a4ee3 | 1087 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 | 1088 | strlen(machine->kernel_cmdline) + 1); |
513f789f BS |
1089 | } else { |
1090 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
748a4ee3 | 1091 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f BS |
1092 | } |
1093 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
6031ff8b | 1094 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size); |
97ec4d21 | 1095 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]); |
513f789f | 1096 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
36cd9210 BS |
1097 | } |
1098 | ||
905fdcb5 | 1099 | enum { |
905fdcb5 BS |
1100 | ss5_id = 32, |
1101 | vger_id, | |
1102 | lx_id, | |
1103 | ss4_id, | |
1104 | scls_id, | |
1105 | sbook_id, | |
1106 | ss10_id = 64, | |
1107 | ss20_id, | |
1108 | ss600mp_id, | |
905fdcb5 BS |
1109 | }; |
1110 | ||
bcdd781f PMD |
1111 | static void sun4m_machine_class_init(ObjectClass *oc, void *data) |
1112 | { | |
1113 | MachineClass *mc = MACHINE_CLASS(oc); | |
1114 | ||
1115 | mc->init = sun4m_hw_init; | |
1116 | mc->block_default_type = IF_SCSI; | |
1117 | mc->default_boot_order = "c"; | |
1118 | mc->default_display = "tcx"; | |
1119 | mc->default_ram_id = "sun4m.ram"; | |
1120 | } | |
1121 | ||
1122 | static void ss5_class_init(ObjectClass *oc, void *data) | |
1123 | { | |
1124 | MachineClass *mc = MACHINE_CLASS(oc); | |
1125 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1126 | static const struct sun4m_hwdef ss5_hwdef = { | |
36cd9210 | 1127 | .iommu_base = 0x10000000, |
3386376c AT |
1128 | .iommu_pad_base = 0x10004000, |
1129 | .iommu_pad_len = 0x0fffb000, | |
36cd9210 BS |
1130 | .tcx_base = 0x50000000, |
1131 | .cs_base = 0x6c000000, | |
384ccb5d | 1132 | .slavio_base = 0x70000000, |
36cd9210 BS |
1133 | .ms_kb_base = 0x71000000, |
1134 | .serial_base = 0x71100000, | |
1135 | .nvram_base = 0x71200000, | |
1136 | .fd_base = 0x71400000, | |
1137 | .counter_base = 0x71d00000, | |
1138 | .intctl_base = 0x71e00000, | |
4c2485de | 1139 | .idreg_base = 0x78000000, |
36cd9210 BS |
1140 | .dma_base = 0x78400000, |
1141 | .esp_base = 0x78800000, | |
1142 | .le_base = 0x78c00000, | |
127fc407 | 1143 | .apc_base = 0x6a000000, |
c5de386a | 1144 | .afx_base = 0x6e000000, |
0019ad53 BS |
1145 | .aux1_base = 0x71900000, |
1146 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1147 | .nvram_machine_id = 0x80, |
1148 | .machine_id = ss5_id, | |
cf3102ac | 1149 | .iommu_version = 0x05000000, |
3ebf5aaf | 1150 | .max_mem = 0x10000000, |
bcdd781f PMD |
1151 | }; |
1152 | ||
1153 | mc->desc = "Sun4m platform, SPARCstation 5"; | |
1154 | mc->is_default = true; | |
1155 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); | |
1156 | smc->hwdef = &ss5_hwdef; | |
1157 | } | |
1158 | ||
1159 | static void ss10_class_init(ObjectClass *oc, void *data) | |
1160 | { | |
1161 | MachineClass *mc = MACHINE_CLASS(oc); | |
1162 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1163 | static const struct sun4m_hwdef ss10_hwdef = { | |
5dcb6b91 BS |
1164 | .iommu_base = 0xfe0000000ULL, |
1165 | .tcx_base = 0xe20000000ULL, | |
5dcb6b91 BS |
1166 | .slavio_base = 0xff0000000ULL, |
1167 | .ms_kb_base = 0xff1000000ULL, | |
1168 | .serial_base = 0xff1100000ULL, | |
1169 | .nvram_base = 0xff1200000ULL, | |
1170 | .fd_base = 0xff1700000ULL, | |
1171 | .counter_base = 0xff1300000ULL, | |
1172 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1173 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
1174 | .dma_base = 0xef0400000ULL, |
1175 | .esp_base = 0xef0800000ULL, | |
1176 | .le_base = 0xef0c00000ULL, | |
41db3b77 | 1177 | .apc_base = 0xefa000000ULL, /* XXX should not exist */ |
127fc407 BS |
1178 | .aux1_base = 0xff1800000ULL, |
1179 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 | 1180 | .ecc_base = 0xf00000000ULL, |
41db3b77 | 1181 | .ecc_version = 0x10000000, /* version 0, implementation 1 */ |
905fdcb5 BS |
1182 | .nvram_machine_id = 0x72, |
1183 | .machine_id = ss10_id, | |
7fbfb139 | 1184 | .iommu_version = 0x03000000, |
6ef05b95 | 1185 | .max_mem = 0xf00000000ULL, |
bcdd781f PMD |
1186 | }; |
1187 | ||
1188 | mc->desc = "Sun4m platform, SPARCstation 10"; | |
1189 | mc->max_cpus = 4; | |
1190 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); | |
1191 | smc->hwdef = &ss10_hwdef; | |
1192 | } | |
1193 | ||
1194 | static void ss600mp_class_init(ObjectClass *oc, void *data) | |
1195 | { | |
1196 | MachineClass *mc = MACHINE_CLASS(oc); | |
1197 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1198 | static const struct sun4m_hwdef ss600mp_hwdef = { | |
6a3b9cc9 BS |
1199 | .iommu_base = 0xfe0000000ULL, |
1200 | .tcx_base = 0xe20000000ULL, | |
6a3b9cc9 BS |
1201 | .slavio_base = 0xff0000000ULL, |
1202 | .ms_kb_base = 0xff1000000ULL, | |
1203 | .serial_base = 0xff1100000ULL, | |
1204 | .nvram_base = 0xff1200000ULL, | |
6a3b9cc9 BS |
1205 | .counter_base = 0xff1300000ULL, |
1206 | .intctl_base = 0xff1400000ULL, | |
1207 | .dma_base = 0xef0081000ULL, | |
1208 | .esp_base = 0xef0080000ULL, | |
1209 | .le_base = 0xef0060000ULL, | |
41db3b77 | 1210 | .apc_base = 0xefa000000ULL, /* XXX should not exist */ |
127fc407 | 1211 | .aux1_base = 0xff1800000ULL, |
41db3b77 | 1212 | .aux2_base = 0xff1a01000ULL, /* XXX should not exist */ |
7eb0c8e8 | 1213 | .ecc_base = 0xf00000000ULL, |
41db3b77 | 1214 | .ecc_version = 0x00000000, /* version 0, implementation 0 */ |
905fdcb5 BS |
1215 | .nvram_machine_id = 0x71, |
1216 | .machine_id = ss600mp_id, | |
7fbfb139 | 1217 | .iommu_version = 0x01000000, |
6ef05b95 | 1218 | .max_mem = 0xf00000000ULL, |
bcdd781f PMD |
1219 | }; |
1220 | ||
1221 | mc->desc = "Sun4m platform, SPARCserver 600MP"; | |
1222 | mc->max_cpus = 4; | |
1223 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); | |
1224 | smc->hwdef = &ss600mp_hwdef; | |
1225 | } | |
1226 | ||
1227 | static void ss20_class_init(ObjectClass *oc, void *data) | |
1228 | { | |
1229 | MachineClass *mc = MACHINE_CLASS(oc); | |
1230 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1231 | static const struct sun4m_hwdef ss20_hwdef = { | |
ae40972f BS |
1232 | .iommu_base = 0xfe0000000ULL, |
1233 | .tcx_base = 0xe20000000ULL, | |
ae40972f BS |
1234 | .slavio_base = 0xff0000000ULL, |
1235 | .ms_kb_base = 0xff1000000ULL, | |
1236 | .serial_base = 0xff1100000ULL, | |
1237 | .nvram_base = 0xff1200000ULL, | |
1238 | .fd_base = 0xff1700000ULL, | |
1239 | .counter_base = 0xff1300000ULL, | |
1240 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1241 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
1242 | .dma_base = 0xef0400000ULL, |
1243 | .esp_base = 0xef0800000ULL, | |
1244 | .le_base = 0xef0c00000ULL, | |
9a62fb24 | 1245 | .bpp_base = 0xef4800000ULL, |
41db3b77 | 1246 | .apc_base = 0xefa000000ULL, /* XXX should not exist */ |
577d8dd4 BS |
1247 | .aux1_base = 0xff1800000ULL, |
1248 | .aux2_base = 0xff1a01000ULL, | |
9a62fb24 BB |
1249 | .dbri_base = 0xee0000000ULL, |
1250 | .sx_base = 0xf80000000ULL, | |
1251 | .vsimm = { | |
1252 | { | |
1253 | .reg_base = 0x9c000000ULL, | |
1254 | .vram_base = 0xfc000000ULL | |
1255 | }, { | |
1256 | .reg_base = 0x90000000ULL, | |
1257 | .vram_base = 0xf0000000ULL | |
1258 | }, { | |
1259 | .reg_base = 0x94000000ULL | |
1260 | }, { | |
1261 | .reg_base = 0x98000000ULL | |
1262 | } | |
1263 | }, | |
ae40972f | 1264 | .ecc_base = 0xf00000000ULL, |
41db3b77 | 1265 | .ecc_version = 0x20000000, /* version 0, implementation 2 */ |
905fdcb5 BS |
1266 | .nvram_machine_id = 0x72, |
1267 | .machine_id = ss20_id, | |
ae40972f | 1268 | .iommu_version = 0x13000000, |
6ef05b95 | 1269 | .max_mem = 0xf00000000ULL, |
bcdd781f PMD |
1270 | }; |
1271 | ||
1272 | mc->desc = "Sun4m platform, SPARCstation 20"; | |
1273 | mc->max_cpus = 4; | |
1274 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); | |
1275 | smc->hwdef = &ss20_hwdef; | |
1276 | } | |
1277 | ||
1278 | static void voyager_class_init(ObjectClass *oc, void *data) | |
1279 | { | |
1280 | MachineClass *mc = MACHINE_CLASS(oc); | |
1281 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1282 | static const struct sun4m_hwdef voyager_hwdef = { | |
a526a31c BS |
1283 | .iommu_base = 0x10000000, |
1284 | .tcx_base = 0x50000000, | |
a526a31c BS |
1285 | .slavio_base = 0x70000000, |
1286 | .ms_kb_base = 0x71000000, | |
1287 | .serial_base = 0x71100000, | |
1288 | .nvram_base = 0x71200000, | |
1289 | .fd_base = 0x71400000, | |
1290 | .counter_base = 0x71d00000, | |
1291 | .intctl_base = 0x71e00000, | |
1292 | .idreg_base = 0x78000000, | |
1293 | .dma_base = 0x78400000, | |
1294 | .esp_base = 0x78800000, | |
1295 | .le_base = 0x78c00000, | |
41db3b77 | 1296 | .apc_base = 0x71300000, /* pmc */ |
a526a31c BS |
1297 | .aux1_base = 0x71900000, |
1298 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1299 | .nvram_machine_id = 0x80, |
1300 | .machine_id = vger_id, | |
a526a31c | 1301 | .iommu_version = 0x05000000, |
a526a31c | 1302 | .max_mem = 0x10000000, |
bcdd781f PMD |
1303 | }; |
1304 | ||
1305 | mc->desc = "Sun4m platform, SPARCstation Voyager"; | |
1306 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); | |
1307 | smc->hwdef = &voyager_hwdef; | |
1308 | } | |
1309 | ||
1310 | static void ss_lx_class_init(ObjectClass *oc, void *data) | |
1311 | { | |
1312 | MachineClass *mc = MACHINE_CLASS(oc); | |
1313 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1314 | static const struct sun4m_hwdef ss_lx_hwdef = { | |
a526a31c | 1315 | .iommu_base = 0x10000000, |
3386376c AT |
1316 | .iommu_pad_base = 0x10004000, |
1317 | .iommu_pad_len = 0x0fffb000, | |
a526a31c | 1318 | .tcx_base = 0x50000000, |
a526a31c BS |
1319 | .slavio_base = 0x70000000, |
1320 | .ms_kb_base = 0x71000000, | |
1321 | .serial_base = 0x71100000, | |
1322 | .nvram_base = 0x71200000, | |
1323 | .fd_base = 0x71400000, | |
1324 | .counter_base = 0x71d00000, | |
1325 | .intctl_base = 0x71e00000, | |
1326 | .idreg_base = 0x78000000, | |
1327 | .dma_base = 0x78400000, | |
1328 | .esp_base = 0x78800000, | |
1329 | .le_base = 0x78c00000, | |
a526a31c BS |
1330 | .aux1_base = 0x71900000, |
1331 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1332 | .nvram_machine_id = 0x80, |
1333 | .machine_id = lx_id, | |
a526a31c | 1334 | .iommu_version = 0x04000000, |
a526a31c | 1335 | .max_mem = 0x10000000, |
bcdd781f PMD |
1336 | }; |
1337 | ||
1338 | mc->desc = "Sun4m platform, SPARCstation LX"; | |
1339 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); | |
1340 | smc->hwdef = &ss_lx_hwdef; | |
1341 | } | |
1342 | ||
1343 | static void ss4_class_init(ObjectClass *oc, void *data) | |
1344 | { | |
1345 | MachineClass *mc = MACHINE_CLASS(oc); | |
1346 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1347 | static const struct sun4m_hwdef ss4_hwdef = { | |
a526a31c BS |
1348 | .iommu_base = 0x10000000, |
1349 | .tcx_base = 0x50000000, | |
1350 | .cs_base = 0x6c000000, | |
1351 | .slavio_base = 0x70000000, | |
1352 | .ms_kb_base = 0x71000000, | |
1353 | .serial_base = 0x71100000, | |
1354 | .nvram_base = 0x71200000, | |
1355 | .fd_base = 0x71400000, | |
1356 | .counter_base = 0x71d00000, | |
1357 | .intctl_base = 0x71e00000, | |
1358 | .idreg_base = 0x78000000, | |
1359 | .dma_base = 0x78400000, | |
1360 | .esp_base = 0x78800000, | |
1361 | .le_base = 0x78c00000, | |
1362 | .apc_base = 0x6a000000, | |
1363 | .aux1_base = 0x71900000, | |
1364 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1365 | .nvram_machine_id = 0x80, |
1366 | .machine_id = ss4_id, | |
a526a31c | 1367 | .iommu_version = 0x05000000, |
a526a31c | 1368 | .max_mem = 0x10000000, |
bcdd781f PMD |
1369 | }; |
1370 | ||
1371 | mc->desc = "Sun4m platform, SPARCstation 4"; | |
1372 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); | |
1373 | smc->hwdef = &ss4_hwdef; | |
1374 | } | |
1375 | ||
1376 | static void scls_class_init(ObjectClass *oc, void *data) | |
1377 | { | |
1378 | MachineClass *mc = MACHINE_CLASS(oc); | |
1379 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1380 | static const struct sun4m_hwdef scls_hwdef = { | |
a526a31c BS |
1381 | .iommu_base = 0x10000000, |
1382 | .tcx_base = 0x50000000, | |
a526a31c BS |
1383 | .slavio_base = 0x70000000, |
1384 | .ms_kb_base = 0x71000000, | |
1385 | .serial_base = 0x71100000, | |
1386 | .nvram_base = 0x71200000, | |
1387 | .fd_base = 0x71400000, | |
1388 | .counter_base = 0x71d00000, | |
1389 | .intctl_base = 0x71e00000, | |
1390 | .idreg_base = 0x78000000, | |
1391 | .dma_base = 0x78400000, | |
1392 | .esp_base = 0x78800000, | |
1393 | .le_base = 0x78c00000, | |
1394 | .apc_base = 0x6a000000, | |
1395 | .aux1_base = 0x71900000, | |
1396 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1397 | .nvram_machine_id = 0x80, |
1398 | .machine_id = scls_id, | |
a526a31c | 1399 | .iommu_version = 0x05000000, |
a526a31c | 1400 | .max_mem = 0x10000000, |
bcdd781f PMD |
1401 | }; |
1402 | ||
1403 | mc->desc = "Sun4m platform, SPARCClassic"; | |
1404 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); | |
1405 | smc->hwdef = &scls_hwdef; | |
1406 | } | |
1407 | ||
1408 | static void sbook_class_init(ObjectClass *oc, void *data) | |
1409 | { | |
1410 | MachineClass *mc = MACHINE_CLASS(oc); | |
1411 | Sun4mMachineClass *smc = SUN4M_MACHINE_CLASS(mc); | |
1412 | static const struct sun4m_hwdef sbook_hwdef = { | |
a526a31c | 1413 | .iommu_base = 0x10000000, |
41db3b77 | 1414 | .tcx_base = 0x50000000, /* XXX */ |
a526a31c BS |
1415 | .slavio_base = 0x70000000, |
1416 | .ms_kb_base = 0x71000000, | |
1417 | .serial_base = 0x71100000, | |
1418 | .nvram_base = 0x71200000, | |
1419 | .fd_base = 0x71400000, | |
1420 | .counter_base = 0x71d00000, | |
1421 | .intctl_base = 0x71e00000, | |
1422 | .idreg_base = 0x78000000, | |
1423 | .dma_base = 0x78400000, | |
1424 | .esp_base = 0x78800000, | |
1425 | .le_base = 0x78c00000, | |
1426 | .apc_base = 0x6a000000, | |
1427 | .aux1_base = 0x71900000, | |
1428 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1429 | .nvram_machine_id = 0x80, |
1430 | .machine_id = sbook_id, | |
a526a31c | 1431 | .iommu_version = 0x05000000, |
a526a31c | 1432 | .max_mem = 0x10000000, |
bcdd781f | 1433 | }; |
8a661aea | 1434 | |
e264d29d | 1435 | mc->desc = "Sun4m platform, SPARCbook"; |
49cbd887 | 1436 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
bcdd781f | 1437 | smc->hwdef = &sbook_hwdef; |
e264d29d EH |
1438 | } |
1439 | ||
828d01b7 PMD |
1440 | static const TypeInfo sun4m_machine_types[] = { |
1441 | { | |
355eb81a PMD |
1442 | .name = MACHINE_TYPE_NAME("SS-5"), |
1443 | .parent = TYPE_SUN4M_MACHINE, | |
1444 | .class_init = ss5_class_init, | |
1445 | }, { | |
1446 | .name = MACHINE_TYPE_NAME("SS-10"), | |
1447 | .parent = TYPE_SUN4M_MACHINE, | |
1448 | .class_init = ss10_class_init, | |
1449 | }, { | |
1450 | .name = MACHINE_TYPE_NAME("SS-600MP"), | |
1451 | .parent = TYPE_SUN4M_MACHINE, | |
1452 | .class_init = ss600mp_class_init, | |
1453 | }, { | |
1454 | .name = MACHINE_TYPE_NAME("SS-20"), | |
1455 | .parent = TYPE_SUN4M_MACHINE, | |
1456 | .class_init = ss20_class_init, | |
1457 | }, { | |
1458 | .name = MACHINE_TYPE_NAME("Voyager"), | |
1459 | .parent = TYPE_SUN4M_MACHINE, | |
1460 | .class_init = voyager_class_init, | |
1461 | }, { | |
1462 | .name = MACHINE_TYPE_NAME("LX"), | |
1463 | .parent = TYPE_SUN4M_MACHINE, | |
1464 | .class_init = ss_lx_class_init, | |
1465 | }, { | |
1466 | .name = MACHINE_TYPE_NAME("SS-4"), | |
1467 | .parent = TYPE_SUN4M_MACHINE, | |
1468 | .class_init = ss4_class_init, | |
1469 | }, { | |
1470 | .name = MACHINE_TYPE_NAME("SPARCClassic"), | |
1471 | .parent = TYPE_SUN4M_MACHINE, | |
1472 | .class_init = scls_class_init, | |
1473 | }, { | |
1474 | .name = MACHINE_TYPE_NAME("SPARCbook"), | |
1475 | .parent = TYPE_SUN4M_MACHINE, | |
1476 | .class_init = sbook_class_init, | |
1477 | }, { | |
828d01b7 PMD |
1478 | .name = TYPE_SUN4M_MACHINE, |
1479 | .parent = TYPE_MACHINE, | |
95bc47de | 1480 | .class_size = sizeof(Sun4mMachineClass), |
f55e8977 | 1481 | .class_init = sun4m_machine_class_init, |
828d01b7 PMD |
1482 | .abstract = true, |
1483 | } | |
1484 | }; | |
1485 | ||
1486 | DEFINE_TYPES(sun4m_machine_types) | |
1487 | ||
83f7d43a AF |
1488 | static void sun4m_register_types(void) |
1489 | { | |
1490 | type_register_static(&idreg_info); | |
1491 | type_register_static(&afx_info); | |
1492 | type_register_static(&prom_info); | |
1493 | type_register_static(&ram_info); | |
8a661aea AF |
1494 | } |
1495 | ||
83f7d43a | 1496 | type_init(sun4m_register_types) |