]>
Commit | Line | Data |
---|---|---|
420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
db5ebe5f | 24 | #include "qemu/osdep.h" |
da34e65c | 25 | #include "qapi/error.h" |
4771d756 PB |
26 | #include "qemu-common.h" |
27 | #include "cpu.h" | |
83c9f4ca | 28 | #include "hw/sysbus.h" |
af87bf29 | 29 | #include "qemu/error-report.h" |
1de7afc9 | 30 | #include "qemu/timer.h" |
0d09e41a PB |
31 | #include "hw/sparc/sun4m.h" |
32 | #include "hw/timer/m48t59.h" | |
33 | #include "hw/sparc/sparc32_dma.h" | |
34 | #include "hw/block/fdc.h" | |
9c17d615 | 35 | #include "sysemu/sysemu.h" |
1422e32d | 36 | #include "net/net.h" |
83c9f4ca | 37 | #include "hw/boards.h" |
0d09e41a PB |
38 | #include "hw/scsi/esp.h" |
39 | #include "hw/i386/pc.h" | |
40 | #include "hw/isa/isa.h" | |
c6363bae | 41 | #include "hw/nvram/sun_nvram.h" |
2024c014 | 42 | #include "hw/nvram/chrp_nvram.h" |
0d09e41a PB |
43 | #include "hw/nvram/fw_cfg.h" |
44 | #include "hw/char/escc.h" | |
83c9f4ca | 45 | #include "hw/empty_slot.h" |
83c9f4ca | 46 | #include "hw/loader.h" |
ca20cf32 | 47 | #include "elf.h" |
4be74634 | 48 | #include "sysemu/block-backend.h" |
97bf4851 | 49 | #include "trace.h" |
f348b6d1 | 50 | #include "qemu/cutils.h" |
420557e8 | 51 | |
36cd9210 BS |
52 | /* |
53 | * Sun4m architecture was used in the following machines: | |
54 | * | |
55 | * SPARCserver 6xxMP/xx | |
77f193da BS |
56 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), |
57 | * SPARCclassic X (4/10) | |
36cd9210 BS |
58 | * SPARCstation LX/ZX (4/30) |
59 | * SPARCstation Voyager | |
60 | * SPARCstation 10/xx, SPARCserver 10/xx | |
61 | * SPARCstation 5, SPARCserver 5 | |
62 | * SPARCstation 20/xx, SPARCserver 20 | |
63 | * SPARCstation 4 | |
64 | * | |
65 | * See for example: http://www.sunhelp.org/faq/sunref1.html | |
66 | */ | |
67 | ||
420557e8 | 68 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 69 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 70 | #define INITRD_LOAD_ADDR 0x00800000 |
a7227727 | 71 | #define PROM_SIZE_MAX (1024 * 1024) |
40ce0a9a | 72 | #define PROM_VADDR 0xffd00000 |
f930d07e | 73 | #define PROM_FILENAME "openbios-sparc32" |
3cce6243 | 74 | #define CFG_ADDR 0xd00000510ULL |
fbfcf955 | 75 | #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00) |
b96919e0 MCA |
76 | #define FW_CFG_SUN4M_WIDTH (FW_CFG_ARCH_LOCAL + 0x01) |
77 | #define FW_CFG_SUN4M_HEIGHT (FW_CFG_ARCH_LOCAL + 0x02) | |
b8174937 | 78 | |
ba3c64fb | 79 | #define MAX_CPUS 16 |
b3a23197 | 80 | #define MAX_PILS 16 |
9a62fb24 | 81 | #define MAX_VSIMMS 4 |
420557e8 | 82 | |
b4ed08e0 BS |
83 | #define ESCC_CLOCK 4915200 |
84 | ||
8137cde8 | 85 | struct sun4m_hwdef { |
a8170e5e AK |
86 | hwaddr iommu_base, iommu_pad_base, iommu_pad_len, slavio_base; |
87 | hwaddr intctl_base, counter_base, nvram_base, ms_kb_base; | |
88 | hwaddr serial_base, fd_base; | |
89 | hwaddr afx_base, idreg_base, dma_base, esp_base, le_base; | |
90 | hwaddr tcx_base, cs_base, apc_base, aux1_base, aux2_base; | |
91 | hwaddr bpp_base, dbri_base, sx_base; | |
9a62fb24 | 92 | struct { |
a8170e5e | 93 | hwaddr reg_base, vram_base; |
9a62fb24 | 94 | } vsimm[MAX_VSIMMS]; |
a8170e5e | 95 | hwaddr ecc_base; |
3ebf5aaf | 96 | uint64_t max_mem; |
61999750 BS |
97 | uint32_t ecc_version; |
98 | uint32_t iommu_version; | |
99 | uint16_t machine_id; | |
100 | uint8_t nvram_machine_id; | |
36cd9210 BS |
101 | }; |
102 | ||
57146941 | 103 | void DMA_init(ISABus *bus, int high_page_enable) |
4556bd8b BS |
104 | { |
105 | } | |
106 | ||
ddcd5531 GA |
107 | static void fw_cfg_boot_set(void *opaque, const char *boot_device, |
108 | Error **errp) | |
81864572 | 109 | { |
48779e50 | 110 | fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]); |
81864572 BS |
111 | } |
112 | ||
31688246 | 113 | static void nvram_init(Nvram *nvram, uint8_t *macaddr, |
43a34704 BS |
114 | const char *cmdline, const char *boot_devices, |
115 | ram_addr_t RAM_size, uint32_t kernel_size, | |
f930d07e | 116 | int width, int height, int depth, |
905fdcb5 | 117 | int nvram_machine_id, const char *arch) |
e80cfcfc | 118 | { |
d2c63fc1 | 119 | unsigned int i; |
2024c014 | 120 | int sysp_end; |
d2c63fc1 | 121 | uint8_t image[0x1ff0]; |
31688246 | 122 | NvramClass *k = NVRAM_GET_CLASS(nvram); |
d2c63fc1 BS |
123 | |
124 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 125 | |
2024c014 TH |
126 | /* OpenBIOS nvram variables partition */ |
127 | sysp_end = chrp_nvram_create_system_partition(image, 0); | |
b6f479d3 | 128 | |
2024c014 TH |
129 | /* Free space partition */ |
130 | chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end); | |
d2c63fc1 | 131 | |
905fdcb5 BS |
132 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, |
133 | nvram_machine_id); | |
d2c63fc1 | 134 | |
31688246 HP |
135 | for (i = 0; i < sizeof(image); i++) { |
136 | (k->write)(nvram, i, image[i]); | |
137 | } | |
e80cfcfc FB |
138 | } |
139 | ||
98cec4a2 | 140 | void cpu_check_irqs(CPUSPARCState *env) |
327ac2e7 | 141 | { |
d8ed887b AF |
142 | CPUState *cs; |
143 | ||
5ee59930 AB |
144 | /* We should be holding the BQL before we mess with IRQs */ |
145 | g_assert(qemu_mutex_iothread_locked()); | |
146 | ||
327ac2e7 BS |
147 | if (env->pil_in && (env->interrupt_index == 0 || |
148 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
149 | unsigned int i; | |
150 | ||
151 | for (i = 15; i > 0; i--) { | |
152 | if (env->pil_in & (1 << i)) { | |
153 | int old_interrupt = env->interrupt_index; | |
154 | ||
155 | env->interrupt_index = TT_EXTINT | i; | |
f32d7ec5 | 156 | if (old_interrupt != env->interrupt_index) { |
c3affe56 | 157 | cs = CPU(sparc_env_get_cpu(env)); |
97bf4851 | 158 | trace_sun4m_cpu_interrupt(i); |
c3affe56 | 159 | cpu_interrupt(cs, CPU_INTERRUPT_HARD); |
f32d7ec5 | 160 | } |
327ac2e7 BS |
161 | break; |
162 | } | |
163 | } | |
164 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
d8ed887b | 165 | cs = CPU(sparc_env_get_cpu(env)); |
97bf4851 | 166 | trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15); |
327ac2e7 | 167 | env->interrupt_index = 0; |
d8ed887b | 168 | cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); |
327ac2e7 BS |
169 | } |
170 | } | |
171 | ||
38c66cf2 | 172 | static void cpu_kick_irq(SPARCCPU *cpu) |
94ad5b00 | 173 | { |
38c66cf2 | 174 | CPUSPARCState *env = &cpu->env; |
259186a7 | 175 | CPUState *cs = CPU(cpu); |
38c66cf2 | 176 | |
259186a7 | 177 | cs->halted = 0; |
94ad5b00 | 178 | cpu_check_irqs(env); |
259186a7 | 179 | qemu_cpu_kick(cs); |
94ad5b00 PB |
180 | } |
181 | ||
b3a23197 BS |
182 | static void cpu_set_irq(void *opaque, int irq, int level) |
183 | { | |
e0bbf9b5 AF |
184 | SPARCCPU *cpu = opaque; |
185 | CPUSPARCState *env = &cpu->env; | |
b3a23197 BS |
186 | |
187 | if (level) { | |
97bf4851 | 188 | trace_sun4m_cpu_set_irq_raise(irq); |
327ac2e7 | 189 | env->pil_in |= 1 << irq; |
38c66cf2 | 190 | cpu_kick_irq(cpu); |
b3a23197 | 191 | } else { |
97bf4851 | 192 | trace_sun4m_cpu_set_irq_lower(irq); |
327ac2e7 BS |
193 | env->pil_in &= ~(1 << irq); |
194 | cpu_check_irqs(env); | |
b3a23197 BS |
195 | } |
196 | } | |
197 | ||
198 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
199 | { | |
200 | } | |
201 | ||
c68ea704 FB |
202 | static void main_cpu_reset(void *opaque) |
203 | { | |
5414dec6 | 204 | SPARCCPU *cpu = opaque; |
259186a7 | 205 | CPUState *cs = CPU(cpu); |
3d29fbef | 206 | |
259186a7 AF |
207 | cpu_reset(cs); |
208 | cs->halted = 0; | |
3d29fbef BS |
209 | } |
210 | ||
211 | static void secondary_cpu_reset(void *opaque) | |
212 | { | |
5414dec6 | 213 | SPARCCPU *cpu = opaque; |
259186a7 | 214 | CPUState *cs = CPU(cpu); |
3d29fbef | 215 | |
259186a7 AF |
216 | cpu_reset(cs); |
217 | cs->halted = 1; | |
c68ea704 FB |
218 | } |
219 | ||
6d0c293d BS |
220 | static void cpu_halt_signal(void *opaque, int irq, int level) |
221 | { | |
4917cf44 AF |
222 | if (level && current_cpu) { |
223 | cpu_interrupt(current_cpu, CPU_INTERRUPT_HALT); | |
c3affe56 | 224 | } |
6d0c293d BS |
225 | } |
226 | ||
409dbce5 AJ |
227 | static uint64_t translate_kernel_address(void *opaque, uint64_t addr) |
228 | { | |
229 | return addr - 0xf0000000ULL; | |
230 | } | |
231 | ||
3ebf5aaf | 232 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
293f78bc | 233 | const char *initrd_filename, |
c227f099 | 234 | ram_addr_t RAM_size) |
3ebf5aaf BS |
235 | { |
236 | int linux_boot; | |
237 | unsigned int i; | |
238 | long initrd_size, kernel_size; | |
3c178e72 | 239 | uint8_t *ptr; |
3ebf5aaf BS |
240 | |
241 | linux_boot = (kernel_filename != NULL); | |
242 | ||
243 | kernel_size = 0; | |
244 | if (linux_boot) { | |
ca20cf32 BS |
245 | int bswap_needed; |
246 | ||
247 | #ifdef BSWAP_NEEDED | |
248 | bswap_needed = 1; | |
249 | #else | |
250 | bswap_needed = 0; | |
251 | #endif | |
409dbce5 | 252 | kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL, |
7ef295ea | 253 | NULL, NULL, NULL, 1, EM_SPARC, 0, 0); |
3ebf5aaf | 254 | if (kernel_size < 0) |
293f78bc | 255 | kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR, |
ca20cf32 BS |
256 | RAM_size - KERNEL_LOAD_ADDR, bswap_needed, |
257 | TARGET_PAGE_SIZE); | |
3ebf5aaf | 258 | if (kernel_size < 0) |
293f78bc BS |
259 | kernel_size = load_image_targphys(kernel_filename, |
260 | KERNEL_LOAD_ADDR, | |
261 | RAM_size - KERNEL_LOAD_ADDR); | |
3ebf5aaf BS |
262 | if (kernel_size < 0) { |
263 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
264 | kernel_filename); | |
265 | exit(1); | |
266 | } | |
267 | ||
268 | /* load initrd */ | |
269 | initrd_size = 0; | |
270 | if (initrd_filename) { | |
293f78bc BS |
271 | initrd_size = load_image_targphys(initrd_filename, |
272 | INITRD_LOAD_ADDR, | |
273 | RAM_size - INITRD_LOAD_ADDR); | |
3ebf5aaf BS |
274 | if (initrd_size < 0) { |
275 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
276 | initrd_filename); | |
277 | exit(1); | |
278 | } | |
279 | } | |
280 | if (initrd_size > 0) { | |
281 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
3c178e72 GH |
282 | ptr = rom_ptr(KERNEL_LOAD_ADDR + i); |
283 | if (ldl_p(ptr) == 0x48647253) { // HdrS | |
284 | stl_p(ptr + 16, INITRD_LOAD_ADDR); | |
285 | stl_p(ptr + 20, initrd_size); | |
3ebf5aaf BS |
286 | break; |
287 | } | |
288 | } | |
289 | } | |
290 | } | |
291 | return kernel_size; | |
292 | } | |
293 | ||
a8170e5e | 294 | static void *iommu_init(hwaddr addr, uint32_t version, qemu_irq irq) |
4b48bf05 BS |
295 | { |
296 | DeviceState *dev; | |
297 | SysBusDevice *s; | |
298 | ||
f542ad03 | 299 | dev = qdev_create(NULL, TYPE_SUN4M_IOMMU); |
4b48bf05 | 300 | qdev_prop_set_uint32(dev, "version", version); |
e23a1b33 | 301 | qdev_init_nofail(dev); |
1356b98d | 302 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
303 | sysbus_connect_irq(s, 0, irq); |
304 | sysbus_mmio_map(s, 0, addr); | |
305 | ||
306 | return s; | |
307 | } | |
308 | ||
9540619d | 309 | static void *sparc32_dma_init(hwaddr daddr, void *iommu, int is_ledma) |
74ff8d90 BS |
310 | { |
311 | DeviceState *dev; | |
312 | SysBusDevice *s; | |
313 | ||
52d39e5b | 314 | dev = qdev_create(NULL, is_ledma ? "sparc32-ledma" : "sparc32-espdma"); |
f542ad03 | 315 | object_property_set_link(OBJECT(dev), OBJECT(iommu), "iommu", &error_abort); |
e23a1b33 | 316 | qdev_init_nofail(dev); |
1356b98d | 317 | s = SYS_BUS_DEVICE(dev); |
74ff8d90 BS |
318 | sysbus_mmio_map(s, 0, daddr); |
319 | ||
320 | return s; | |
321 | } | |
322 | ||
a8170e5e | 323 | static void lance_init(NICInfo *nd, hwaddr leaddr, |
74ff8d90 | 324 | void *dma_opaque, qemu_irq irq) |
9d07d757 PB |
325 | { |
326 | DeviceState *dev; | |
327 | SysBusDevice *s; | |
74ff8d90 | 328 | qemu_irq reset; |
9d07d757 PB |
329 | |
330 | qemu_check_nic_model(&nd_table[0], "lance"); | |
331 | ||
332 | dev = qdev_create(NULL, "lance"); | |
76224833 | 333 | qdev_set_nic_properties(dev, nd); |
daa65491 | 334 | qdev_prop_set_ptr(dev, "dma", dma_opaque); |
e23a1b33 | 335 | qdev_init_nofail(dev); |
1356b98d | 336 | s = SYS_BUS_DEVICE(dev); |
9d07d757 PB |
337 | sysbus_mmio_map(s, 0, leaddr); |
338 | sysbus_connect_irq(s, 0, irq); | |
74ff8d90 BS |
339 | reset = qdev_get_gpio_in(dev, 0); |
340 | qdev_connect_gpio_out(dma_opaque, 0, reset); | |
9d07d757 PB |
341 | } |
342 | ||
a8170e5e AK |
343 | static DeviceState *slavio_intctl_init(hwaddr addr, |
344 | hwaddr addrg, | |
462eda24 | 345 | qemu_irq **parent_irq) |
4b48bf05 BS |
346 | { |
347 | DeviceState *dev; | |
348 | SysBusDevice *s; | |
349 | unsigned int i, j; | |
350 | ||
351 | dev = qdev_create(NULL, "slavio_intctl"); | |
e23a1b33 | 352 | qdev_init_nofail(dev); |
4b48bf05 | 353 | |
1356b98d | 354 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
355 | |
356 | for (i = 0; i < MAX_CPUS; i++) { | |
357 | for (j = 0; j < MAX_PILS; j++) { | |
358 | sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]); | |
359 | } | |
360 | } | |
361 | sysbus_mmio_map(s, 0, addrg); | |
362 | for (i = 0; i < MAX_CPUS; i++) { | |
363 | sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE); | |
364 | } | |
365 | ||
366 | return dev; | |
367 | } | |
368 | ||
369 | #define SYS_TIMER_OFFSET 0x10000ULL | |
370 | #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu) | |
371 | ||
a8170e5e | 372 | static void slavio_timer_init_all(hwaddr addr, qemu_irq master_irq, |
4b48bf05 BS |
373 | qemu_irq *cpu_irqs, unsigned int num_cpus) |
374 | { | |
375 | DeviceState *dev; | |
376 | SysBusDevice *s; | |
377 | unsigned int i; | |
378 | ||
379 | dev = qdev_create(NULL, "slavio_timer"); | |
380 | qdev_prop_set_uint32(dev, "num_cpus", num_cpus); | |
e23a1b33 | 381 | qdev_init_nofail(dev); |
1356b98d | 382 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
383 | sysbus_connect_irq(s, 0, master_irq); |
384 | sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET); | |
385 | ||
386 | for (i = 0; i < MAX_CPUS; i++) { | |
a8170e5e | 387 | sysbus_mmio_map(s, i + 1, addr + (hwaddr)CPU_TIMER_OFFSET(i)); |
4b48bf05 BS |
388 | sysbus_connect_irq(s, i + 1, cpu_irqs[i]); |
389 | } | |
390 | } | |
391 | ||
bea42280 IM |
392 | static qemu_irq slavio_system_powerdown; |
393 | ||
394 | static void slavio_powerdown_req(Notifier *n, void *opaque) | |
395 | { | |
396 | qemu_irq_raise(slavio_system_powerdown); | |
397 | } | |
398 | ||
399 | static Notifier slavio_system_powerdown_notifier = { | |
400 | .notify = slavio_powerdown_req | |
401 | }; | |
402 | ||
4b48bf05 BS |
403 | #define MISC_LEDS 0x01600000 |
404 | #define MISC_CFG 0x01800000 | |
405 | #define MISC_DIAG 0x01a00000 | |
406 | #define MISC_MDM 0x01b00000 | |
407 | #define MISC_SYS 0x01f00000 | |
408 | ||
a8170e5e AK |
409 | static void slavio_misc_init(hwaddr base, |
410 | hwaddr aux1_base, | |
411 | hwaddr aux2_base, qemu_irq irq, | |
b2b6f6ec | 412 | qemu_irq fdc_tc) |
4b48bf05 BS |
413 | { |
414 | DeviceState *dev; | |
415 | SysBusDevice *s; | |
416 | ||
417 | dev = qdev_create(NULL, "slavio_misc"); | |
e23a1b33 | 418 | qdev_init_nofail(dev); |
1356b98d | 419 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
420 | if (base) { |
421 | /* 8 bit registers */ | |
422 | /* Slavio control */ | |
423 | sysbus_mmio_map(s, 0, base + MISC_CFG); | |
424 | /* Diagnostics */ | |
425 | sysbus_mmio_map(s, 1, base + MISC_DIAG); | |
426 | /* Modem control */ | |
427 | sysbus_mmio_map(s, 2, base + MISC_MDM); | |
428 | /* 16 bit registers */ | |
429 | /* ss600mp diag LEDs */ | |
430 | sysbus_mmio_map(s, 3, base + MISC_LEDS); | |
431 | /* 32 bit registers */ | |
432 | /* System control */ | |
433 | sysbus_mmio_map(s, 4, base + MISC_SYS); | |
434 | } | |
435 | if (aux1_base) { | |
436 | /* AUX 1 (Misc System Functions) */ | |
437 | sysbus_mmio_map(s, 5, aux1_base); | |
438 | } | |
439 | if (aux2_base) { | |
440 | /* AUX 2 (Software Powerdown Control) */ | |
441 | sysbus_mmio_map(s, 6, aux2_base); | |
442 | } | |
443 | sysbus_connect_irq(s, 0, irq); | |
444 | sysbus_connect_irq(s, 1, fdc_tc); | |
bea42280 IM |
445 | slavio_system_powerdown = qdev_get_gpio_in(dev, 0); |
446 | qemu_register_powerdown_notifier(&slavio_system_powerdown_notifier); | |
4b48bf05 BS |
447 | } |
448 | ||
a8170e5e | 449 | static void ecc_init(hwaddr base, qemu_irq irq, uint32_t version) |
4b48bf05 BS |
450 | { |
451 | DeviceState *dev; | |
452 | SysBusDevice *s; | |
453 | ||
454 | dev = qdev_create(NULL, "eccmemctl"); | |
455 | qdev_prop_set_uint32(dev, "version", version); | |
e23a1b33 | 456 | qdev_init_nofail(dev); |
1356b98d | 457 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
458 | sysbus_connect_irq(s, 0, irq); |
459 | sysbus_mmio_map(s, 0, base); | |
460 | if (version == 0) { // SS-600MP only | |
461 | sysbus_mmio_map(s, 1, base + 0x1000); | |
462 | } | |
463 | } | |
464 | ||
a8170e5e | 465 | static void apc_init(hwaddr power_base, qemu_irq cpu_halt) |
4b48bf05 BS |
466 | { |
467 | DeviceState *dev; | |
468 | SysBusDevice *s; | |
469 | ||
470 | dev = qdev_create(NULL, "apc"); | |
e23a1b33 | 471 | qdev_init_nofail(dev); |
1356b98d | 472 | s = SYS_BUS_DEVICE(dev); |
4b48bf05 BS |
473 | /* Power management (APC) XXX: not a Slavio device */ |
474 | sysbus_mmio_map(s, 0, power_base); | |
475 | sysbus_connect_irq(s, 0, cpu_halt); | |
476 | } | |
477 | ||
55d7bfe2 | 478 | static void tcx_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
4b48bf05 BS |
479 | int height, int depth) |
480 | { | |
481 | DeviceState *dev; | |
482 | SysBusDevice *s; | |
483 | ||
484 | dev = qdev_create(NULL, "SUNW,tcx"); | |
4b48bf05 BS |
485 | qdev_prop_set_uint32(dev, "vram_size", vram_size); |
486 | qdev_prop_set_uint16(dev, "width", width); | |
487 | qdev_prop_set_uint16(dev, "height", height); | |
488 | qdev_prop_set_uint16(dev, "depth", depth); | |
e23a1b33 | 489 | qdev_init_nofail(dev); |
1356b98d | 490 | s = SYS_BUS_DEVICE(dev); |
55d7bfe2 MCA |
491 | |
492 | /* 10/ROM : FCode ROM */ | |
da87dd7b | 493 | sysbus_mmio_map(s, 0, addr); |
55d7bfe2 MCA |
494 | /* 2/STIP : Stipple */ |
495 | sysbus_mmio_map(s, 1, addr + 0x04000000ULL); | |
496 | /* 3/BLIT : Blitter */ | |
497 | sysbus_mmio_map(s, 2, addr + 0x06000000ULL); | |
498 | /* 5/RSTIP : Raw Stipple */ | |
499 | sysbus_mmio_map(s, 3, addr + 0x0c000000ULL); | |
500 | /* 6/RBLIT : Raw Blitter */ | |
501 | sysbus_mmio_map(s, 4, addr + 0x0e000000ULL); | |
502 | /* 7/TEC : Transform Engine */ | |
503 | sysbus_mmio_map(s, 5, addr + 0x00700000ULL); | |
504 | /* 8/CMAP : DAC */ | |
505 | sysbus_mmio_map(s, 6, addr + 0x00200000ULL); | |
506 | /* 9/THC : */ | |
507 | if (depth == 8) { | |
508 | sysbus_mmio_map(s, 7, addr + 0x00300000ULL); | |
4b48bf05 | 509 | } else { |
55d7bfe2 | 510 | sysbus_mmio_map(s, 7, addr + 0x00301000ULL); |
4b48bf05 | 511 | } |
55d7bfe2 MCA |
512 | /* 11/DHC : */ |
513 | sysbus_mmio_map(s, 8, addr + 0x00240000ULL); | |
514 | /* 12/ALT : */ | |
515 | sysbus_mmio_map(s, 9, addr + 0x00280000ULL); | |
516 | /* 0/DFB8 : 8-bit plane */ | |
517 | sysbus_mmio_map(s, 10, addr + 0x00800000ULL); | |
518 | /* 1/DFB24 : 24bit plane */ | |
519 | sysbus_mmio_map(s, 11, addr + 0x02000000ULL); | |
520 | /* 4/RDFB32: Raw framebuffer. Control plane */ | |
521 | sysbus_mmio_map(s, 12, addr + 0x0a000000ULL); | |
522 | /* 9/THC24bits : NetBSD writes here even with 8-bit display: dummy */ | |
523 | if (depth == 8) { | |
524 | sysbus_mmio_map(s, 13, addr + 0x00301000ULL); | |
525 | } | |
526 | ||
527 | sysbus_connect_irq(s, 0, irq); | |
4b48bf05 BS |
528 | } |
529 | ||
af87bf29 MCA |
530 | static void cg3_init(hwaddr addr, qemu_irq irq, int vram_size, int width, |
531 | int height, int depth) | |
532 | { | |
533 | DeviceState *dev; | |
534 | SysBusDevice *s; | |
535 | ||
536 | dev = qdev_create(NULL, "cgthree"); | |
537 | qdev_prop_set_uint32(dev, "vram-size", vram_size); | |
538 | qdev_prop_set_uint16(dev, "width", width); | |
539 | qdev_prop_set_uint16(dev, "height", height); | |
540 | qdev_prop_set_uint16(dev, "depth", depth); | |
af87bf29 MCA |
541 | qdev_init_nofail(dev); |
542 | s = SYS_BUS_DEVICE(dev); | |
543 | ||
544 | /* FCode ROM */ | |
545 | sysbus_mmio_map(s, 0, addr); | |
546 | /* DAC */ | |
547 | sysbus_mmio_map(s, 1, addr + 0x400000ULL); | |
548 | /* 8-bit plane */ | |
549 | sysbus_mmio_map(s, 2, addr + 0x800000ULL); | |
550 | ||
551 | sysbus_connect_irq(s, 0, irq); | |
552 | } | |
553 | ||
325f2747 | 554 | /* NCR89C100/MACIO Internal ID register */ |
ef9dfa4c AF |
555 | |
556 | #define TYPE_MACIO_ID_REGISTER "macio_idreg" | |
557 | ||
325f2747 BS |
558 | static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 }; |
559 | ||
a8170e5e | 560 | static void idreg_init(hwaddr addr) |
325f2747 BS |
561 | { |
562 | DeviceState *dev; | |
563 | SysBusDevice *s; | |
564 | ||
ef9dfa4c | 565 | dev = qdev_create(NULL, TYPE_MACIO_ID_REGISTER); |
e23a1b33 | 566 | qdev_init_nofail(dev); |
1356b98d | 567 | s = SYS_BUS_DEVICE(dev); |
325f2747 BS |
568 | |
569 | sysbus_mmio_map(s, 0, addr); | |
2a221651 EI |
570 | cpu_physical_memory_write_rom(&address_space_memory, |
571 | addr, idreg_data, sizeof(idreg_data)); | |
325f2747 BS |
572 | } |
573 | ||
ef9dfa4c AF |
574 | #define MACIO_ID_REGISTER(obj) \ |
575 | OBJECT_CHECK(IDRegState, (obj), TYPE_MACIO_ID_REGISTER) | |
576 | ||
3150fa50 | 577 | typedef struct IDRegState { |
ef9dfa4c AF |
578 | SysBusDevice parent_obj; |
579 | ||
3150fa50 AK |
580 | MemoryRegion mem; |
581 | } IDRegState; | |
582 | ||
dc8b6dd9 | 583 | static void idreg_init1(Object *obj) |
325f2747 | 584 | { |
dc8b6dd9 XZ |
585 | IDRegState *s = MACIO_ID_REGISTER(obj); |
586 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
325f2747 | 587 | |
1cfe48c1 | 588 | memory_region_init_ram_nomigrate(&s->mem, obj, |
f8ed85ac | 589 | "sun4m.idreg", sizeof(idreg_data), &error_fatal); |
c5705a77 | 590 | vmstate_register_ram_global(&s->mem); |
3150fa50 | 591 | memory_region_set_readonly(&s->mem, true); |
750ecd44 | 592 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
593 | } |
594 | ||
8c43a6f0 | 595 | static const TypeInfo idreg_info = { |
ef9dfa4c | 596 | .name = TYPE_MACIO_ID_REGISTER, |
39bffca2 AL |
597 | .parent = TYPE_SYS_BUS_DEVICE, |
598 | .instance_size = sizeof(IDRegState), | |
dc8b6dd9 | 599 | .instance_init = idreg_init1, |
325f2747 BS |
600 | }; |
601 | ||
b3a49965 AF |
602 | #define TYPE_TCX_AFX "tcx_afx" |
603 | #define TCX_AFX(obj) OBJECT_CHECK(AFXState, (obj), TYPE_TCX_AFX) | |
604 | ||
3150fa50 | 605 | typedef struct AFXState { |
b3a49965 AF |
606 | SysBusDevice parent_obj; |
607 | ||
3150fa50 AK |
608 | MemoryRegion mem; |
609 | } AFXState; | |
610 | ||
c5de386a | 611 | /* SS-5 TCX AFX register */ |
a8170e5e | 612 | static void afx_init(hwaddr addr) |
c5de386a AT |
613 | { |
614 | DeviceState *dev; | |
615 | SysBusDevice *s; | |
616 | ||
b3a49965 | 617 | dev = qdev_create(NULL, TYPE_TCX_AFX); |
c5de386a | 618 | qdev_init_nofail(dev); |
1356b98d | 619 | s = SYS_BUS_DEVICE(dev); |
c5de386a AT |
620 | |
621 | sysbus_mmio_map(s, 0, addr); | |
622 | } | |
623 | ||
dc8b6dd9 | 624 | static void afx_init1(Object *obj) |
c5de386a | 625 | { |
dc8b6dd9 XZ |
626 | AFXState *s = TCX_AFX(obj); |
627 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
c5de386a | 628 | |
1cfe48c1 | 629 | memory_region_init_ram_nomigrate(&s->mem, obj, "sun4m.afx", 4, &error_fatal); |
c5705a77 | 630 | vmstate_register_ram_global(&s->mem); |
750ecd44 | 631 | sysbus_init_mmio(dev, &s->mem); |
999e12bb AL |
632 | } |
633 | ||
8c43a6f0 | 634 | static const TypeInfo afx_info = { |
b3a49965 | 635 | .name = TYPE_TCX_AFX, |
39bffca2 AL |
636 | .parent = TYPE_SYS_BUS_DEVICE, |
637 | .instance_size = sizeof(AFXState), | |
dc8b6dd9 | 638 | .instance_init = afx_init1, |
c5de386a AT |
639 | }; |
640 | ||
e6f54c91 AF |
641 | #define TYPE_OPENPROM "openprom" |
642 | #define OPENPROM(obj) OBJECT_CHECK(PROMState, (obj), TYPE_OPENPROM) | |
643 | ||
3150fa50 | 644 | typedef struct PROMState { |
e6f54c91 AF |
645 | SysBusDevice parent_obj; |
646 | ||
3150fa50 AK |
647 | MemoryRegion prom; |
648 | } PROMState; | |
649 | ||
f48f6569 | 650 | /* Boot PROM (OpenBIOS) */ |
409dbce5 AJ |
651 | static uint64_t translate_prom_address(void *opaque, uint64_t addr) |
652 | { | |
a8170e5e | 653 | hwaddr *base_addr = (hwaddr *)opaque; |
409dbce5 AJ |
654 | return addr + *base_addr - PROM_VADDR; |
655 | } | |
656 | ||
a8170e5e | 657 | static void prom_init(hwaddr addr, const char *bios_name) |
f48f6569 BS |
658 | { |
659 | DeviceState *dev; | |
660 | SysBusDevice *s; | |
661 | char *filename; | |
662 | int ret; | |
663 | ||
e6f54c91 | 664 | dev = qdev_create(NULL, TYPE_OPENPROM); |
e23a1b33 | 665 | qdev_init_nofail(dev); |
1356b98d | 666 | s = SYS_BUS_DEVICE(dev); |
f48f6569 BS |
667 | |
668 | sysbus_mmio_map(s, 0, addr); | |
669 | ||
670 | /* load boot prom */ | |
671 | if (bios_name == NULL) { | |
672 | bios_name = PROM_FILENAME; | |
673 | } | |
674 | filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); | |
675 | if (filename) { | |
409dbce5 | 676 | ret = load_elf(filename, translate_prom_address, &addr, NULL, |
7ef295ea | 677 | NULL, NULL, 1, EM_SPARC, 0, 0); |
f48f6569 BS |
678 | if (ret < 0 || ret > PROM_SIZE_MAX) { |
679 | ret = load_image_targphys(filename, addr, PROM_SIZE_MAX); | |
680 | } | |
7267c094 | 681 | g_free(filename); |
f48f6569 BS |
682 | } else { |
683 | ret = -1; | |
684 | } | |
685 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
686 | fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name); | |
687 | exit(1); | |
688 | } | |
689 | } | |
690 | ||
dc8b6dd9 | 691 | static void prom_init1(Object *obj) |
f48f6569 | 692 | { |
dc8b6dd9 XZ |
693 | PROMState *s = OPENPROM(obj); |
694 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
f48f6569 | 695 | |
1cfe48c1 | 696 | memory_region_init_ram_nomigrate(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX, |
f8ed85ac | 697 | &error_fatal); |
c5705a77 | 698 | vmstate_register_ram_global(&s->prom); |
3150fa50 | 699 | memory_region_set_readonly(&s->prom, true); |
750ecd44 | 700 | sysbus_init_mmio(dev, &s->prom); |
f48f6569 BS |
701 | } |
702 | ||
999e12bb AL |
703 | static Property prom_properties[] = { |
704 | {/* end of property list */}, | |
705 | }; | |
706 | ||
707 | static void prom_class_init(ObjectClass *klass, void *data) | |
708 | { | |
39bffca2 | 709 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 710 | |
39bffca2 | 711 | dc->props = prom_properties; |
999e12bb AL |
712 | } |
713 | ||
8c43a6f0 | 714 | static const TypeInfo prom_info = { |
e6f54c91 | 715 | .name = TYPE_OPENPROM, |
39bffca2 AL |
716 | .parent = TYPE_SYS_BUS_DEVICE, |
717 | .instance_size = sizeof(PROMState), | |
718 | .class_init = prom_class_init, | |
dc8b6dd9 | 719 | .instance_init = prom_init1, |
f48f6569 BS |
720 | }; |
721 | ||
5ab6b4c6 AF |
722 | #define TYPE_SUN4M_MEMORY "memory" |
723 | #define SUN4M_RAM(obj) OBJECT_CHECK(RamDevice, (obj), TYPE_SUN4M_MEMORY) | |
724 | ||
725 | typedef struct RamDevice { | |
726 | SysBusDevice parent_obj; | |
727 | ||
3150fa50 | 728 | MemoryRegion ram; |
04843626 | 729 | uint64_t size; |
ee6847d1 GH |
730 | } RamDevice; |
731 | ||
a350db85 | 732 | /* System RAM */ |
dc8b6dd9 | 733 | static void ram_realize(DeviceState *dev, Error **errp) |
a350db85 | 734 | { |
5ab6b4c6 | 735 | RamDevice *d = SUN4M_RAM(dev); |
dc8b6dd9 | 736 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
a350db85 | 737 | |
8e7ba4ed DM |
738 | memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram", |
739 | d->size); | |
dc8b6dd9 | 740 | sysbus_init_mmio(sbd, &d->ram); |
a350db85 BS |
741 | } |
742 | ||
a8170e5e | 743 | static void ram_init(hwaddr addr, ram_addr_t RAM_size, |
a350db85 BS |
744 | uint64_t max_mem) |
745 | { | |
746 | DeviceState *dev; | |
747 | SysBusDevice *s; | |
ee6847d1 | 748 | RamDevice *d; |
a350db85 BS |
749 | |
750 | /* allocate RAM */ | |
751 | if ((uint64_t)RAM_size > max_mem) { | |
752 | fprintf(stderr, | |
753 | "qemu: Too much memory for this machine: %d, maximum %d\n", | |
754 | (unsigned int)(RAM_size / (1024 * 1024)), | |
755 | (unsigned int)(max_mem / (1024 * 1024))); | |
756 | exit(1); | |
757 | } | |
758 | dev = qdev_create(NULL, "memory"); | |
1356b98d | 759 | s = SYS_BUS_DEVICE(dev); |
a350db85 | 760 | |
5ab6b4c6 | 761 | d = SUN4M_RAM(dev); |
ee6847d1 | 762 | d->size = RAM_size; |
e23a1b33 | 763 | qdev_init_nofail(dev); |
ee6847d1 | 764 | |
a350db85 BS |
765 | sysbus_mmio_map(s, 0, addr); |
766 | } | |
767 | ||
999e12bb AL |
768 | static Property ram_properties[] = { |
769 | DEFINE_PROP_UINT64("size", RamDevice, size, 0), | |
770 | DEFINE_PROP_END_OF_LIST(), | |
771 | }; | |
772 | ||
773 | static void ram_class_init(ObjectClass *klass, void *data) | |
774 | { | |
39bffca2 | 775 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 776 | |
dc8b6dd9 | 777 | dc->realize = ram_realize; |
39bffca2 | 778 | dc->props = ram_properties; |
999e12bb AL |
779 | } |
780 | ||
8c43a6f0 | 781 | static const TypeInfo ram_info = { |
5ab6b4c6 | 782 | .name = TYPE_SUN4M_MEMORY, |
39bffca2 AL |
783 | .parent = TYPE_SYS_BUS_DEVICE, |
784 | .instance_size = sizeof(RamDevice), | |
785 | .class_init = ram_class_init, | |
a350db85 BS |
786 | }; |
787 | ||
49cbd887 | 788 | static void cpu_devinit(const char *cpu_type, unsigned int id, |
89835363 | 789 | uint64_t prom_addr, qemu_irq **cpu_irqs) |
666713c0 | 790 | { |
259186a7 | 791 | CPUState *cs; |
8968f588 | 792 | SPARCCPU *cpu; |
98cec4a2 | 793 | CPUSPARCState *env; |
666713c0 | 794 | |
49cbd887 | 795 | cpu = SPARC_CPU(cpu_create(cpu_type)); |
8968f588 | 796 | env = &cpu->env; |
666713c0 BS |
797 | |
798 | cpu_sparc_set_id(env, id); | |
799 | if (id == 0) { | |
5414dec6 | 800 | qemu_register_reset(main_cpu_reset, cpu); |
666713c0 | 801 | } else { |
5414dec6 | 802 | qemu_register_reset(secondary_cpu_reset, cpu); |
259186a7 AF |
803 | cs = CPU(cpu); |
804 | cs->halted = 1; | |
666713c0 | 805 | } |
e0bbf9b5 | 806 | *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, cpu, MAX_PILS); |
666713c0 | 807 | env->prom_addr = prom_addr; |
666713c0 BS |
808 | } |
809 | ||
acfbe712 BS |
810 | static void dummy_fdc_tc(void *opaque, int irq, int level) |
811 | { | |
812 | } | |
813 | ||
6b63ef4d | 814 | static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, |
3ef96221 | 815 | MachineState *machine) |
420557e8 | 816 | { |
61b97833 | 817 | DeviceState *slavio_intctl; |
713c45fa | 818 | unsigned int i; |
9540619d | 819 | void *iommu, *nvram; |
7f773ff5 | 820 | DeviceState *espdma, *esp, *ledma; |
9540619d MCA |
821 | SysBusDevice *sbd; |
822 | qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS]; | |
2582cfa0 | 823 | qemu_irq fdc_tc; |
5c6602c5 | 824 | unsigned long kernel_size; |
fd8014e1 | 825 | DriveInfo *fd[MAX_FD]; |
a88b362c | 826 | FWCfgState *fw_cfg; |
9a62fb24 | 827 | unsigned int num_vsimms; |
420557e8 | 828 | |
ba3c64fb FB |
829 | /* init CPUs */ |
830 | for(i = 0; i < smp_cpus; i++) { | |
49cbd887 | 831 | cpu_devinit(machine->cpu_type, i, hwdef->slavio_base, &cpu_irqs[i]); |
ba3c64fb | 832 | } |
b3a23197 BS |
833 | |
834 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
835 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
836 | ||
3ebf5aaf | 837 | |
3ebf5aaf | 838 | /* set up devices */ |
3ef96221 | 839 | ram_init(0, machine->ram_size, hwdef->max_mem); |
676d9b9b AT |
840 | /* models without ECC don't trap when missing ram is accessed */ |
841 | if (!hwdef->ecc_base) { | |
3ef96221 | 842 | empty_slot_init(machine->ram_size, hwdef->max_mem - machine->ram_size); |
676d9b9b | 843 | } |
a350db85 | 844 | |
f48f6569 BS |
845 | prom_init(hwdef->slavio_base, bios_name); |
846 | ||
d453c2c3 BS |
847 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
848 | hwdef->intctl_base + 0x10000ULL, | |
462eda24 | 849 | cpu_irqs); |
a1961a4b BS |
850 | |
851 | for (i = 0; i < 32; i++) { | |
d453c2c3 | 852 | slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i); |
a1961a4b BS |
853 | } |
854 | for (i = 0; i < MAX_CPUS; i++) { | |
d453c2c3 | 855 | slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i); |
a1961a4b | 856 | } |
b3a23197 | 857 | |
fe096129 | 858 | if (hwdef->idreg_base) { |
325f2747 | 859 | idreg_init(hwdef->idreg_base); |
4c2485de BS |
860 | } |
861 | ||
c5de386a AT |
862 | if (hwdef->afx_base) { |
863 | afx_init(hwdef->afx_base); | |
864 | } | |
865 | ||
ff403da6 | 866 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
c533e0b3 | 867 | slavio_irq[30]); |
ff403da6 | 868 | |
3386376c AT |
869 | if (hwdef->iommu_pad_base) { |
870 | /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased. | |
871 | Software shouldn't use aliased addresses, neither should it crash | |
872 | when does. Using empty_slot instead of aliasing can help with | |
873 | debugging such accesses */ | |
874 | empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len); | |
875 | } | |
876 | ||
9540619d MCA |
877 | espdma = sparc32_dma_init(hwdef->dma_base, iommu, 0); |
878 | sbd = SYS_BUS_DEVICE(espdma); | |
879 | sysbus_connect_irq(sbd, 0, slavio_irq[18]); | |
2d069bab | 880 | |
7f773ff5 MCA |
881 | esp = DEVICE(object_resolve_path_component(OBJECT(espdma), "esp")); |
882 | sbd = SYS_BUS_DEVICE(esp); | |
883 | sysbus_mmio_map(sbd, 0, hwdef->esp_base); | |
884 | sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(espdma, 0)); | |
885 | qdev_connect_gpio_out(espdma, 0, qdev_get_gpio_in(esp, 0)); | |
886 | qdev_connect_gpio_out(espdma, 1, qdev_get_gpio_in(esp, 1)); | |
887 | ||
9540619d MCA |
888 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, iommu, 1); |
889 | sbd = SYS_BUS_DEVICE(ledma); | |
890 | sysbus_connect_irq(sbd, 0, slavio_irq[16]); | |
ba3c64fb | 891 | |
eee0b836 | 892 | if (graphic_depth != 8 && graphic_depth != 24) { |
af87bf29 | 893 | error_report("Unsupported depth: %d", graphic_depth); |
eee0b836 BS |
894 | exit (1); |
895 | } | |
9a62fb24 BB |
896 | num_vsimms = 0; |
897 | if (num_vsimms == 0) { | |
af87bf29 MCA |
898 | if (vga_interface_type == VGA_CG3) { |
899 | if (graphic_depth != 8) { | |
900 | error_report("Unsupported depth: %d", graphic_depth); | |
901 | exit(1); | |
902 | } | |
903 | ||
904 | if (!(graphic_width == 1024 && graphic_height == 768) && | |
905 | !(graphic_width == 1152 && graphic_height == 900)) { | |
906 | error_report("Unsupported resolution: %d x %d", graphic_width, | |
907 | graphic_height); | |
908 | exit(1); | |
909 | } | |
910 | ||
911 | /* sbus irq 5 */ | |
912 | cg3_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, | |
913 | graphic_width, graphic_height, graphic_depth); | |
914 | } else { | |
915 | /* If no display specified, default to TCX */ | |
916 | if (graphic_depth != 8 && graphic_depth != 24) { | |
917 | error_report("Unsupported depth: %d", graphic_depth); | |
918 | exit(1); | |
919 | } | |
920 | ||
921 | if (!(graphic_width == 1024 && graphic_height == 768)) { | |
922 | error_report("Unsupported resolution: %d x %d", | |
923 | graphic_width, graphic_height); | |
924 | exit(1); | |
925 | } | |
926 | ||
55d7bfe2 MCA |
927 | tcx_init(hwdef->tcx_base, slavio_irq[11], 0x00100000, |
928 | graphic_width, graphic_height, graphic_depth); | |
af87bf29 | 929 | } |
9a62fb24 BB |
930 | } |
931 | ||
932 | for (i = num_vsimms; i < MAX_VSIMMS; i++) { | |
933 | /* vsimm registers probed by OBP */ | |
934 | if (hwdef->vsimm[i].reg_base) { | |
935 | empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000); | |
936 | } | |
937 | } | |
938 | ||
939 | if (hwdef->sx_base) { | |
940 | empty_slot_init(hwdef->sx_base, 0x2000); | |
941 | } | |
dbe06e18 | 942 | |
9540619d MCA |
943 | lance_init(&nd_table[0], hwdef->le_base, ledma, |
944 | qdev_get_gpio_in(ledma, 0)); | |
dbe06e18 | 945 | |
6de04973 | 946 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 1968, 8); |
81732d19 | 947 | |
c533e0b3 | 948 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus); |
81732d19 | 949 | |
c533e0b3 | 950 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14], |
cfc58cf3 | 951 | !machine->enable_graphics, ESCC_CLOCK, 1); |
5cbdb3a3 SW |
952 | /* Slavio TTYA (base+4, Linux ttyS0) is the first QEMU serial device |
953 | Slavio TTYB (base+0, Linux ttyS1) is the second QEMU serial device */ | |
c533e0b3 | 954 | escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15], |
aeeb69c7 | 955 | serial_hds[0], serial_hds[1], ESCC_CLOCK, 1); |
741402f9 | 956 | |
2582cfa0 | 957 | if (hwdef->apc_base) { |
ca43b97b | 958 | apc_init(hwdef->apc_base, qemu_allocate_irq(cpu_halt_signal, NULL, 0)); |
2582cfa0 | 959 | } |
2be17ebd | 960 | |
fe096129 | 961 | if (hwdef->fd_base) { |
e4bcb14c | 962 | /* there is zero or one floppy drive */ |
309e60bd | 963 | memset(fd, 0, sizeof(fd)); |
fd8014e1 | 964 | fd[0] = drive_get(IF_FLOPPY, 0, 0); |
c533e0b3 | 965 | sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd, |
2582cfa0 | 966 | &fdc_tc); |
acfbe712 | 967 | } else { |
ca43b97b | 968 | fdc_tc = qemu_allocate_irq(dummy_fdc_tc, NULL, 0); |
e4bcb14c TS |
969 | } |
970 | ||
acfbe712 BS |
971 | slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base, |
972 | slavio_irq[30], fdc_tc); | |
973 | ||
fa28ec52 BS |
974 | if (hwdef->cs_base) { |
975 | sysbus_create_simple("SUNW,CS4231", hwdef->cs_base, | |
c533e0b3 | 976 | slavio_irq[5]); |
fa28ec52 | 977 | } |
b3ceef24 | 978 | |
9a62fb24 BB |
979 | if (hwdef->dbri_base) { |
980 | /* ISDN chip with attached CS4215 audio codec */ | |
981 | /* prom space */ | |
982 | empty_slot_init(hwdef->dbri_base+0x1000, 0x30); | |
983 | /* reg space */ | |
984 | empty_slot_init(hwdef->dbri_base+0x10000, 0x100); | |
985 | } | |
986 | ||
987 | if (hwdef->bpp_base) { | |
988 | /* parallel port */ | |
989 | empty_slot_init(hwdef->bpp_base, 0x20); | |
990 | } | |
991 | ||
3ef96221 MA |
992 | kernel_size = sun4m_load_kernel(machine->kernel_filename, |
993 | machine->initrd_filename, | |
994 | machine->ram_size); | |
36cd9210 | 995 | |
3ef96221 MA |
996 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, machine->kernel_cmdline, |
997 | machine->boot_order, machine->ram_size, kernel_size, | |
998 | graphic_width, graphic_height, graphic_depth, | |
999 | hwdef->nvram_machine_id, "Sun4m"); | |
7eb0c8e8 | 1000 | |
fe096129 | 1001 | if (hwdef->ecc_base) |
c533e0b3 | 1002 | ecc_init(hwdef->ecc_base, slavio_irq[28], |
e42c20b4 | 1003 | hwdef->ecc_version); |
3cce6243 | 1004 | |
66708822 | 1005 | fw_cfg = fw_cfg_init_mem(CFG_ADDR, CFG_ADDR + 2); |
5836d168 | 1006 | fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)smp_cpus); |
70db9222 | 1007 | fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)max_cpus); |
905fdcb5 BS |
1008 | fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); |
1009 | fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id); | |
fbfcf955 | 1010 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth); |
b96919e0 MCA |
1011 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_WIDTH, graphic_width); |
1012 | fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_HEIGHT, graphic_height); | |
513f789f BS |
1013 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR); |
1014 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); | |
3ef96221 | 1015 | if (machine->kernel_cmdline) { |
513f789f | 1016 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR); |
6b63ef4d | 1017 | pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, |
3ef96221 MA |
1018 | machine->kernel_cmdline); |
1019 | fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline); | |
748a4ee3 | 1020 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, |
3ef96221 | 1021 | strlen(machine->kernel_cmdline) + 1); |
513f789f BS |
1022 | } else { |
1023 | fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0); | |
748a4ee3 | 1024 | fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0); |
513f789f BS |
1025 | } |
1026 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR); | |
1027 | fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used | |
3ef96221 | 1028 | fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_order[0]); |
513f789f | 1029 | qemu_register_boot_set(fw_cfg_boot_set, fw_cfg); |
36cd9210 BS |
1030 | } |
1031 | ||
905fdcb5 | 1032 | enum { |
905fdcb5 BS |
1033 | ss5_id = 32, |
1034 | vger_id, | |
1035 | lx_id, | |
1036 | ss4_id, | |
1037 | scls_id, | |
1038 | sbook_id, | |
1039 | ss10_id = 64, | |
1040 | ss20_id, | |
1041 | ss600mp_id, | |
905fdcb5 BS |
1042 | }; |
1043 | ||
8137cde8 | 1044 | static const struct sun4m_hwdef sun4m_hwdefs[] = { |
36cd9210 BS |
1045 | /* SS-5 */ |
1046 | { | |
1047 | .iommu_base = 0x10000000, | |
3386376c AT |
1048 | .iommu_pad_base = 0x10004000, |
1049 | .iommu_pad_len = 0x0fffb000, | |
36cd9210 BS |
1050 | .tcx_base = 0x50000000, |
1051 | .cs_base = 0x6c000000, | |
384ccb5d | 1052 | .slavio_base = 0x70000000, |
36cd9210 BS |
1053 | .ms_kb_base = 0x71000000, |
1054 | .serial_base = 0x71100000, | |
1055 | .nvram_base = 0x71200000, | |
1056 | .fd_base = 0x71400000, | |
1057 | .counter_base = 0x71d00000, | |
1058 | .intctl_base = 0x71e00000, | |
4c2485de | 1059 | .idreg_base = 0x78000000, |
36cd9210 BS |
1060 | .dma_base = 0x78400000, |
1061 | .esp_base = 0x78800000, | |
1062 | .le_base = 0x78c00000, | |
127fc407 | 1063 | .apc_base = 0x6a000000, |
c5de386a | 1064 | .afx_base = 0x6e000000, |
0019ad53 BS |
1065 | .aux1_base = 0x71900000, |
1066 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1067 | .nvram_machine_id = 0x80, |
1068 | .machine_id = ss5_id, | |
cf3102ac | 1069 | .iommu_version = 0x05000000, |
3ebf5aaf | 1070 | .max_mem = 0x10000000, |
e0353fe2 BS |
1071 | }, |
1072 | /* SS-10 */ | |
e0353fe2 | 1073 | { |
5dcb6b91 BS |
1074 | .iommu_base = 0xfe0000000ULL, |
1075 | .tcx_base = 0xe20000000ULL, | |
5dcb6b91 BS |
1076 | .slavio_base = 0xff0000000ULL, |
1077 | .ms_kb_base = 0xff1000000ULL, | |
1078 | .serial_base = 0xff1100000ULL, | |
1079 | .nvram_base = 0xff1200000ULL, | |
1080 | .fd_base = 0xff1700000ULL, | |
1081 | .counter_base = 0xff1300000ULL, | |
1082 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1083 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
1084 | .dma_base = 0xef0400000ULL, |
1085 | .esp_base = 0xef0800000ULL, | |
1086 | .le_base = 0xef0c00000ULL, | |
0019ad53 | 1087 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1088 | .aux1_base = 0xff1800000ULL, |
1089 | .aux2_base = 0xff1a01000ULL, | |
7eb0c8e8 BS |
1090 | .ecc_base = 0xf00000000ULL, |
1091 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
905fdcb5 BS |
1092 | .nvram_machine_id = 0x72, |
1093 | .machine_id = ss10_id, | |
7fbfb139 | 1094 | .iommu_version = 0x03000000, |
6ef05b95 | 1095 | .max_mem = 0xf00000000ULL, |
36cd9210 | 1096 | }, |
6a3b9cc9 BS |
1097 | /* SS-600MP */ |
1098 | { | |
1099 | .iommu_base = 0xfe0000000ULL, | |
1100 | .tcx_base = 0xe20000000ULL, | |
6a3b9cc9 BS |
1101 | .slavio_base = 0xff0000000ULL, |
1102 | .ms_kb_base = 0xff1000000ULL, | |
1103 | .serial_base = 0xff1100000ULL, | |
1104 | .nvram_base = 0xff1200000ULL, | |
6a3b9cc9 BS |
1105 | .counter_base = 0xff1300000ULL, |
1106 | .intctl_base = 0xff1400000ULL, | |
1107 | .dma_base = 0xef0081000ULL, | |
1108 | .esp_base = 0xef0080000ULL, | |
1109 | .le_base = 0xef0060000ULL, | |
0019ad53 | 1110 | .apc_base = 0xefa000000ULL, // XXX should not exist |
127fc407 BS |
1111 | .aux1_base = 0xff1800000ULL, |
1112 | .aux2_base = 0xff1a01000ULL, // XXX should not exist | |
7eb0c8e8 BS |
1113 | .ecc_base = 0xf00000000ULL, |
1114 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
905fdcb5 BS |
1115 | .nvram_machine_id = 0x71, |
1116 | .machine_id = ss600mp_id, | |
7fbfb139 | 1117 | .iommu_version = 0x01000000, |
6ef05b95 | 1118 | .max_mem = 0xf00000000ULL, |
6a3b9cc9 | 1119 | }, |
ae40972f BS |
1120 | /* SS-20 */ |
1121 | { | |
1122 | .iommu_base = 0xfe0000000ULL, | |
1123 | .tcx_base = 0xe20000000ULL, | |
ae40972f BS |
1124 | .slavio_base = 0xff0000000ULL, |
1125 | .ms_kb_base = 0xff1000000ULL, | |
1126 | .serial_base = 0xff1100000ULL, | |
1127 | .nvram_base = 0xff1200000ULL, | |
1128 | .fd_base = 0xff1700000ULL, | |
1129 | .counter_base = 0xff1300000ULL, | |
1130 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 1131 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
1132 | .dma_base = 0xef0400000ULL, |
1133 | .esp_base = 0xef0800000ULL, | |
1134 | .le_base = 0xef0c00000ULL, | |
9a62fb24 | 1135 | .bpp_base = 0xef4800000ULL, |
0019ad53 | 1136 | .apc_base = 0xefa000000ULL, // XXX should not exist |
577d8dd4 BS |
1137 | .aux1_base = 0xff1800000ULL, |
1138 | .aux2_base = 0xff1a01000ULL, | |
9a62fb24 BB |
1139 | .dbri_base = 0xee0000000ULL, |
1140 | .sx_base = 0xf80000000ULL, | |
1141 | .vsimm = { | |
1142 | { | |
1143 | .reg_base = 0x9c000000ULL, | |
1144 | .vram_base = 0xfc000000ULL | |
1145 | }, { | |
1146 | .reg_base = 0x90000000ULL, | |
1147 | .vram_base = 0xf0000000ULL | |
1148 | }, { | |
1149 | .reg_base = 0x94000000ULL | |
1150 | }, { | |
1151 | .reg_base = 0x98000000ULL | |
1152 | } | |
1153 | }, | |
ae40972f BS |
1154 | .ecc_base = 0xf00000000ULL, |
1155 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
905fdcb5 BS |
1156 | .nvram_machine_id = 0x72, |
1157 | .machine_id = ss20_id, | |
ae40972f | 1158 | .iommu_version = 0x13000000, |
6ef05b95 | 1159 | .max_mem = 0xf00000000ULL, |
ae40972f | 1160 | }, |
a526a31c BS |
1161 | /* Voyager */ |
1162 | { | |
1163 | .iommu_base = 0x10000000, | |
1164 | .tcx_base = 0x50000000, | |
a526a31c BS |
1165 | .slavio_base = 0x70000000, |
1166 | .ms_kb_base = 0x71000000, | |
1167 | .serial_base = 0x71100000, | |
1168 | .nvram_base = 0x71200000, | |
1169 | .fd_base = 0x71400000, | |
1170 | .counter_base = 0x71d00000, | |
1171 | .intctl_base = 0x71e00000, | |
1172 | .idreg_base = 0x78000000, | |
1173 | .dma_base = 0x78400000, | |
1174 | .esp_base = 0x78800000, | |
1175 | .le_base = 0x78c00000, | |
1176 | .apc_base = 0x71300000, // pmc | |
1177 | .aux1_base = 0x71900000, | |
1178 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1179 | .nvram_machine_id = 0x80, |
1180 | .machine_id = vger_id, | |
a526a31c | 1181 | .iommu_version = 0x05000000, |
a526a31c | 1182 | .max_mem = 0x10000000, |
a526a31c BS |
1183 | }, |
1184 | /* LX */ | |
1185 | { | |
1186 | .iommu_base = 0x10000000, | |
3386376c AT |
1187 | .iommu_pad_base = 0x10004000, |
1188 | .iommu_pad_len = 0x0fffb000, | |
a526a31c | 1189 | .tcx_base = 0x50000000, |
a526a31c BS |
1190 | .slavio_base = 0x70000000, |
1191 | .ms_kb_base = 0x71000000, | |
1192 | .serial_base = 0x71100000, | |
1193 | .nvram_base = 0x71200000, | |
1194 | .fd_base = 0x71400000, | |
1195 | .counter_base = 0x71d00000, | |
1196 | .intctl_base = 0x71e00000, | |
1197 | .idreg_base = 0x78000000, | |
1198 | .dma_base = 0x78400000, | |
1199 | .esp_base = 0x78800000, | |
1200 | .le_base = 0x78c00000, | |
a526a31c BS |
1201 | .aux1_base = 0x71900000, |
1202 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1203 | .nvram_machine_id = 0x80, |
1204 | .machine_id = lx_id, | |
a526a31c | 1205 | .iommu_version = 0x04000000, |
a526a31c | 1206 | .max_mem = 0x10000000, |
a526a31c BS |
1207 | }, |
1208 | /* SS-4 */ | |
1209 | { | |
1210 | .iommu_base = 0x10000000, | |
1211 | .tcx_base = 0x50000000, | |
1212 | .cs_base = 0x6c000000, | |
1213 | .slavio_base = 0x70000000, | |
1214 | .ms_kb_base = 0x71000000, | |
1215 | .serial_base = 0x71100000, | |
1216 | .nvram_base = 0x71200000, | |
1217 | .fd_base = 0x71400000, | |
1218 | .counter_base = 0x71d00000, | |
1219 | .intctl_base = 0x71e00000, | |
1220 | .idreg_base = 0x78000000, | |
1221 | .dma_base = 0x78400000, | |
1222 | .esp_base = 0x78800000, | |
1223 | .le_base = 0x78c00000, | |
1224 | .apc_base = 0x6a000000, | |
1225 | .aux1_base = 0x71900000, | |
1226 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1227 | .nvram_machine_id = 0x80, |
1228 | .machine_id = ss4_id, | |
a526a31c | 1229 | .iommu_version = 0x05000000, |
a526a31c | 1230 | .max_mem = 0x10000000, |
a526a31c BS |
1231 | }, |
1232 | /* SPARCClassic */ | |
1233 | { | |
1234 | .iommu_base = 0x10000000, | |
1235 | .tcx_base = 0x50000000, | |
a526a31c BS |
1236 | .slavio_base = 0x70000000, |
1237 | .ms_kb_base = 0x71000000, | |
1238 | .serial_base = 0x71100000, | |
1239 | .nvram_base = 0x71200000, | |
1240 | .fd_base = 0x71400000, | |
1241 | .counter_base = 0x71d00000, | |
1242 | .intctl_base = 0x71e00000, | |
1243 | .idreg_base = 0x78000000, | |
1244 | .dma_base = 0x78400000, | |
1245 | .esp_base = 0x78800000, | |
1246 | .le_base = 0x78c00000, | |
1247 | .apc_base = 0x6a000000, | |
1248 | .aux1_base = 0x71900000, | |
1249 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1250 | .nvram_machine_id = 0x80, |
1251 | .machine_id = scls_id, | |
a526a31c | 1252 | .iommu_version = 0x05000000, |
a526a31c | 1253 | .max_mem = 0x10000000, |
a526a31c BS |
1254 | }, |
1255 | /* SPARCbook */ | |
1256 | { | |
1257 | .iommu_base = 0x10000000, | |
1258 | .tcx_base = 0x50000000, // XXX | |
a526a31c BS |
1259 | .slavio_base = 0x70000000, |
1260 | .ms_kb_base = 0x71000000, | |
1261 | .serial_base = 0x71100000, | |
1262 | .nvram_base = 0x71200000, | |
1263 | .fd_base = 0x71400000, | |
1264 | .counter_base = 0x71d00000, | |
1265 | .intctl_base = 0x71e00000, | |
1266 | .idreg_base = 0x78000000, | |
1267 | .dma_base = 0x78400000, | |
1268 | .esp_base = 0x78800000, | |
1269 | .le_base = 0x78c00000, | |
1270 | .apc_base = 0x6a000000, | |
1271 | .aux1_base = 0x71900000, | |
1272 | .aux2_base = 0x71910000, | |
905fdcb5 BS |
1273 | .nvram_machine_id = 0x80, |
1274 | .machine_id = sbook_id, | |
a526a31c | 1275 | .iommu_version = 0x05000000, |
a526a31c | 1276 | .max_mem = 0x10000000, |
a526a31c | 1277 | }, |
36cd9210 BS |
1278 | }; |
1279 | ||
36cd9210 | 1280 | /* SPARCstation 5 hardware initialisation */ |
3ef96221 | 1281 | static void ss5_init(MachineState *machine) |
36cd9210 | 1282 | { |
3ef96221 | 1283 | sun4m_hw_init(&sun4m_hwdefs[0], machine); |
420557e8 | 1284 | } |
c0e564d5 | 1285 | |
e0353fe2 | 1286 | /* SPARCstation 10 hardware initialisation */ |
3ef96221 | 1287 | static void ss10_init(MachineState *machine) |
e0353fe2 | 1288 | { |
3ef96221 | 1289 | sun4m_hw_init(&sun4m_hwdefs[1], machine); |
e0353fe2 BS |
1290 | } |
1291 | ||
6a3b9cc9 | 1292 | /* SPARCserver 600MP hardware initialisation */ |
3ef96221 | 1293 | static void ss600mp_init(MachineState *machine) |
6a3b9cc9 | 1294 | { |
3ef96221 | 1295 | sun4m_hw_init(&sun4m_hwdefs[2], machine); |
6a3b9cc9 BS |
1296 | } |
1297 | ||
ae40972f | 1298 | /* SPARCstation 20 hardware initialisation */ |
3ef96221 | 1299 | static void ss20_init(MachineState *machine) |
ae40972f | 1300 | { |
3ef96221 | 1301 | sun4m_hw_init(&sun4m_hwdefs[3], machine); |
ee76f82e BS |
1302 | } |
1303 | ||
a526a31c | 1304 | /* SPARCstation Voyager hardware initialisation */ |
3ef96221 | 1305 | static void vger_init(MachineState *machine) |
a526a31c | 1306 | { |
3ef96221 | 1307 | sun4m_hw_init(&sun4m_hwdefs[4], machine); |
a526a31c BS |
1308 | } |
1309 | ||
1310 | /* SPARCstation LX hardware initialisation */ | |
3ef96221 | 1311 | static void ss_lx_init(MachineState *machine) |
a526a31c | 1312 | { |
3ef96221 | 1313 | sun4m_hw_init(&sun4m_hwdefs[5], machine); |
a526a31c BS |
1314 | } |
1315 | ||
1316 | /* SPARCstation 4 hardware initialisation */ | |
3ef96221 | 1317 | static void ss4_init(MachineState *machine) |
a526a31c | 1318 | { |
3ef96221 | 1319 | sun4m_hw_init(&sun4m_hwdefs[6], machine); |
a526a31c BS |
1320 | } |
1321 | ||
1322 | /* SPARCClassic hardware initialisation */ | |
3ef96221 | 1323 | static void scls_init(MachineState *machine) |
a526a31c | 1324 | { |
3ef96221 | 1325 | sun4m_hw_init(&sun4m_hwdefs[7], machine); |
a526a31c BS |
1326 | } |
1327 | ||
1328 | /* SPARCbook hardware initialisation */ | |
3ef96221 | 1329 | static void sbook_init(MachineState *machine) |
a526a31c | 1330 | { |
3ef96221 | 1331 | sun4m_hw_init(&sun4m_hwdefs[8], machine); |
a526a31c BS |
1332 | } |
1333 | ||
8a661aea | 1334 | static void ss5_class_init(ObjectClass *oc, void *data) |
e264d29d | 1335 | { |
8a661aea AF |
1336 | MachineClass *mc = MACHINE_CLASS(oc); |
1337 | ||
e264d29d EH |
1338 | mc->desc = "Sun4m platform, SPARCstation 5"; |
1339 | mc->init = ss5_init; | |
1340 | mc->block_default_type = IF_SCSI; | |
1341 | mc->is_default = 1; | |
1342 | mc->default_boot_order = "c"; | |
49cbd887 | 1343 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
e264d29d | 1344 | } |
e0353fe2 | 1345 | |
8a661aea AF |
1346 | static const TypeInfo ss5_type = { |
1347 | .name = MACHINE_TYPE_NAME("SS-5"), | |
1348 | .parent = TYPE_MACHINE, | |
1349 | .class_init = ss5_class_init, | |
1350 | }; | |
6a3b9cc9 | 1351 | |
8a661aea | 1352 | static void ss10_class_init(ObjectClass *oc, void *data) |
e264d29d | 1353 | { |
8a661aea AF |
1354 | MachineClass *mc = MACHINE_CLASS(oc); |
1355 | ||
e264d29d EH |
1356 | mc->desc = "Sun4m platform, SPARCstation 10"; |
1357 | mc->init = ss10_init; | |
1358 | mc->block_default_type = IF_SCSI; | |
1359 | mc->max_cpus = 4; | |
1360 | mc->default_boot_order = "c"; | |
49cbd887 | 1361 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
e264d29d | 1362 | } |
ae40972f | 1363 | |
8a661aea AF |
1364 | static const TypeInfo ss10_type = { |
1365 | .name = MACHINE_TYPE_NAME("SS-10"), | |
1366 | .parent = TYPE_MACHINE, | |
1367 | .class_init = ss10_class_init, | |
1368 | }; | |
ae40972f | 1369 | |
8a661aea | 1370 | static void ss600mp_class_init(ObjectClass *oc, void *data) |
e264d29d | 1371 | { |
8a661aea AF |
1372 | MachineClass *mc = MACHINE_CLASS(oc); |
1373 | ||
e264d29d EH |
1374 | mc->desc = "Sun4m platform, SPARCserver 600MP"; |
1375 | mc->init = ss600mp_init; | |
1376 | mc->block_default_type = IF_SCSI; | |
1377 | mc->max_cpus = 4; | |
1378 | mc->default_boot_order = "c"; | |
49cbd887 | 1379 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
e264d29d | 1380 | } |
a526a31c | 1381 | |
8a661aea AF |
1382 | static const TypeInfo ss600mp_type = { |
1383 | .name = MACHINE_TYPE_NAME("SS-600MP"), | |
1384 | .parent = TYPE_MACHINE, | |
1385 | .class_init = ss600mp_class_init, | |
1386 | }; | |
a526a31c | 1387 | |
8a661aea | 1388 | static void ss20_class_init(ObjectClass *oc, void *data) |
e264d29d | 1389 | { |
8a661aea AF |
1390 | MachineClass *mc = MACHINE_CLASS(oc); |
1391 | ||
e264d29d EH |
1392 | mc->desc = "Sun4m platform, SPARCstation 20"; |
1393 | mc->init = ss20_init; | |
1394 | mc->block_default_type = IF_SCSI; | |
1395 | mc->max_cpus = 4; | |
1396 | mc->default_boot_order = "c"; | |
49cbd887 | 1397 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-SuperSparc-II"); |
e264d29d | 1398 | } |
a526a31c | 1399 | |
8a661aea AF |
1400 | static const TypeInfo ss20_type = { |
1401 | .name = MACHINE_TYPE_NAME("SS-20"), | |
1402 | .parent = TYPE_MACHINE, | |
1403 | .class_init = ss20_class_init, | |
1404 | }; | |
a526a31c | 1405 | |
8a661aea | 1406 | static void voyager_class_init(ObjectClass *oc, void *data) |
e264d29d | 1407 | { |
8a661aea AF |
1408 | MachineClass *mc = MACHINE_CLASS(oc); |
1409 | ||
e264d29d EH |
1410 | mc->desc = "Sun4m platform, SPARCstation Voyager"; |
1411 | mc->init = vger_init; | |
1412 | mc->block_default_type = IF_SCSI; | |
1413 | mc->default_boot_order = "c"; | |
49cbd887 | 1414 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
e264d29d EH |
1415 | } |
1416 | ||
8a661aea AF |
1417 | static const TypeInfo voyager_type = { |
1418 | .name = MACHINE_TYPE_NAME("Voyager"), | |
1419 | .parent = TYPE_MACHINE, | |
1420 | .class_init = voyager_class_init, | |
1421 | }; | |
e264d29d | 1422 | |
8a661aea | 1423 | static void ss_lx_class_init(ObjectClass *oc, void *data) |
e264d29d | 1424 | { |
8a661aea AF |
1425 | MachineClass *mc = MACHINE_CLASS(oc); |
1426 | ||
e264d29d EH |
1427 | mc->desc = "Sun4m platform, SPARCstation LX"; |
1428 | mc->init = ss_lx_init; | |
1429 | mc->block_default_type = IF_SCSI; | |
1430 | mc->default_boot_order = "c"; | |
49cbd887 | 1431 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
e264d29d EH |
1432 | } |
1433 | ||
8a661aea AF |
1434 | static const TypeInfo ss_lx_type = { |
1435 | .name = MACHINE_TYPE_NAME("LX"), | |
1436 | .parent = TYPE_MACHINE, | |
1437 | .class_init = ss_lx_class_init, | |
1438 | }; | |
e264d29d | 1439 | |
8a661aea | 1440 | static void ss4_class_init(ObjectClass *oc, void *data) |
e264d29d | 1441 | { |
8a661aea AF |
1442 | MachineClass *mc = MACHINE_CLASS(oc); |
1443 | ||
e264d29d EH |
1444 | mc->desc = "Sun4m platform, SPARCstation 4"; |
1445 | mc->init = ss4_init; | |
1446 | mc->block_default_type = IF_SCSI; | |
1447 | mc->default_boot_order = "c"; | |
49cbd887 | 1448 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Fujitsu-MB86904"); |
e264d29d EH |
1449 | } |
1450 | ||
8a661aea AF |
1451 | static const TypeInfo ss4_type = { |
1452 | .name = MACHINE_TYPE_NAME("SS-4"), | |
1453 | .parent = TYPE_MACHINE, | |
1454 | .class_init = ss4_class_init, | |
1455 | }; | |
e264d29d | 1456 | |
8a661aea | 1457 | static void scls_class_init(ObjectClass *oc, void *data) |
e264d29d | 1458 | { |
8a661aea AF |
1459 | MachineClass *mc = MACHINE_CLASS(oc); |
1460 | ||
e264d29d EH |
1461 | mc->desc = "Sun4m platform, SPARCClassic"; |
1462 | mc->init = scls_init; | |
1463 | mc->block_default_type = IF_SCSI; | |
1464 | mc->default_boot_order = "c"; | |
49cbd887 | 1465 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
e264d29d EH |
1466 | } |
1467 | ||
8a661aea AF |
1468 | static const TypeInfo scls_type = { |
1469 | .name = MACHINE_TYPE_NAME("SPARCClassic"), | |
1470 | .parent = TYPE_MACHINE, | |
1471 | .class_init = scls_class_init, | |
1472 | }; | |
e264d29d | 1473 | |
8a661aea | 1474 | static void sbook_class_init(ObjectClass *oc, void *data) |
e264d29d | 1475 | { |
8a661aea AF |
1476 | MachineClass *mc = MACHINE_CLASS(oc); |
1477 | ||
e264d29d EH |
1478 | mc->desc = "Sun4m platform, SPARCbook"; |
1479 | mc->init = sbook_init; | |
1480 | mc->block_default_type = IF_SCSI; | |
1481 | mc->default_boot_order = "c"; | |
49cbd887 | 1482 | mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-MicroSparc-I"); |
e264d29d EH |
1483 | } |
1484 | ||
8a661aea AF |
1485 | static const TypeInfo sbook_type = { |
1486 | .name = MACHINE_TYPE_NAME("SPARCbook"), | |
1487 | .parent = TYPE_MACHINE, | |
1488 | .class_init = sbook_class_init, | |
1489 | }; | |
a526a31c | 1490 | |
83f7d43a AF |
1491 | static void sun4m_register_types(void) |
1492 | { | |
1493 | type_register_static(&idreg_info); | |
1494 | type_register_static(&afx_info); | |
1495 | type_register_static(&prom_info); | |
1496 | type_register_static(&ram_info); | |
83f7d43a | 1497 | |
8a661aea AF |
1498 | type_register_static(&ss5_type); |
1499 | type_register_static(&ss10_type); | |
1500 | type_register_static(&ss600mp_type); | |
1501 | type_register_static(&ss20_type); | |
1502 | type_register_static(&voyager_type); | |
1503 | type_register_static(&ss_lx_type); | |
1504 | type_register_static(&ss4_type); | |
1505 | type_register_static(&scls_type); | |
1506 | type_register_static(&sbook_type); | |
1507 | } | |
1508 | ||
83f7d43a | 1509 | type_init(sun4m_register_types) |