[mirror_qemu.git] / hw / sparc / sun4m_iommu.c

/*
 * QEMU Sun4m iommu emulation
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sparc/sun4m_iommu.h"
#include "hw/sysbus.h"
#include "qemu/module.h"
#include "exec/address-spaces.h"
#include "trace.h"

/*
 * I/O MMU used by Sun4m systems
 *
 * Chipset docs:
 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
 * http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
 */

#define IOMMU_CTRL          (0x0000 >> 2)
#define IOMMU_CTRL_IMPL     0xf0000000 /* Implementation */
#define IOMMU_CTRL_VERS     0x0f000000 /* Version */
#define IOMMU_CTRL_RNGE     0x0000001c /* Mapping RANGE */
#define IOMMU_RNGE_16MB     0x00000000 /* 0xff000000 -> 0xffffffff */
#define IOMMU_RNGE_32MB     0x00000004 /* 0xfe000000 -> 0xffffffff */
#define IOMMU_RNGE_64MB     0x00000008 /* 0xfc000000 -> 0xffffffff */
#define IOMMU_RNGE_128MB    0x0000000c /* 0xf8000000 -> 0xffffffff */
#define IOMMU_RNGE_256MB    0x00000010 /* 0xf0000000 -> 0xffffffff */
#define IOMMU_RNGE_512MB    0x00000014 /* 0xe0000000 -> 0xffffffff */
#define IOMMU_RNGE_1GB      0x00000018 /* 0xc0000000 -> 0xffffffff */
#define IOMMU_RNGE_2GB      0x0000001c /* 0x80000000 -> 0xffffffff */
#define IOMMU_CTRL_ENAB     0x00000001 /* IOMMU Enable */
#define IOMMU_CTRL_MASK     0x0000001d

#define IOMMU_BASE          (0x0004 >> 2)
#define IOMMU_BASE_MASK     0x07fffc00

#define IOMMU_TLBFLUSH      (0x0014 >> 2)
#define IOMMU_TLBFLUSH_MASK 0xffffffff

#define IOMMU_PGFLUSH       (0x0018 >> 2)
#define IOMMU_PGFLUSH_MASK  0xffffffff

#define IOMMU_AFSR          (0x1000 >> 2)
#define IOMMU_AFSR_ERR      0x80000000 /* LE, TO, or BE asserted */
#define IOMMU_AFSR_LE       0x40000000 /* SBUS reports error after
                                          transaction */
#define IOMMU_AFSR_TO       0x20000000 /* Write access took more than
                                          12.8 us. */
#define IOMMU_AFSR_BE       0x10000000 /* Write access received error
                                          acknowledge */
#define IOMMU_AFSR_SIZE     0x0e000000 /* Size of transaction causing error */
#define IOMMU_AFSR_S        0x01000000 /* Sparc was in supervisor mode */
#define IOMMU_AFSR_RESV     0x00800000 /* Reserved, forced to 0x8 by
                                          hardware */
#define IOMMU_AFSR_ME       0x00080000 /* Multiple errors occurred */
#define IOMMU_AFSR_RD       0x00040000 /* A read operation was in progress */
#define IOMMU_AFSR_FAV      0x00020000 /* IOMMU afar has valid contents */
#define IOMMU_AFSR_MASK     0xff0fffff

#define IOMMU_AFAR          (0x1004 >> 2)

#define IOMMU_AER           (0x1008 >> 2) /* Arbiter Enable Register */
#define IOMMU_AER_EN_P0_ARB 0x00000001    /* MBus master 0x8 (Always 1) */
#define IOMMU_AER_EN_P1_ARB 0x00000002    /* MBus master 0x9 */
#define IOMMU_AER_EN_P2_ARB 0x00000004    /* MBus master 0xa */
#define IOMMU_AER_EN_P3_ARB 0x00000008    /* MBus master 0xb */
#define IOMMU_AER_EN_0      0x00010000    /* SBus slot 0 */
#define IOMMU_AER_EN_1      0x00020000    /* SBus slot 1 */
#define IOMMU_AER_EN_2      0x00040000    /* SBus slot 2 */
#define IOMMU_AER_EN_3      0x00080000    /* SBus slot 3 */
#define IOMMU_AER_EN_F      0x00100000    /* SBus on-board */
#define IOMMU_AER_SBW       0x80000000    /* S-to-M asynchronous writes */
#define IOMMU_AER_MASK      0x801f000f

#define IOMMU_SBCFG0        (0x1010 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG1        (0x1014 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG2        (0x1018 >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG3        (0x101c >> 2) /* SBUS configration per-slot */
#define IOMMU_SBCFG_SAB30   0x00010000 /* Phys-address bit 30 when
                                          bypass enabled */
#define IOMMU_SBCFG_BA16    0x00000004 /* Slave supports 16 byte bursts */
#define IOMMU_SBCFG_BA8     0x00000002 /* Slave supports 8 byte bursts */
#define IOMMU_SBCFG_BYPASS  0x00000001 /* Bypass IOMMU, treat all addresses
                                          produced by this device as pure
                                          physical. */
#define IOMMU_SBCFG_MASK    0x00010003

#define IOMMU_ARBEN         (0x2000 >> 2) /* SBUS arbitration enable */
#define IOMMU_ARBEN_MASK    0x001f0000
#define IOMMU_MID           0x00000008

#define IOMMU_MASK_ID       (0x3018 >> 2) /* Mask ID */
#define IOMMU_MASK_ID_MASK  0x00ffffff

#define IOMMU_MSII_MASK     0x26000000 /* microSPARC II mask number */
#define IOMMU_TS_MASK       0x23000000 /* turboSPARC mask number */

/* The format of an iopte in the page tables */
#define IOPTE_PAGE          0xffffff00 /* Physical page number (PA[35:12]) */
#define IOPTE_CACHE         0x00000080 /* Cached (in vme IOCACHE or
                                          Viking/MXCC) */
#define IOPTE_WRITE         0x00000004 /* Writable */
#define IOPTE_VALID         0x00000002 /* IOPTE is valid */
#define IOPTE_WAZ           0x00000001 /* Write as zeros */

#define IOMMU_PAGE_SHIFT    12
#define IOMMU_PAGE_SIZE     (1 << IOMMU_PAGE_SHIFT)
#define IOMMU_PAGE_MASK     (~(IOMMU_PAGE_SIZE - 1))

static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
                               unsigned size)
{
    IOMMUState *s = opaque;
    hwaddr saddr;
    uint32_t ret;

    saddr = addr >> 2;
    switch (saddr) {
    default:
        ret = s->regs[saddr];
        break;
    case IOMMU_AFAR:
    case IOMMU_AFSR:
        ret = s->regs[saddr];
        qemu_irq_lower(s->irq);
        break;
    }
    trace_sun4m_iommu_mem_readl(saddr, ret);
    return ret;
}

static void iommu_mem_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned size)
{
    IOMMUState *s = opaque;
    hwaddr saddr;

    saddr = addr >> 2;
    trace_sun4m_iommu_mem_writel(saddr, val);
    switch (saddr) {
    case IOMMU_CTRL:
        switch (val & IOMMU_CTRL_RNGE) {
        case IOMMU_RNGE_16MB:
            s->iostart = 0xffffffffff000000ULL;
            break;
        case IOMMU_RNGE_32MB:
            s->iostart = 0xfffffffffe000000ULL;
            break;
        case IOMMU_RNGE_64MB:
            s->iostart = 0xfffffffffc000000ULL;
            break;
        case IOMMU_RNGE_128MB:
            s->iostart = 0xfffffffff8000000ULL;
            break;
        case IOMMU_RNGE_256MB:
            s->iostart = 0xfffffffff0000000ULL;
            break;
        case IOMMU_RNGE_512MB:
            s->iostart = 0xffffffffe0000000ULL;
            break;
        case IOMMU_RNGE_1GB:
            s->iostart = 0xffffffffc0000000ULL;
            break;
        default:
        case IOMMU_RNGE_2GB:
            s->iostart = 0xffffffff80000000ULL;
            break;
        }
        trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
        s->regs[saddr] = ((val & IOMMU_CTRL_MASK) | s->version);
        break;
    case IOMMU_BASE:
        s->regs[saddr] = val & IOMMU_BASE_MASK;
        break;
    case IOMMU_TLBFLUSH:
        trace_sun4m_iommu_mem_writel_tlbflush(val);
        s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
        break;
    case IOMMU_PGFLUSH:
        trace_sun4m_iommu_mem_writel_pgflush(val);
        s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
        break;
    case IOMMU_AFAR:
        s->regs[saddr] = val;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_AER:
        s->regs[saddr] = (val & IOMMU_AER_MASK) | IOMMU_AER_EN_P0_ARB;
        break;
    case IOMMU_AFSR:
        s->regs[saddr] = (val & IOMMU_AFSR_MASK) | IOMMU_AFSR_RESV;
        qemu_irq_lower(s->irq);
        break;
    case IOMMU_SBCFG0:
    case IOMMU_SBCFG1:
    case IOMMU_SBCFG2:
    case IOMMU_SBCFG3:
        s->regs[saddr] = val & IOMMU_SBCFG_MASK;
        break;
    case IOMMU_ARBEN:
        /* XXX implement SBus probing: fault when reading unmapped
           addresses, fault cause and address stored to MMU/IOMMU */
        s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID;
        break;
    case IOMMU_MASK_ID:
        s->regs[saddr] |= val & IOMMU_MASK_ID_MASK;
        break;
    default:
        s->regs[saddr] = val;
        break;
    }
}

static const MemoryRegionOps iommu_mem_ops = {
    .read = iommu_mem_read,
    .write = iommu_mem_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
{
    uint32_t ret;
    hwaddr iopte;
    hwaddr pa = addr;

    iopte = s->regs[IOMMU_BASE] << 4;
    addr &= ~s->iostart;
    iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
    ret = address_space_ldl_be(&address_space_memory, iopte,
                               MEMTXATTRS_UNSPECIFIED, NULL);
    trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
    return ret;
}

static hwaddr iommu_translate_pa(hwaddr addr,
                                             uint32_t pte)
{
    hwaddr pa;

    pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
    trace_sun4m_iommu_translate_pa(addr, pa, pte);
    return pa;
}

static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
                           int is_write)
{
    trace_sun4m_iommu_bad_addr(addr);
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR | IOMMU_AFSR_LE | IOMMU_AFSR_RESV |
        IOMMU_AFSR_FAV;
    if (!is_write) {
        s->regs[IOMMU_AFSR] |= IOMMU_AFSR_RD;
    }
    s->regs[IOMMU_AFAR] = addr;
    qemu_irq_raise(s->irq);
}

/* Called from RCU critical section */
static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,
                                           hwaddr addr,
                                           IOMMUAccessFlags flags,
                                           int iommu_idx)
{
    IOMMUState *is = container_of(iommu, IOMMUState, iommu);
    hwaddr page, pa;
    int is_write = (flags & IOMMU_WO) ? 1 : 0;
    uint32_t pte;
    IOMMUTLBEntry ret = {
        .target_as = &address_space_memory,
        .iova = 0,
        .translated_addr = 0,
        .addr_mask = ~(hwaddr)0,
        .perm = IOMMU_NONE,
    };

    page = addr & IOMMU_PAGE_MASK;
    pte = iommu_page_get_flags(is, page);
    if (!(pte & IOPTE_VALID)) {
        iommu_bad_addr(is, page, is_write);
        return ret;
    }

    pa = iommu_translate_pa(addr, pte);
    if (is_write && !(pte & IOPTE_WRITE)) {
        iommu_bad_addr(is, page, is_write);
        return ret;
    }

    if (pte & IOPTE_WRITE) {
        ret.perm = IOMMU_RW;
    } else {
        ret.perm = IOMMU_RO;
    }

    ret.iova = page;
    ret.translated_addr = pa;
    ret.addr_mask = ~IOMMU_PAGE_MASK;

    return ret;
}

static const VMStateDescription vmstate_iommu = {
    .name = "iommu",
    .version_id = 2,
    .minimum_version_id = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
        VMSTATE_UINT64(iostart, IOMMUState),
        VMSTATE_END_OF_LIST()
    }
};

static void iommu_reset(DeviceState *d)
{
    IOMMUState *s = SUN4M_IOMMU(d);

    memset(s->regs, 0, IOMMU_NREGS * 4);
    s->iostart = 0;
    s->regs[IOMMU_CTRL] = s->version;
    s->regs[IOMMU_ARBEN] = IOMMU_MID;
    s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
    s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB | IOMMU_AER_EN_P1_ARB;
    s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
}

static void iommu_init(Object *obj)
{
    IOMMUState *s = SUN4M_IOMMU(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
                             TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev),
                             "iommu-sun4m", UINT64_MAX);
    address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");

    sysbus_init_irq(dev, &s->irq);

    memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
                          IOMMU_NREGS * sizeof(uint32_t));
    sysbus_init_mmio(dev, &s->iomem);
}

static Property iommu_properties[] = {
    DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void iommu_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = iommu_reset;
    dc->vmsd = &vmstate_iommu;
    dc->props = iommu_properties;
}

static const TypeInfo iommu_info = {
    .name          = TYPE_SUN4M_IOMMU,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IOMMUState),
    .instance_init = iommu_init,
    .class_init    = iommu_class_init,
};

static void sun4m_iommu_memory_region_class_init(ObjectClass *klass, void *data)
{
    IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);

    imrc->translate = sun4m_translate_iommu;
}

static const TypeInfo sun4m_iommu_memory_region_info = {
    .parent = TYPE_IOMMU_MEMORY_REGION,
    .name = TYPE_SUN4M_IOMMU_MEMORY_REGION,
    .class_init = sun4m_iommu_memory_region_class_init,
};

static void iommu_register_types(void)
{
    type_register_static(&iommu_info);
    type_register_static(&sun4m_iommu_memory_region_info);
}

type_init(iommu_register_types)
Commit	Line	Data
420557e8	1	/*
93c5a32f	2	* QEMU Sun4m iommu emulation
420557e8	3	*
66321a11	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
5f750b2e	24
0430891c	25	#include "qemu/osdep.h"
1527f488	26	#include "hw/sparc/sun4m_iommu.h"
83c9f4ca	27	#include "hw/sysbus.h"
0b8fa32f	28	#include "qemu/module.h"
fdfba1a2	29	#include "exec/address-spaces.h"
97bf4851	30	#include "trace.h"
420557e8	31
93c5a32f BS	32	/*
	33	* I/O MMU used by Sun4m systems
	34	*
	35	* Chipset docs:
	36	* "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
	37	* http://mediacast.sun.com/users/Barton808/media/Sun4M_SystemArchitecture_edited2.pdf
	38	*/
	39
4e3b1ea1	40	#define IOMMU_CTRL (0x0000 >> 2)
420557e8 FB	41	#define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */
	42	#define IOMMU_CTRL_VERS 0x0f000000 /* Version */
	43	#define IOMMU_CTRL_RNGE 0x0000001c /* Mapping RANGE */
	44	#define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
	45	#define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
	46	#define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
	47	#define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
	48	#define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
	49	#define IOMMU_RNGE_512MB 0x00000014 /* 0xe0000000 -> 0xffffffff */
	50	#define IOMMU_RNGE_1GB 0x00000018 /* 0xc0000000 -> 0xffffffff */
	51	#define IOMMU_RNGE_2GB 0x0000001c /* 0x80000000 -> 0xffffffff */
	52	#define IOMMU_CTRL_ENAB 0x00000001 /* IOMMU Enable */
4e3b1ea1 FB	53	#define IOMMU_CTRL_MASK 0x0000001d
	54
	55	#define IOMMU_BASE (0x0004 >> 2)
	56	#define IOMMU_BASE_MASK 0x07fffc00
	57
	58	#define IOMMU_TLBFLUSH (0x0014 >> 2)
	59	#define IOMMU_TLBFLUSH_MASK 0xffffffff
	60
	61	#define IOMMU_PGFLUSH (0x0018 >> 2)
	62	#define IOMMU_PGFLUSH_MASK 0xffffffff
	63
225d4be7 BS	64	#define IOMMU_AFSR (0x1000 >> 2)
225d4be7 BS	65	#define IOMMU_AFSR_ERR 0x80000000 /* LE, TO, or BE asserted */
5ad6bb97 BS	66	#define IOMMU_AFSR_LE 0x40000000 /* SBUS reports error after
	67	transaction */
	68	#define IOMMU_AFSR_TO 0x20000000 /* Write access took more than
	69	12.8 us. */
	70	#define IOMMU_AFSR_BE 0x10000000 /* Write access received error
	71	acknowledge */
225d4be7 BS	72	#define IOMMU_AFSR_SIZE 0x0e000000 /* Size of transaction causing error */
225d4be7 BS	73	#define IOMMU_AFSR_S 0x01000000 /* Sparc was in supervisor mode */
5ad6bb97 BS	74	#define IOMMU_AFSR_RESV 0x00800000 /* Reserved, forced to 0x8 by
5ad6bb97 BS	75	hardware */
225d4be7 BS	76	#define IOMMU_AFSR_ME 0x00080000 /* Multiple errors occurred */
	77	#define IOMMU_AFSR_RD 0x00040000 /* A read operation was in progress */
	78	#define IOMMU_AFSR_FAV 0x00020000 /* IOMMU afar has valid contents */
c52428fc	79	#define IOMMU_AFSR_MASK 0xff0fffff
225d4be7 BS	80
	81	#define IOMMU_AFAR (0x1004 >> 2)
	82
7b169687 BS	83	#define IOMMU_AER (0x1008 >> 2) /* Arbiter Enable Register */
	84	#define IOMMU_AER_EN_P0_ARB 0x00000001 /* MBus master 0x8 (Always 1) */
	85	#define IOMMU_AER_EN_P1_ARB 0x00000002 /* MBus master 0x9 */
	86	#define IOMMU_AER_EN_P2_ARB 0x00000004 /* MBus master 0xa */
	87	#define IOMMU_AER_EN_P3_ARB 0x00000008 /* MBus master 0xb */
	88	#define IOMMU_AER_EN_0 0x00010000 /* SBus slot 0 */
	89	#define IOMMU_AER_EN_1 0x00020000 /* SBus slot 1 */
	90	#define IOMMU_AER_EN_2 0x00040000 /* SBus slot 2 */
	91	#define IOMMU_AER_EN_3 0x00080000 /* SBus slot 3 */
	92	#define IOMMU_AER_EN_F 0x00100000 /* SBus on-board */
	93	#define IOMMU_AER_SBW 0x80000000 /* S-to-M asynchronous writes */
	94	#define IOMMU_AER_MASK 0x801f000f
	95
4e3b1ea1 FB	96	#define IOMMU_SBCFG0 (0x1010 >> 2) /* SBUS configration per-slot */
	97	#define IOMMU_SBCFG1 (0x1014 >> 2) /* SBUS configration per-slot */
	98	#define IOMMU_SBCFG2 (0x1018 >> 2) /* SBUS configration per-slot */
	99	#define IOMMU_SBCFG3 (0x101c >> 2) /* SBUS configration per-slot */
5ad6bb97 BS	100	#define IOMMU_SBCFG_SAB30 0x00010000 /* Phys-address bit 30 when
5ad6bb97 BS	101	bypass enabled */
4e3b1ea1 FB	102	#define IOMMU_SBCFG_BA16 0x00000004 /* Slave supports 16 byte bursts */
	103	#define IOMMU_SBCFG_BA8 0x00000002 /* Slave supports 8 byte bursts */
	104	#define IOMMU_SBCFG_BYPASS 0x00000001 /* Bypass IOMMU, treat all addresses
f930d07e	105	produced by this device as pure
4e3b1ea1 FB	106	physical. */
	107	#define IOMMU_SBCFG_MASK 0x00010003
	108
	109	#define IOMMU_ARBEN (0x2000 >> 2) /* SBUS arbitration enable */
	110	#define IOMMU_ARBEN_MASK 0x001f0000
	111	#define IOMMU_MID 0x00000008
420557e8	112
e5e38121 BS	113	#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */
	114	#define IOMMU_MASK_ID_MASK 0x00ffffff
	115
	116	#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */
	117	#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */
	118
420557e8	119	/* The format of an iopte in the page tables */
498fbd8a	120	#define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */
5ad6bb97 BS	121	#define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or
5ad6bb97 BS	122	Viking/MXCC) */
ebabb67a	123	#define IOPTE_WRITE 0x00000004 /* Writable */
420557e8 FB	124	#define IOPTE_VALID 0x00000002 /* IOPTE is valid */
	125	#define IOPTE_WAZ 0x00000001 /* Write as zeros */
	126
8b0de438 BS	127	#define IOMMU_PAGE_SHIFT 12
8b0de438 BS	128	#define IOMMU_PAGE_SIZE (1 << IOMMU_PAGE_SHIFT)
ba51ef25	129	#define IOMMU_PAGE_MASK (~(IOMMU_PAGE_SIZE - 1))
420557e8	130
a8170e5e	131	static uint64_t iommu_mem_read(void *opaque, hwaddr addr,
d224136c	132	unsigned size)
420557e8 FB	133	{
420557e8 FB	134	IOMMUState *s = opaque;
a8170e5e	135	hwaddr saddr;
ff403da6	136	uint32_t ret;
420557e8	137
8da3ff18	138	saddr = addr >> 2;
420557e8 FB	139	switch (saddr) {
420557e8 FB	140	default:
ff403da6 BS	141	ret = s->regs[saddr];
	142	break;
	143	case IOMMU_AFAR:
	144	case IOMMU_AFSR:
	145	ret = s->regs[saddr];
	146	qemu_irq_lower(s->irq);
f930d07e	147	break;
420557e8	148	}
97bf4851	149	trace_sun4m_iommu_mem_readl(saddr, ret);
ff403da6	150	return ret;
420557e8 FB	151	}
420557e8 FB	152
a8170e5e	153	static void iommu_mem_write(void *opaque, hwaddr addr,
d224136c	154	uint64_t val, unsigned size)
420557e8 FB	155	{
420557e8 FB	156	IOMMUState *s = opaque;
a8170e5e	157	hwaddr saddr;
420557e8	158
8da3ff18	159	saddr = addr >> 2;
97bf4851	160	trace_sun4m_iommu_mem_writel(saddr, val);
420557e8	161	switch (saddr) {
4e3b1ea1	162	case IOMMU_CTRL:
f930d07e BS	163	switch (val & IOMMU_CTRL_RNGE) {
	164	case IOMMU_RNGE_16MB:
	165	s->iostart = 0xffffffffff000000ULL;
	166	break;
	167	case IOMMU_RNGE_32MB:
	168	s->iostart = 0xfffffffffe000000ULL;
	169	break;
	170	case IOMMU_RNGE_64MB:
	171	s->iostart = 0xfffffffffc000000ULL;
	172	break;
	173	case IOMMU_RNGE_128MB:
	174	s->iostart = 0xfffffffff8000000ULL;
	175	break;
	176	case IOMMU_RNGE_256MB:
	177	s->iostart = 0xfffffffff0000000ULL;
	178	break;
	179	case IOMMU_RNGE_512MB:
	180	s->iostart = 0xffffffffe0000000ULL;
	181	break;
	182	case IOMMU_RNGE_1GB:
	183	s->iostart = 0xffffffffc0000000ULL;
	184	break;
	185	default:
	186	case IOMMU_RNGE_2GB:
	187	s->iostart = 0xffffffff80000000ULL;
	188	break;
	189	}
97bf4851	190	trace_sun4m_iommu_mem_writel_ctrl(s->iostart);
7fbfb139	191	s->regs[saddr] = ((val & IOMMU_CTRL_MASK) \| s->version);
f930d07e	192	break;
4e3b1ea1	193	case IOMMU_BASE:
f930d07e BS	194	s->regs[saddr] = val & IOMMU_BASE_MASK;
f930d07e BS	195	break;
4e3b1ea1	196	case IOMMU_TLBFLUSH:
97bf4851	197	trace_sun4m_iommu_mem_writel_tlbflush(val);
f930d07e BS	198	s->regs[saddr] = val & IOMMU_TLBFLUSH_MASK;
f930d07e BS	199	break;
4e3b1ea1	200	case IOMMU_PGFLUSH:
97bf4851	201	trace_sun4m_iommu_mem_writel_pgflush(val);
f930d07e BS	202	s->regs[saddr] = val & IOMMU_PGFLUSH_MASK;
f930d07e BS	203	break;
ff403da6 BS	204	case IOMMU_AFAR:
	205	s->regs[saddr] = val;
	206	qemu_irq_lower(s->irq);
	207	break;
7b169687 BS	208	case IOMMU_AER:
	209	s->regs[saddr] = (val & IOMMU_AER_MASK) \| IOMMU_AER_EN_P0_ARB;
	210	break;
c52428fc BS	211	case IOMMU_AFSR:
c52428fc BS	212	s->regs[saddr] = (val & IOMMU_AFSR_MASK) \| IOMMU_AFSR_RESV;
ff403da6	213	qemu_irq_lower(s->irq);
c52428fc	214	break;
4e3b1ea1 FB	215	case IOMMU_SBCFG0:
	216	case IOMMU_SBCFG1:
	217	case IOMMU_SBCFG2:
	218	case IOMMU_SBCFG3:
f930d07e BS	219	s->regs[saddr] = val & IOMMU_SBCFG_MASK;
f930d07e BS	220	break;
4e3b1ea1	221	case IOMMU_ARBEN:
ba51ef25 MCA	222	/* XXX implement SBus probing: fault when reading unmapped
ba51ef25 MCA	223	addresses, fault cause and address stored to MMU/IOMMU */
f930d07e BS	224	s->regs[saddr] = (val & IOMMU_ARBEN_MASK) \| IOMMU_MID;
f930d07e BS	225	break;
e5e38121 BS	226	case IOMMU_MASK_ID:
	227	s->regs[saddr] \|= val & IOMMU_MASK_ID_MASK;
	228	break;
420557e8	229	default:
f930d07e BS	230	s->regs[saddr] = val;
f930d07e BS	231	break;
420557e8 FB	232	}
	233	}
	234
d224136c AK	235	static const MemoryRegionOps iommu_mem_ops = {
	236	.read = iommu_mem_read,
	237	.write = iommu_mem_write,
	238	.endianness = DEVICE_NATIVE_ENDIAN,
	239	.valid = {
	240	.min_access_size = 4,
	241	.max_access_size = 4,
	242	},
420557e8 FB	243	};
420557e8 FB	244
a8170e5e	245	static uint32_t iommu_page_get_flags(IOMMUState *s, hwaddr addr)
420557e8	246	{
5e3b100b	247	uint32_t ret;
a8170e5e AK	248	hwaddr iopte;
a8170e5e AK	249	hwaddr pa = addr;
420557e8	250
981a2e99	251	iopte = s->regs[IOMMU_BASE] << 4;
66321a11	252	addr &= ~s->iostart;
8b0de438	253	iopte += (addr >> (IOMMU_PAGE_SHIFT - 2)) & ~3;
42874d3a PM	254	ret = address_space_ldl_be(&address_space_memory, iopte,
42874d3a PM	255	MEMTXATTRS_UNSPECIFIED, NULL);
97bf4851	256	trace_sun4m_iommu_page_get_flags(pa, iopte, ret);
981a2e99	257	return ret;
a917d384 PB	258	}
a917d384 PB	259
a8170e5e	260	static hwaddr iommu_translate_pa(hwaddr addr,
5dcb6b91	261	uint32_t pte)
a917d384	262	{
a8170e5e	263	hwaddr pa;
5dcb6b91	264
8b0de438	265	pa = ((pte & IOPTE_PAGE) << 4) + (addr & ~IOMMU_PAGE_MASK);
97bf4851	266	trace_sun4m_iommu_translate_pa(addr, pa, pte);
66321a11	267	return pa;
420557e8 FB	268	}
420557e8 FB	269
a8170e5e	270	static void iommu_bad_addr(IOMMUState *s, hwaddr addr,
5ad6bb97	271	int is_write)
225d4be7	272	{
97bf4851	273	trace_sun4m_iommu_bad_addr(addr);
5ad6bb97	274	s->regs[IOMMU_AFSR] = IOMMU_AFSR_ERR \| IOMMU_AFSR_LE \| IOMMU_AFSR_RESV \|
225d4be7	275	IOMMU_AFSR_FAV;
ba51ef25	276	if (!is_write) {
225d4be7	277	s->regs[IOMMU_AFSR] \|= IOMMU_AFSR_RD;
ba51ef25	278	}
225d4be7	279	s->regs[IOMMU_AFAR] = addr;
ff403da6	280	qemu_irq_raise(s->irq);
225d4be7 BS	281	}
225d4be7 BS	282
84138466 MCA	283	/* Called from RCU critical section */
	284	static IOMMUTLBEntry sun4m_translate_iommu(IOMMUMemoryRegion *iommu,
	285	hwaddr addr,
2c91bcf2 PM	286	IOMMUAccessFlags flags,
2c91bcf2 PM	287	int iommu_idx)
84138466 MCA	288	{
	289	IOMMUState *is = container_of(iommu, IOMMUState, iommu);
	290	hwaddr page, pa;
	291	int is_write = (flags & IOMMU_WO) ? 1 : 0;
	292	uint32_t pte;
	293	IOMMUTLBEntry ret = {
	294	.target_as = &address_space_memory,
	295	.iova = 0,
	296	.translated_addr = 0,
	297	.addr_mask = ~(hwaddr)0,
	298	.perm = IOMMU_NONE,
	299	};
	300
	301	page = addr & IOMMU_PAGE_MASK;
	302	pte = iommu_page_get_flags(is, page);
	303	if (!(pte & IOPTE_VALID)) {
	304	iommu_bad_addr(is, page, is_write);
	305	return ret;
	306	}
	307
	308	pa = iommu_translate_pa(addr, pte);
	309	if (is_write && !(pte & IOPTE_WRITE)) {
	310	iommu_bad_addr(is, page, is_write);
	311	return ret;
	312	}
	313
	314	if (pte & IOPTE_WRITE) {
	315	ret.perm = IOMMU_RW;
	316	} else {
	317	ret.perm = IOMMU_RO;
	318	}
	319
	320	ret.iova = page;
	321	ret.translated_addr = pa;
	322	ret.addr_mask = ~IOMMU_PAGE_MASK;
	323
	324	return ret;
	325	}
	326
db3c9e08	327	static const VMStateDescription vmstate_iommu = {
ba51ef25	328	.name = "iommu",
db3c9e08 BS	329	.version_id = 2,
db3c9e08 BS	330	.minimum_version_id = 2,
35d08458	331	.fields = (VMStateField[]) {
db3c9e08 BS	332	VMSTATE_UINT32_ARRAY(regs, IOMMUState, IOMMU_NREGS),
	333	VMSTATE_UINT64(iostart, IOMMUState),
	334	VMSTATE_END_OF_LIST()
	335	}
	336	};
e80cfcfc	337
1a522e8a	338	static void iommu_reset(DeviceState *d)
e80cfcfc	339	{
049e7d22	340	IOMMUState *s = SUN4M_IOMMU(d);
e80cfcfc	341
66321a11	342	memset(s->regs, 0, IOMMU_NREGS * 4);
e80cfcfc	343	s->iostart = 0;
7fbfb139 BS	344	s->regs[IOMMU_CTRL] = s->version;
7fbfb139 BS	345	s->regs[IOMMU_ARBEN] = IOMMU_MID;
5ad6bb97	346	s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV;
7b169687	347	s->regs[IOMMU_AER] = IOMMU_AER_EN_P0_ARB \| IOMMU_AER_EN_P1_ARB;
e5e38121	348	s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
e80cfcfc FB	349	}
e80cfcfc FB	350
1c958ad3	351	static void iommu_init(Object *obj)
5f750b2e	352	{
1c958ad3 XZ	353	IOMMUState *s = SUN4M_IOMMU(obj);
1c958ad3 XZ	354	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
420557e8	355
84138466 MCA	356	memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
	357	TYPE_SUN4M_IOMMU_MEMORY_REGION, OBJECT(dev),
	358	"iommu-sun4m", UINT64_MAX);
	359	address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
	360
5f750b2e	361	sysbus_init_irq(dev, &s->irq);
420557e8	362
1c958ad3	363	memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
d224136c	364	IOMMU_NREGS * sizeof(uint32_t));
750ecd44	365	sysbus_init_mmio(dev, &s->iomem);
420557e8	366	}
5f750b2e	367
999e12bb	368	static Property iommu_properties[] = {
c7bcc85d	369	DEFINE_PROP_UINT32("version", IOMMUState, version, 0),
999e12bb AL	370	DEFINE_PROP_END_OF_LIST(),
	371	};
	372
	373	static void iommu_class_init(ObjectClass klass, void data)
	374	{
39bffca2	375	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	376
39bffca2 AL	377	dc->reset = iommu_reset;
	378	dc->vmsd = &vmstate_iommu;
	379	dc->props = iommu_properties;
999e12bb AL	380	}
999e12bb AL	381
8c43a6f0	382	static const TypeInfo iommu_info = {
049e7d22	383	.name = TYPE_SUN4M_IOMMU,
39bffca2 AL	384	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	385	.instance_size = sizeof(IOMMUState),
1c958ad3	386	.instance_init = iommu_init,
39bffca2	387	.class_init = iommu_class_init,
5f750b2e BS	388	};
5f750b2e BS	389
84138466 MCA	390	static void sun4m_iommu_memory_region_class_init(ObjectClass klass, void data)
	391	{
	392	IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
	393
	394	imrc->translate = sun4m_translate_iommu;
	395	}
	396
	397	static const TypeInfo sun4m_iommu_memory_region_info = {
	398	.parent = TYPE_IOMMU_MEMORY_REGION,
	399	.name = TYPE_SUN4M_IOMMU_MEMORY_REGION,
	400	.class_init = sun4m_iommu_memory_region_class_init,
	401	};
	402
83f7d43a	403	static void iommu_register_types(void)
5f750b2e	404	{
39bffca2	405	type_register_static(&iommu_info);
84138466	406	type_register_static(&sun4m_iommu_memory_region_info);
5f750b2e BS	407	}
5f750b2e BS	408
83f7d43a	409	type_init(iommu_register_types)