[mirror_qemu.git] / hw / sparc64 / sun4u_iommu.c

/*
 * QEMU sun4u IOMMU emulation
 *
 * Copyright (c) 2006 Fabrice Bellard
 * Copyright (c) 2012,2013 Artyom Tarasenko
 * Copyright (c) 2017 Mark Cave-Ayland
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/sparc/sun4u_iommu.h"
#include "exec/address-spaces.h"
#include "qemu/log.h"
#include "trace.h"


#define IOMMU_PAGE_SIZE_8K      (1ULL << 13)
#define IOMMU_PAGE_MASK_8K      (~(IOMMU_PAGE_SIZE_8K - 1))
#define IOMMU_PAGE_SIZE_64K     (1ULL << 16)
#define IOMMU_PAGE_MASK_64K     (~(IOMMU_PAGE_SIZE_64K - 1))

#define IOMMU_CTRL              0x0
#define IOMMU_CTRL_TBW_SIZE     (1ULL << 2)
#define IOMMU_CTRL_MMU_EN       (1ULL)

#define IOMMU_CTRL_TSB_SHIFT    16

#define IOMMU_BASE              0x8
#define IOMMU_FLUSH             0x10

#define IOMMU_TTE_DATA_V        (1ULL << 63)
#define IOMMU_TTE_DATA_SIZE     (1ULL << 61)
#define IOMMU_TTE_DATA_W        (1ULL << 1)

#define IOMMU_TTE_PHYS_MASK_8K  0x1ffffffe000ULL
#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL

#define IOMMU_TSB_8K_OFFSET_MASK_8M    0x00000000007fe000ULL
#define IOMMU_TSB_8K_OFFSET_MASK_16M   0x0000000000ffe000ULL
#define IOMMU_TSB_8K_OFFSET_MASK_32M   0x0000000001ffe000ULL
#define IOMMU_TSB_8K_OFFSET_MASK_64M   0x0000000003ffe000ULL
#define IOMMU_TSB_8K_OFFSET_MASK_128M  0x0000000007ffe000ULL
#define IOMMU_TSB_8K_OFFSET_MASK_256M  0x000000000fffe000ULL
#define IOMMU_TSB_8K_OFFSET_MASK_512M  0x000000001fffe000ULL
#define IOMMU_TSB_8K_OFFSET_MASK_1G    0x000000003fffe000ULL

#define IOMMU_TSB_64K_OFFSET_MASK_64M  0x0000000003ff0000ULL
#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
#define IOMMU_TSB_64K_OFFSET_MASK_1G   0x000000003fff0000ULL
#define IOMMU_TSB_64K_OFFSET_MASK_2G   0x000000007fff0000ULL


/* Called from RCU critical section */
static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu,
                                           hwaddr addr,
                                           IOMMUAccessFlags flag)
{
    IOMMUState *is = container_of(iommu, IOMMUState, iommu);
    hwaddr baseaddr, offset;
    uint64_t tte;
    uint32_t tsbsize;
    IOMMUTLBEntry ret = {
        .target_as = &address_space_memory,
        .iova = 0,
        .translated_addr = 0,
        .addr_mask = ~(hwaddr)0,
        .perm = IOMMU_NONE,
    };

    if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
        /* IOMMU disabled, passthrough using standard 8K page */
        ret.iova = addr & IOMMU_PAGE_MASK_8K;
        ret.translated_addr = addr;
        ret.addr_mask = IOMMU_PAGE_MASK_8K;
        ret.perm = IOMMU_RW;

        return ret;
    }

    baseaddr = is->regs[IOMMU_BASE >> 3];
    tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;

    if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
        /* 64K */
        switch (tsbsize) {
        case 0:
            offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
            break;
        case 1:
            offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
            break;
        case 2:
            offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
            break;
        case 3:
            offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
            break;
        case 4:
            offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
            break;
        case 5:
            offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
            break;
        default:
            /* Not implemented, error */
            return ret;
        }
    } else {
        /* 8K */
        switch (tsbsize) {
        case 0:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
            break;
        case 1:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
            break;
        case 2:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
            break;
        case 3:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
            break;
        case 4:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
            break;
        case 5:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
            break;
        case 6:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
            break;
        case 7:
            offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
            break;
        }
    }

    tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
                               MEMTXATTRS_UNSPECIFIED, NULL);

    if (!(tte & IOMMU_TTE_DATA_V)) {
        /* Invalid mapping */
        return ret;
    }

    if (tte & IOMMU_TTE_DATA_W) {
        /* Writeable */
        ret.perm = IOMMU_RW;
    } else {
        ret.perm = IOMMU_RO;
    }

    /* Extract phys */
    if (tte & IOMMU_TTE_DATA_SIZE) {
        /* 64K */
        ret.iova = addr & IOMMU_PAGE_MASK_64K;
        ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
        ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
    } else {
        /* 8K */
        ret.iova = addr & IOMMU_PAGE_MASK_8K;
        ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
        ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
    }

    trace_sun4u_iommu_translate(ret.iova, ret.translated_addr, tte);

    return ret;
}

static void iommu_mem_write(void *opaque, hwaddr addr,
                            uint64_t val, unsigned size)
{
    IOMMUState *is = opaque;

    trace_sun4u_iommu_mem_write(addr, val, size);

    switch (addr) {
    case IOMMU_CTRL:
        if (size == 4) {
            is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
            is->regs[IOMMU_CTRL >> 3] |= val << 32;
        } else {
            is->regs[IOMMU_CTRL >> 3] = val;
        }
        break;
    case IOMMU_CTRL + 0x4:
        is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
        is->regs[IOMMU_CTRL >> 3] |= val & 0xffffffffULL;
        break;
    case IOMMU_BASE:
        if (size == 4) {
            is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
            is->regs[IOMMU_BASE >> 3] |= val << 32;
        } else {
            is->regs[IOMMU_BASE >> 3] = val;
        }
        break;
    case IOMMU_BASE + 0x4:
        is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
        is->regs[IOMMU_BASE >> 3] |= val & 0xffffffffULL;
        break;
    case IOMMU_FLUSH:
    case IOMMU_FLUSH + 0x4:
        break;
    default:
        qemu_log_mask(LOG_UNIMP,
                  "sun4u-iommu: Unimplemented register write "
                  "reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
                  addr, size, val);
        break;
    }
}

static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size)
{
    IOMMUState *is = opaque;
    uint64_t val;

    switch (addr) {
    case IOMMU_CTRL:
        if (size == 4) {
            val = is->regs[IOMMU_CTRL >> 3] >> 32;
        } else {
            val = is->regs[IOMMU_CTRL >> 3];
        }
        break;
    case IOMMU_CTRL + 0x4:
        val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
        break;
    case IOMMU_BASE:
        if (size == 4) {
            val = is->regs[IOMMU_BASE >> 3] >> 32;
        } else {
            val = is->regs[IOMMU_BASE >> 3];
        }
        break;
    case IOMMU_BASE + 0x4:
        val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
        break;
    case IOMMU_FLUSH:
    case IOMMU_FLUSH + 0x4:
        val = 0;
        break;
    default:
        qemu_log_mask(LOG_UNIMP,
                      "sun4u-iommu: Unimplemented register read "
                      "reg 0x%" HWADDR_PRIx " size 0x%x\n",
                      addr, size);
        val = 0;
        break;
    }

    trace_sun4u_iommu_mem_read(addr, val, size);

    return val;
}

static const MemoryRegionOps iommu_mem_ops = {
    .read = iommu_mem_read,
    .write = iommu_mem_write,
    .endianness = DEVICE_BIG_ENDIAN,
};

static void iommu_reset(DeviceState *d)
{
    IOMMUState *s = SUN4U_IOMMU(d);

    memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t));
}

static void iommu_init(Object *obj)
{
    IOMMUState *s = SUN4U_IOMMU(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
                             TYPE_SUN4U_IOMMU_MEMORY_REGION, OBJECT(s),
                             "iommu-sun4u", UINT64_MAX);
    address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");

    memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
                          IOMMU_NREGS * sizeof(uint64_t));
    sysbus_init_mmio(sbd, &s->iomem);
}

static void iommu_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = iommu_reset;
}

static const TypeInfo iommu_info = {
    .name          = TYPE_SUN4U_IOMMU,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(IOMMUState),
    .instance_init = iommu_init,
    .class_init    = iommu_class_init,
};

static void sun4u_iommu_memory_region_class_init(ObjectClass *klass, void *data)
{
    IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);

    imrc->translate = sun4u_translate_iommu;
}

static const TypeInfo sun4u_iommu_memory_region_info = {
    .parent = TYPE_IOMMU_MEMORY_REGION,
    .name = TYPE_SUN4U_IOMMU_MEMORY_REGION,
    .class_init = sun4u_iommu_memory_region_class_init,
};

static void iommu_register_types(void)
{
    type_register_static(&iommu_info);
    type_register_static(&sun4u_iommu_memory_region_info);
}

type_init(iommu_register_types)
Commit	Line	Data
0ea833c2 MCA	1	/*
	2	* QEMU sun4u IOMMU emulation
	3	*
	4	* Copyright (c) 2006 Fabrice Bellard
	5	* Copyright (c) 2012,2013 Artyom Tarasenko
	6	* Copyright (c) 2017 Mark Cave-Ayland
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a copy
	9	* of this software and associated documentation files (the "Software"), to deal
	10	* in the Software without restriction, including without limitation the rights
	11	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	12	* copies of the Software, and to permit persons to whom the Software is
	13	* furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	21	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	23	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	24	* THE SOFTWARE.
	25	*/
	26
	27	#include "qemu/osdep.h"
	28	#include "hw/sysbus.h"
	29	#include "hw/sparc/sun4u_iommu.h"
	30	#include "exec/address-spaces.h"
0ea833c2	31	#include "qemu/log.h"
09ecbb78	32	#include "trace.h"
0ea833c2 MCA	33
	34
	35	#define IOMMU_PAGE_SIZE_8K (1ULL << 13)
	36	#define IOMMU_PAGE_MASK_8K (~(IOMMU_PAGE_SIZE_8K - 1))
	37	#define IOMMU_PAGE_SIZE_64K (1ULL << 16)
	38	#define IOMMU_PAGE_MASK_64K (~(IOMMU_PAGE_SIZE_64K - 1))
	39
	40	#define IOMMU_CTRL 0x0
	41	#define IOMMU_CTRL_TBW_SIZE (1ULL << 2)
	42	#define IOMMU_CTRL_MMU_EN (1ULL)
	43
	44	#define IOMMU_CTRL_TSB_SHIFT 16
	45
	46	#define IOMMU_BASE 0x8
	47	#define IOMMU_FLUSH 0x10
	48
	49	#define IOMMU_TTE_DATA_V (1ULL << 63)
	50	#define IOMMU_TTE_DATA_SIZE (1ULL << 61)
	51	#define IOMMU_TTE_DATA_W (1ULL << 1)
	52
	53	#define IOMMU_TTE_PHYS_MASK_8K 0x1ffffffe000ULL
	54	#define IOMMU_TTE_PHYS_MASK_64K 0x1ffffff8000ULL
	55
	56	#define IOMMU_TSB_8K_OFFSET_MASK_8M 0x00000000007fe000ULL
	57	#define IOMMU_TSB_8K_OFFSET_MASK_16M 0x0000000000ffe000ULL
	58	#define IOMMU_TSB_8K_OFFSET_MASK_32M 0x0000000001ffe000ULL
	59	#define IOMMU_TSB_8K_OFFSET_MASK_64M 0x0000000003ffe000ULL
	60	#define IOMMU_TSB_8K_OFFSET_MASK_128M 0x0000000007ffe000ULL
	61	#define IOMMU_TSB_8K_OFFSET_MASK_256M 0x000000000fffe000ULL
	62	#define IOMMU_TSB_8K_OFFSET_MASK_512M 0x000000001fffe000ULL
	63	#define IOMMU_TSB_8K_OFFSET_MASK_1G 0x000000003fffe000ULL
	64
	65	#define IOMMU_TSB_64K_OFFSET_MASK_64M 0x0000000003ff0000ULL
	66	#define IOMMU_TSB_64K_OFFSET_MASK_128M 0x0000000007ff0000ULL
	67	#define IOMMU_TSB_64K_OFFSET_MASK_256M 0x000000000fff0000ULL
	68	#define IOMMU_TSB_64K_OFFSET_MASK_512M 0x000000001fff0000ULL
	69	#define IOMMU_TSB_64K_OFFSET_MASK_1G 0x000000003fff0000ULL
	70	#define IOMMU_TSB_64K_OFFSET_MASK_2G 0x000000007fff0000ULL
	71
	72
	73	/* Called from RCU critical section */
4c9fbc38 MCA	74	static IOMMUTLBEntry sun4u_translate_iommu(IOMMUMemoryRegion *iommu,
	75	hwaddr addr,
	76	IOMMUAccessFlags flag)
0ea833c2 MCA	77	{
	78	IOMMUState *is = container_of(iommu, IOMMUState, iommu);
	79	hwaddr baseaddr, offset;
	80	uint64_t tte;
	81	uint32_t tsbsize;
	82	IOMMUTLBEntry ret = {
	83	.target_as = &address_space_memory,
	84	.iova = 0,
	85	.translated_addr = 0,
	86	.addr_mask = ~(hwaddr)0,
	87	.perm = IOMMU_NONE,
	88	};
	89
	90	if (!(is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_MMU_EN)) {
	91	/* IOMMU disabled, passthrough using standard 8K page */
	92	ret.iova = addr & IOMMU_PAGE_MASK_8K;
	93	ret.translated_addr = addr;
	94	ret.addr_mask = IOMMU_PAGE_MASK_8K;
	95	ret.perm = IOMMU_RW;
	96
	97	return ret;
	98	}
	99
	100	baseaddr = is->regs[IOMMU_BASE >> 3];
	101	tsbsize = (is->regs[IOMMU_CTRL >> 3] >> IOMMU_CTRL_TSB_SHIFT) & 0x7;
	102
	103	if (is->regs[IOMMU_CTRL >> 3] & IOMMU_CTRL_TBW_SIZE) {
	104	/* 64K */
	105	switch (tsbsize) {
	106	case 0:
	107	offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_64M) >> 13;
	108	break;
	109	case 1:
	110	offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_128M) >> 13;
	111	break;
	112	case 2:
	113	offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_256M) >> 13;
	114	break;
	115	case 3:
	116	offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_512M) >> 13;
	117	break;
	118	case 4:
	119	offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_1G) >> 13;
	120	break;
	121	case 5:
	122	offset = (addr & IOMMU_TSB_64K_OFFSET_MASK_2G) >> 13;
	123	break;
	124	default:
	125	/* Not implemented, error */
	126	return ret;
	127	}
	128	} else {
	129	/* 8K */
	130	switch (tsbsize) {
	131	case 0:
	132	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_8M) >> 10;
	133	break;
	134	case 1:
	135	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_16M) >> 10;
	136	break;
	137	case 2:
	138	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_32M) >> 10;
	139	break;
	140	case 3:
141	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_64M) >> 10;
142	break;
143	case 4:
144	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_128M) >> 10;
145	break;
146	case 5:
147	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_256M) >> 10;
148	break;
149	case 6:
150	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_512M) >> 10;
151	break;
152	case 7:
153	offset = (addr & IOMMU_TSB_8K_OFFSET_MASK_1G) >> 10;
154	break;
155	}
156	}
157
158	tte = address_space_ldq_be(&address_space_memory, baseaddr + offset,
159	MEMTXATTRS_UNSPECIFIED, NULL);
160
161	if (!(tte & IOMMU_TTE_DATA_V)) {
162	/* Invalid mapping */
163	return ret;
164	}
165
166	if (tte & IOMMU_TTE_DATA_W) {
167	/* Writeable */
168	ret.perm = IOMMU_RW;
169	} else {
170	ret.perm = IOMMU_RO;
171	}
172
173	/* Extract phys */
174	if (tte & IOMMU_TTE_DATA_SIZE) {
175	/* 64K */
176	ret.iova = addr & IOMMU_PAGE_MASK_64K;
177	ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_64K;
178	ret.addr_mask = (IOMMU_PAGE_SIZE_64K - 1);
179	} else {
180	/* 8K */
181	ret.iova = addr & IOMMU_PAGE_MASK_8K;
182	ret.translated_addr = tte & IOMMU_TTE_PHYS_MASK_8K;
183	ret.addr_mask = (IOMMU_PAGE_SIZE_8K - 1);
184	}
185
602c993a MCA	186	trace_sun4u_iommu_translate(ret.iova, ret.translated_addr, tte);
602c993a MCA	187
0ea833c2 MCA	188	return ret;
	189	}
	190
	191	static void iommu_mem_write(void *opaque, hwaddr addr,
	192	uint64_t val, unsigned size)
	193	{
	194	IOMMUState *is = opaque;
	195
09ecbb78	196	trace_sun4u_iommu_mem_write(addr, val, size);
0ea833c2 MCA	197
	198	switch (addr) {
	199	case IOMMU_CTRL:
	200	if (size == 4) {
	201	is->regs[IOMMU_CTRL >> 3] &= 0xffffffffULL;
	202	is->regs[IOMMU_CTRL >> 3] \|= val << 32;
	203	} else {
	204	is->regs[IOMMU_CTRL >> 3] = val;
	205	}
	206	break;
	207	case IOMMU_CTRL + 0x4:
	208	is->regs[IOMMU_CTRL >> 3] &= 0xffffffff00000000ULL;
	209	is->regs[IOMMU_CTRL >> 3] \|= val & 0xffffffffULL;
	210	break;
	211	case IOMMU_BASE:
	212	if (size == 4) {
	213	is->regs[IOMMU_BASE >> 3] &= 0xffffffffULL;
	214	is->regs[IOMMU_BASE >> 3] \|= val << 32;
	215	} else {
	216	is->regs[IOMMU_BASE >> 3] = val;
	217	}
	218	break;
	219	case IOMMU_BASE + 0x4:
	220	is->regs[IOMMU_BASE >> 3] &= 0xffffffff00000000ULL;
	221	is->regs[IOMMU_BASE >> 3] \|= val & 0xffffffffULL;
	222	break;
	223	case IOMMU_FLUSH:
	224	case IOMMU_FLUSH + 0x4:
	225	break;
	226	default:
	227	qemu_log_mask(LOG_UNIMP,
4c9fbc38	228	"sun4u-iommu: Unimplemented register write "
0ea833c2 MCA	229	"reg 0x%" HWADDR_PRIx " size 0x%x value 0x%" PRIx64 "\n",
	230	addr, size, val);
	231	break;
	232	}
	233	}
	234
	235	static uint64_t iommu_mem_read(void *opaque, hwaddr addr, unsigned size)
	236	{
	237	IOMMUState *is = opaque;
	238	uint64_t val;
	239
	240	switch (addr) {
	241	case IOMMU_CTRL:
	242	if (size == 4) {
	243	val = is->regs[IOMMU_CTRL >> 3] >> 32;
	244	} else {
	245	val = is->regs[IOMMU_CTRL >> 3];
	246	}
	247	break;
	248	case IOMMU_CTRL + 0x4:
	249	val = is->regs[IOMMU_CTRL >> 3] & 0xffffffffULL;
	250	break;
	251	case IOMMU_BASE:
	252	if (size == 4) {
	253	val = is->regs[IOMMU_BASE >> 3] >> 32;
	254	} else {
	255	val = is->regs[IOMMU_BASE >> 3];
	256	}
	257	break;
	258	case IOMMU_BASE + 0x4:
	259	val = is->regs[IOMMU_BASE >> 3] & 0xffffffffULL;
	260	break;
	261	case IOMMU_FLUSH:
	262	case IOMMU_FLUSH + 0x4:
	263	val = 0;
	264	break;
	265	default:
	266	qemu_log_mask(LOG_UNIMP,
4c9fbc38	267	"sun4u-iommu: Unimplemented register read "
0ea833c2 MCA	268	"reg 0x%" HWADDR_PRIx " size 0x%x\n",
	269	addr, size);
	270	val = 0;
	271	break;
	272	}
	273
09ecbb78	274	trace_sun4u_iommu_mem_read(addr, val, size);
0ea833c2 MCA	275
	276	return val;
	277	}
	278
	279	static const MemoryRegionOps iommu_mem_ops = {
	280	.read = iommu_mem_read,
	281	.write = iommu_mem_write,
	282	.endianness = DEVICE_BIG_ENDIAN,
	283	};
	284
	285	static void iommu_reset(DeviceState *d)
	286	{
	287	IOMMUState *s = SUN4U_IOMMU(d);
	288
	289	memset(s->regs, 0, IOMMU_NREGS * sizeof(uint64_t));
	290	}
	291
	292	static void iommu_init(Object *obj)
	293	{
	294	IOMMUState *s = SUN4U_IOMMU(obj);
	295	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	296
	297	memory_region_init_iommu(&s->iommu, sizeof(s->iommu),
4c9fbc38 MCA	298	TYPE_SUN4U_IOMMU_MEMORY_REGION, OBJECT(s),
	299	"iommu-sun4u", UINT64_MAX);
	300	address_space_init(&s->iommu_as, MEMORY_REGION(&s->iommu), "iommu-as");
0ea833c2 MCA	301
	302	memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
	303	IOMMU_NREGS * sizeof(uint64_t));
	304	sysbus_init_mmio(sbd, &s->iomem);
	305	}
	306
	307	static void iommu_class_init(ObjectClass klass, void data)
	308	{
	309	DeviceClass *dc = DEVICE_CLASS(klass);
	310
	311	dc->reset = iommu_reset;
	312	}
	313
4c9fbc38	314	static const TypeInfo iommu_info = {
0ea833c2 MCA	315	.name = TYPE_SUN4U_IOMMU,
	316	.parent = TYPE_SYS_BUS_DEVICE,
	317	.instance_size = sizeof(IOMMUState),
	318	.instance_init = iommu_init,
	319	.class_init = iommu_class_init,
	320	};
	321
4c9fbc38	322	static void sun4u_iommu_memory_region_class_init(ObjectClass klass, void data)
0ea833c2 MCA	323	{
	324	IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
	325
4c9fbc38	326	imrc->translate = sun4u_translate_iommu;
0ea833c2 MCA	327	}
0ea833c2 MCA	328
4c9fbc38	329	static const TypeInfo sun4u_iommu_memory_region_info = {
0ea833c2	330	.parent = TYPE_IOMMU_MEMORY_REGION,
4c9fbc38 MCA	331	.name = TYPE_SUN4U_IOMMU_MEMORY_REGION,
4c9fbc38 MCA	332	.class_init = sun4u_iommu_memory_region_class_init,
0ea833c2 MCA	333	};
0ea833c2 MCA	334
4c9fbc38	335	static void iommu_register_types(void)
0ea833c2	336	{
4c9fbc38 MCA	337	type_register_static(&iommu_info);
4c9fbc38 MCA	338	type_register_static(&sun4u_iommu_memory_region_info);
0ea833c2 MCA	339	}
0ea833c2 MCA	340
4c9fbc38	341	type_init(iommu_register_types)