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7c1c69bc CLG |
1 | /* |
2 | * ASPEED AST2400 SMC Controller (SPI Flash Only) | |
3 | * | |
4 | * Copyright (C) 2016 IBM Corp. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include "qemu/osdep.h" | |
26 | #include "hw/sysbus.h" | |
d6454270 | 27 | #include "migration/vmstate.h" |
7c1c69bc | 28 | #include "qemu/log.h" |
0b8fa32f | 29 | #include "qemu/module.h" |
d6e3f50a | 30 | #include "qemu/error-report.h" |
c4e1f0b4 | 31 | #include "qapi/error.h" |
bcaa8ddd | 32 | #include "qemu/units.h" |
bd6ce9a6 | 33 | #include "trace.h" |
7c1c69bc | 34 | |
64552b6b | 35 | #include "hw/irq.h" |
a27bd6c7 | 36 | #include "hw/qdev-properties.h" |
7c1c69bc CLG |
37 | #include "hw/ssi/aspeed_smc.h" |
38 | ||
39 | /* CE Type Setting Register */ | |
40 | #define R_CONF (0x00 / 4) | |
41 | #define CONF_LEGACY_DISABLE (1 << 31) | |
42 | #define CONF_ENABLE_W4 20 | |
43 | #define CONF_ENABLE_W3 19 | |
44 | #define CONF_ENABLE_W2 18 | |
45 | #define CONF_ENABLE_W1 17 | |
46 | #define CONF_ENABLE_W0 16 | |
0707b34d CLG |
47 | #define CONF_FLASH_TYPE4 8 |
48 | #define CONF_FLASH_TYPE3 6 | |
49 | #define CONF_FLASH_TYPE2 4 | |
50 | #define CONF_FLASH_TYPE1 2 | |
51 | #define CONF_FLASH_TYPE0 0 | |
52 | #define CONF_FLASH_TYPE_NOR 0x0 | |
53 | #define CONF_FLASH_TYPE_NAND 0x1 | |
bcaa8ddd | 54 | #define CONF_FLASH_TYPE_SPI 0x2 /* AST2600 is SPI only */ |
7c1c69bc CLG |
55 | |
56 | /* CE Control Register */ | |
57 | #define R_CE_CTRL (0x04 / 4) | |
58 | #define CTRL_EXTENDED4 4 /* 32 bit addressing for SPI */ | |
59 | #define CTRL_EXTENDED3 3 /* 32 bit addressing for SPI */ | |
60 | #define CTRL_EXTENDED2 2 /* 32 bit addressing for SPI */ | |
61 | #define CTRL_EXTENDED1 1 /* 32 bit addressing for SPI */ | |
62 | #define CTRL_EXTENDED0 0 /* 32 bit addressing for SPI */ | |
63 | ||
64 | /* Interrupt Control and Status Register */ | |
65 | #define R_INTR_CTRL (0x08 / 4) | |
66 | #define INTR_CTRL_DMA_STATUS (1 << 11) | |
67 | #define INTR_CTRL_CMD_ABORT_STATUS (1 << 10) | |
68 | #define INTR_CTRL_WRITE_PROTECT_STATUS (1 << 9) | |
69 | #define INTR_CTRL_DMA_EN (1 << 3) | |
70 | #define INTR_CTRL_CMD_ABORT_EN (1 << 2) | |
71 | #define INTR_CTRL_WRITE_PROTECT_EN (1 << 1) | |
72 | ||
af453a5e CLG |
73 | /* Command Control Register */ |
74 | #define R_CE_CMD_CTRL (0x0C / 4) | |
75 | #define CTRL_ADDR_BYTE0_DISABLE_SHIFT 4 | |
76 | #define CTRL_DATA_BYTE0_DISABLE_SHIFT 0 | |
77 | ||
78 | #define aspeed_smc_addr_byte_enabled(s, i) \ | |
79 | (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_ADDR_BYTE0_DISABLE_SHIFT + (i))))) | |
80 | #define aspeed_smc_data_byte_enabled(s, i) \ | |
81 | (!((s)->regs[R_CE_CMD_CTRL] & (1 << (CTRL_DATA_BYTE0_DISABLE_SHIFT + (i))))) | |
82 | ||
7c1c69bc CLG |
83 | /* CEx Control Register */ |
84 | #define R_CTRL0 (0x10 / 4) | |
bcaa8ddd CLG |
85 | #define CTRL_IO_QPI (1 << 31) |
86 | #define CTRL_IO_QUAD_DATA (1 << 30) | |
0721309e CLG |
87 | #define CTRL_IO_DUAL_DATA (1 << 29) |
88 | #define CTRL_IO_DUAL_ADDR_DATA (1 << 28) /* Includes dummies */ | |
bcaa8ddd | 89 | #define CTRL_IO_QUAD_ADDR_DATA (1 << 28) /* Includes dummies */ |
7c1c69bc CLG |
90 | #define CTRL_CMD_SHIFT 16 |
91 | #define CTRL_CMD_MASK 0xff | |
ac2810de | 92 | #define CTRL_DUMMY_HIGH_SHIFT 14 |
fcdf2c59 | 93 | #define CTRL_AST2400_SPI_4BYTE (1 << 13) |
0d72c717 CLG |
94 | #define CE_CTRL_CLOCK_FREQ_SHIFT 8 |
95 | #define CE_CTRL_CLOCK_FREQ_MASK 0xf | |
96 | #define CE_CTRL_CLOCK_FREQ(div) \ | |
97 | (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) | |
ac2810de | 98 | #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ |
7c1c69bc CLG |
99 | #define CTRL_CE_STOP_ACTIVE (1 << 2) |
100 | #define CTRL_CMD_MODE_MASK 0x3 | |
101 | #define CTRL_READMODE 0x0 | |
102 | #define CTRL_FREADMODE 0x1 | |
103 | #define CTRL_WRITEMODE 0x2 | |
104 | #define CTRL_USERMODE 0x3 | |
105 | #define R_CTRL1 (0x14 / 4) | |
106 | #define R_CTRL2 (0x18 / 4) | |
107 | #define R_CTRL3 (0x1C / 4) | |
108 | #define R_CTRL4 (0x20 / 4) | |
109 | ||
110 | /* CEx Segment Address Register */ | |
111 | #define R_SEG_ADDR0 (0x30 / 4) | |
a03cb1da CLG |
112 | #define SEG_END_SHIFT 24 /* 8MB units */ |
113 | #define SEG_END_MASK 0xff | |
7c1c69bc | 114 | #define SEG_START_SHIFT 16 /* address bit [A29-A23] */ |
a03cb1da | 115 | #define SEG_START_MASK 0xff |
7c1c69bc CLG |
116 | #define R_SEG_ADDR1 (0x34 / 4) |
117 | #define R_SEG_ADDR2 (0x38 / 4) | |
118 | #define R_SEG_ADDR3 (0x3C / 4) | |
119 | #define R_SEG_ADDR4 (0x40 / 4) | |
120 | ||
121 | /* Misc Control Register #1 */ | |
122 | #define R_MISC_CTRL1 (0x50 / 4) | |
123 | ||
9149af2a CLG |
124 | /* SPI dummy cycle data */ |
125 | #define R_DUMMY_DATA (0x54 / 4) | |
7c1c69bc | 126 | |
45a904af CLG |
127 | /* FMC_WDT2 Control/Status Register for Alternate Boot (AST2600) */ |
128 | #define R_FMC_WDT2_CTRL (0x64 / 4) | |
129 | #define FMC_WDT2_CTRL_ALT_BOOT_MODE BIT(6) /* O: 2 chips 1: 1 chip */ | |
130 | #define FMC_WDT2_CTRL_SINGLE_BOOT_MODE BIT(5) | |
131 | #define FMC_WDT2_CTRL_BOOT_SOURCE BIT(4) /* O: primary 1: alternate */ | |
132 | #define FMC_WDT2_CTRL_EN BIT(0) | |
133 | ||
7c1c69bc CLG |
134 | /* DMA Control/Status Register */ |
135 | #define R_DMA_CTRL (0x80 / 4) | |
1769a70e CLG |
136 | #define DMA_CTRL_REQUEST (1 << 31) |
137 | #define DMA_CTRL_GRANT (1 << 30) | |
7c1c69bc CLG |
138 | #define DMA_CTRL_DELAY_MASK 0xf |
139 | #define DMA_CTRL_DELAY_SHIFT 8 | |
140 | #define DMA_CTRL_FREQ_MASK 0xf | |
141 | #define DMA_CTRL_FREQ_SHIFT 4 | |
0d72c717 | 142 | #define DMA_CTRL_CALIB (1 << 3) |
7c1c69bc | 143 | #define DMA_CTRL_CKSUM (1 << 2) |
c4e1f0b4 CLG |
144 | #define DMA_CTRL_WRITE (1 << 1) |
145 | #define DMA_CTRL_ENABLE (1 << 0) | |
7c1c69bc CLG |
146 | |
147 | /* DMA Flash Side Address */ | |
148 | #define R_DMA_FLASH_ADDR (0x84 / 4) | |
149 | ||
150 | /* DMA DRAM Side Address */ | |
151 | #define R_DMA_DRAM_ADDR (0x88 / 4) | |
152 | ||
153 | /* DMA Length Register */ | |
154 | #define R_DMA_LEN (0x8C / 4) | |
155 | ||
156 | /* Checksum Calculation Result */ | |
157 | #define R_DMA_CHECKSUM (0x90 / 4) | |
158 | ||
f286f04c | 159 | /* Read Timing Compensation Register */ |
7c1c69bc CLG |
160 | #define R_TIMINGS (0x94 / 4) |
161 | ||
bcaa8ddd | 162 | /* SPI controller registers and bits (AST2400) */ |
7c1c69bc CLG |
163 | #define R_SPI_CONF (0x00 / 4) |
164 | #define SPI_CONF_ENABLE_W0 0 | |
165 | #define R_SPI_CTRL0 (0x4 / 4) | |
166 | #define R_SPI_MISC_CTRL (0x10 / 4) | |
167 | #define R_SPI_TIMINGS (0x14 / 4) | |
168 | ||
087b57c9 CLG |
169 | #define ASPEED_SMC_R_SPI_MAX (0x20 / 4) |
170 | #define ASPEED_SMC_R_SMC_MAX (0x20 / 4) | |
171 | ||
c4e1f0b4 CLG |
172 | /* |
173 | * DMA DRAM addresses should be 4 bytes aligned and the valid address | |
174 | * range is 0x40000000 - 0x5FFFFFFF (AST2400) | |
175 | * 0x80000000 - 0xBFFFFFFF (AST2500) | |
176 | * | |
177 | * DMA flash addresses should be 4 bytes aligned and the valid address | |
178 | * range is 0x20000000 - 0x2FFFFFFF. | |
179 | * | |
180 | * DMA length is from 4 bytes to 32MB | |
181 | * 0: 4 bytes | |
182 | * 0x7FFFFF: 32M bytes | |
183 | */ | |
30b6852c CLG |
184 | #define DMA_DRAM_ADDR(asc, val) ((val) & (asc)->dma_dram_mask) |
185 | #define DMA_FLASH_ADDR(asc, val) ((val) & (asc)->dma_flash_mask) | |
c4e1f0b4 CLG |
186 | #define DMA_LENGTH(val) ((val) & 0x01FFFFFC) |
187 | ||
fcdf2c59 CLG |
188 | /* Flash opcodes. */ |
189 | #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ | |
190 | ||
f95c4bff CLG |
191 | #define SNOOP_OFF 0xFF |
192 | #define SNOOP_START 0x0 | |
193 | ||
924ed163 | 194 | /* |
5ade579b | 195 | * Default segments mapping addresses and size for each peripheral per |
924ed163 | 196 | * controller. These can be changed when board is initialized with the |
a03cb1da | 197 | * Segment Address Registers. |
924ed163 | 198 | */ |
30b6852c CLG |
199 | static const AspeedSegments aspeed_2500_spi1_segments[]; |
200 | static const AspeedSegments aspeed_2500_spi2_segments[]; | |
1769a70e | 201 | |
1c5ee69d | 202 | #define ASPEED_SMC_FEATURE_DMA 0x1 |
1769a70e | 203 | #define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 |
45a904af | 204 | #define ASPEED_SMC_FEATURE_WDT_CONTROL 0x4 |
1c5ee69d | 205 | |
30b6852c | 206 | static inline bool aspeed_smc_has_dma(const AspeedSMCClass *asc) |
bcaa8ddd | 207 | { |
30b6852c | 208 | return !!(asc->features & ASPEED_SMC_FEATURE_DMA); |
bcaa8ddd CLG |
209 | } |
210 | ||
30b6852c | 211 | static inline bool aspeed_smc_has_wdt_control(const AspeedSMCClass *asc) |
bcaa8ddd | 212 | { |
30b6852c | 213 | return !!(asc->features & ASPEED_SMC_FEATURE_WDT_CONTROL); |
bcaa8ddd CLG |
214 | } |
215 | ||
32c54bd0 CLG |
216 | #define aspeed_smc_error(fmt, ...) \ |
217 | qemu_log_mask(LOG_GUEST_ERROR, "%s: " fmt "\n", __func__, ## __VA_ARGS__) | |
218 | ||
a03cb1da CLG |
219 | static bool aspeed_smc_flash_overlap(const AspeedSMCState *s, |
220 | const AspeedSegments *new, | |
221 | int cs) | |
222 | { | |
30b6852c | 223 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
a03cb1da CLG |
224 | AspeedSegments seg; |
225 | int i; | |
226 | ||
ae945a00 | 227 | for (i = 0; i < asc->cs_num_max; i++) { |
a03cb1da CLG |
228 | if (i == cs) { |
229 | continue; | |
230 | } | |
231 | ||
30b6852c | 232 | asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + i], &seg); |
a03cb1da CLG |
233 | |
234 | if (new->addr + new->size > seg.addr && | |
235 | new->addr < seg.addr + seg.size) { | |
32c54bd0 CLG |
236 | aspeed_smc_error("new segment CS%d [ 0x%" |
237 | HWADDR_PRIx" - 0x%"HWADDR_PRIx" ] overlaps with " | |
238 | "CS%d [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", | |
239 | cs, new->addr, new->addr + new->size, | |
240 | i, seg.addr, seg.addr + seg.size); | |
a03cb1da CLG |
241 | return true; |
242 | } | |
243 | } | |
244 | return false; | |
245 | } | |
246 | ||
673b1f86 CLG |
247 | static void aspeed_smc_flash_set_segment_region(AspeedSMCState *s, int cs, |
248 | uint64_t regval) | |
249 | { | |
30b6852c | 250 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
673b1f86 CLG |
251 | AspeedSMCFlash *fl = &s->flashes[cs]; |
252 | AspeedSegments seg; | |
253 | ||
30b6852c | 254 | asc->reg_to_segment(s, regval, &seg); |
673b1f86 CLG |
255 | |
256 | memory_region_transaction_begin(); | |
257 | memory_region_set_size(&fl->mmio, seg.size); | |
30b6852c | 258 | memory_region_set_address(&fl->mmio, seg.addr - asc->flash_window_base); |
2175eacf | 259 | memory_region_set_enabled(&fl->mmio, !!seg.size); |
673b1f86 CLG |
260 | memory_region_transaction_commit(); |
261 | ||
7c8d2fc4 CLG |
262 | if (asc->segment_addr_mask) { |
263 | regval &= asc->segment_addr_mask; | |
264 | } | |
265 | ||
673b1f86 CLG |
266 | s->regs[R_SEG_ADDR0 + cs] = regval; |
267 | } | |
268 | ||
a03cb1da CLG |
269 | static void aspeed_smc_flash_set_segment(AspeedSMCState *s, int cs, |
270 | uint64_t new) | |
271 | { | |
30b6852c | 272 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
a03cb1da CLG |
273 | AspeedSegments seg; |
274 | ||
30b6852c | 275 | asc->reg_to_segment(s, new, &seg); |
a03cb1da | 276 | |
bd6ce9a6 CLG |
277 | trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.size); |
278 | ||
a03cb1da | 279 | /* The start address of CS0 is read-only */ |
30b6852c | 280 | if (cs == 0 && seg.addr != asc->flash_window_base) { |
32c54bd0 CLG |
281 | aspeed_smc_error("Tried to change CS0 start address to 0x%" |
282 | HWADDR_PRIx, seg.addr); | |
30b6852c CLG |
283 | seg.addr = asc->flash_window_base; |
284 | new = asc->segment_to_reg(s, &seg); | |
a03cb1da CLG |
285 | } |
286 | ||
287 | /* | |
288 | * The end address of the AST2500 spi controllers is also | |
289 | * read-only. | |
290 | */ | |
30b6852c CLG |
291 | if ((asc->segments == aspeed_2500_spi1_segments || |
292 | asc->segments == aspeed_2500_spi2_segments) && | |
ae945a00 | 293 | cs == asc->cs_num_max && |
30b6852c CLG |
294 | seg.addr + seg.size != asc->segments[cs].addr + |
295 | asc->segments[cs].size) { | |
32c54bd0 CLG |
296 | aspeed_smc_error("Tried to change CS%d end address to 0x%" |
297 | HWADDR_PRIx, cs, seg.addr + seg.size); | |
30b6852c | 298 | seg.size = asc->segments[cs].addr + asc->segments[cs].size - |
0584d3c3 | 299 | seg.addr; |
30b6852c | 300 | new = asc->segment_to_reg(s, &seg); |
a03cb1da CLG |
301 | } |
302 | ||
303 | /* Keep the segment in the overall flash window */ | |
2175eacf | 304 | if (seg.size && |
30b6852c CLG |
305 | (seg.addr + seg.size <= asc->flash_window_base || |
306 | seg.addr > asc->flash_window_base + asc->flash_window_size)) { | |
32c54bd0 CLG |
307 | aspeed_smc_error("new segment for CS%d is invalid : " |
308 | "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", | |
309 | cs, seg.addr, seg.addr + seg.size); | |
a03cb1da CLG |
310 | return; |
311 | } | |
312 | ||
313 | /* Check start address vs. alignment */ | |
0584d3c3 | 314 | if (seg.size && !QEMU_IS_ALIGNED(seg.addr, seg.size)) { |
32c54bd0 CLG |
315 | aspeed_smc_error("new segment for CS%d is not " |
316 | "aligned : [ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", | |
317 | cs, seg.addr, seg.addr + seg.size); | |
a03cb1da CLG |
318 | } |
319 | ||
0584d3c3 CLG |
320 | /* And segments should not overlap (in the specs) */ |
321 | aspeed_smc_flash_overlap(s, &seg, cs); | |
a03cb1da CLG |
322 | |
323 | /* All should be fine now to move the region */ | |
673b1f86 | 324 | aspeed_smc_flash_set_segment_region(s, cs, new); |
a03cb1da CLG |
325 | } |
326 | ||
924ed163 CLG |
327 | static uint64_t aspeed_smc_flash_default_read(void *opaque, hwaddr addr, |
328 | unsigned size) | |
329 | { | |
c1402ea1 | 330 | aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u", addr, size); |
924ed163 CLG |
331 | return 0; |
332 | } | |
333 | ||
334 | static void aspeed_smc_flash_default_write(void *opaque, hwaddr addr, | |
335 | uint64_t data, unsigned size) | |
336 | { | |
32c54bd0 CLG |
337 | aspeed_smc_error("To 0x%" HWADDR_PRIx " of size %u: 0x%" PRIx64, |
338 | addr, size, data); | |
924ed163 CLG |
339 | } |
340 | ||
341 | static const MemoryRegionOps aspeed_smc_flash_default_ops = { | |
342 | .read = aspeed_smc_flash_default_read, | |
343 | .write = aspeed_smc_flash_default_write, | |
344 | .endianness = DEVICE_LITTLE_ENDIAN, | |
345 | .valid = { | |
346 | .min_access_size = 1, | |
347 | .max_access_size = 4, | |
348 | }, | |
349 | }; | |
350 | ||
f248a9db | 351 | static inline int aspeed_smc_flash_mode(const AspeedSMCFlash *fl) |
924ed163 | 352 | { |
f248a9db CLG |
353 | const AspeedSMCState *s = fl->controller; |
354 | ||
10f915e4 | 355 | return s->regs[s->r_ctrl0 + fl->cs] & CTRL_CMD_MODE_MASK; |
924ed163 CLG |
356 | } |
357 | ||
fcdf2c59 | 358 | static inline bool aspeed_smc_is_writable(const AspeedSMCFlash *fl) |
924ed163 | 359 | { |
fcdf2c59 CLG |
360 | const AspeedSMCState *s = fl->controller; |
361 | ||
10f915e4 | 362 | return s->regs[s->r_conf] & (1 << (s->conf_enable_w0 + fl->cs)); |
924ed163 CLG |
363 | } |
364 | ||
fcdf2c59 | 365 | static inline int aspeed_smc_flash_cmd(const AspeedSMCFlash *fl) |
924ed163 | 366 | { |
f248a9db | 367 | const AspeedSMCState *s = fl->controller; |
10f915e4 | 368 | int cmd = (s->regs[s->r_ctrl0 + fl->cs] >> CTRL_CMD_SHIFT) & CTRL_CMD_MASK; |
f248a9db | 369 | |
bcaa8ddd CLG |
370 | /* |
371 | * In read mode, the default SPI command is READ (0x3). In other | |
372 | * modes, the command should necessarily be defined | |
373 | * | |
374 | * TODO: add support for READ4 (0x13) on AST2600 | |
375 | */ | |
fcdf2c59 CLG |
376 | if (aspeed_smc_flash_mode(fl) == CTRL_READMODE) { |
377 | cmd = SPI_OP_READ; | |
378 | } | |
379 | ||
380 | if (!cmd) { | |
32c54bd0 CLG |
381 | aspeed_smc_error("no command defined for mode %d", |
382 | aspeed_smc_flash_mode(fl)); | |
fcdf2c59 CLG |
383 | } |
384 | ||
385 | return cmd; | |
386 | } | |
387 | ||
a779e37c | 388 | static inline int aspeed_smc_flash_addr_width(const AspeedSMCFlash *fl) |
fcdf2c59 CLG |
389 | { |
390 | const AspeedSMCState *s = fl->controller; | |
b84a9482 | 391 | AspeedSMCClass *asc = fl->asc; |
fcdf2c59 | 392 | |
a779e37c CLG |
393 | if (asc->addr_width) { |
394 | return asc->addr_width(s); | |
fcdf2c59 | 395 | } else { |
a779e37c | 396 | return s->regs[s->r_ce_ctrl] & (1 << (CTRL_EXTENDED0 + fl->cs)) ? 4 : 3; |
fcdf2c59 CLG |
397 | } |
398 | } | |
399 | ||
e7e741ca | 400 | static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) |
fcdf2c59 | 401 | { |
e7e741ca CLG |
402 | AspeedSMCState *s = fl->controller; |
403 | ||
10f915e4 | 404 | trace_aspeed_smc_flash_select(fl->cs, unselect ? "un" : ""); |
fcdf2c59 | 405 | |
10f915e4 | 406 | qemu_set_irq(s->cs_lines[fl->cs], unselect); |
fcdf2c59 CLG |
407 | } |
408 | ||
409 | static void aspeed_smc_flash_select(AspeedSMCFlash *fl) | |
410 | { | |
e7e741ca | 411 | aspeed_smc_flash_do_select(fl, false); |
fcdf2c59 CLG |
412 | } |
413 | ||
414 | static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) | |
415 | { | |
e7e741ca | 416 | aspeed_smc_flash_do_select(fl, true); |
fcdf2c59 CLG |
417 | } |
418 | ||
419 | static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, | |
420 | uint32_t addr) | |
421 | { | |
422 | const AspeedSMCState *s = fl->controller; | |
b84a9482 | 423 | AspeedSMCClass *asc = fl->asc; |
fcdf2c59 CLG |
424 | AspeedSegments seg; |
425 | ||
10f915e4 | 426 | asc->reg_to_segment(s, s->regs[R_SEG_ADDR0 + fl->cs], &seg); |
b4cc583f | 427 | if ((addr % seg.size) != addr) { |
32c54bd0 CLG |
428 | aspeed_smc_error("invalid address 0x%08x for CS%d segment : " |
429 | "[ 0x%"HWADDR_PRIx" - 0x%"HWADDR_PRIx" ]", | |
10f915e4 | 430 | addr, fl->cs, seg.addr, seg.addr + seg.size); |
b4cc583f | 431 | addr %= seg.size; |
fcdf2c59 CLG |
432 | } |
433 | ||
fcdf2c59 CLG |
434 | return addr; |
435 | } | |
436 | ||
ac2810de CLG |
437 | static int aspeed_smc_flash_dummies(const AspeedSMCFlash *fl) |
438 | { | |
439 | const AspeedSMCState *s = fl->controller; | |
10f915e4 | 440 | uint32_t r_ctrl0 = s->regs[s->r_ctrl0 + fl->cs]; |
ac2810de CLG |
441 | uint32_t dummy_high = (r_ctrl0 >> CTRL_DUMMY_HIGH_SHIFT) & 0x1; |
442 | uint32_t dummy_low = (r_ctrl0 >> CTRL_DUMMY_LOW_SHIFT) & 0x3; | |
0721309e | 443 | uint32_t dummies = ((dummy_high << 2) | dummy_low) * 8; |
ac2810de | 444 | |
0721309e CLG |
445 | if (r_ctrl0 & CTRL_IO_DUAL_ADDR_DATA) { |
446 | dummies /= 2; | |
447 | } | |
448 | ||
449 | return dummies; | |
ac2810de CLG |
450 | } |
451 | ||
96c4be95 | 452 | static void aspeed_smc_flash_setup(AspeedSMCFlash *fl, uint32_t addr) |
fcdf2c59 CLG |
453 | { |
454 | const AspeedSMCState *s = fl->controller; | |
455 | uint8_t cmd = aspeed_smc_flash_cmd(fl); | |
a779e37c | 456 | int i = aspeed_smc_flash_addr_width(fl); |
fcdf2c59 CLG |
457 | |
458 | /* Flash access can not exceed CS segment */ | |
459 | addr = aspeed_smc_check_segment_addr(fl, addr); | |
460 | ||
461 | ssi_transfer(s->spi, cmd); | |
af453a5e CLG |
462 | while (i--) { |
463 | if (aspeed_smc_addr_byte_enabled(s, i)) { | |
464 | ssi_transfer(s->spi, (addr >> (i * 8)) & 0xff); | |
465 | } | |
fcdf2c59 | 466 | } |
96c4be95 CLG |
467 | |
468 | /* | |
469 | * Use fake transfers to model dummy bytes. The value should | |
470 | * be configured to some non-zero value in fast read mode and | |
471 | * zero in read mode. But, as the HW allows inconsistent | |
472 | * settings, let's check for fast read mode. | |
473 | */ | |
474 | if (aspeed_smc_flash_mode(fl) == CTRL_FREADMODE) { | |
475 | for (i = 0; i < aspeed_smc_flash_dummies(fl); i++) { | |
9149af2a | 476 | ssi_transfer(fl->controller->spi, s->regs[R_DUMMY_DATA] & 0xff); |
96c4be95 CLG |
477 | } |
478 | } | |
924ed163 CLG |
479 | } |
480 | ||
481 | static uint64_t aspeed_smc_flash_read(void *opaque, hwaddr addr, unsigned size) | |
482 | { | |
483 | AspeedSMCFlash *fl = opaque; | |
fcdf2c59 | 484 | AspeedSMCState *s = fl->controller; |
924ed163 CLG |
485 | uint64_t ret = 0; |
486 | int i; | |
487 | ||
fcdf2c59 CLG |
488 | switch (aspeed_smc_flash_mode(fl)) { |
489 | case CTRL_USERMODE: | |
924ed163 | 490 | for (i = 0; i < size; i++) { |
75dbf30b | 491 | ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); |
924ed163 | 492 | } |
fcdf2c59 CLG |
493 | break; |
494 | case CTRL_READMODE: | |
495 | case CTRL_FREADMODE: | |
496 | aspeed_smc_flash_select(fl); | |
96c4be95 | 497 | aspeed_smc_flash_setup(fl, addr); |
ac2810de | 498 | |
fcdf2c59 | 499 | for (i = 0; i < size; i++) { |
75dbf30b | 500 | ret |= (uint64_t) ssi_transfer(s->spi, 0x0) << (8 * i); |
fcdf2c59 CLG |
501 | } |
502 | ||
503 | aspeed_smc_flash_unselect(fl); | |
504 | break; | |
505 | default: | |
32c54bd0 | 506 | aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); |
924ed163 CLG |
507 | } |
508 | ||
10f915e4 | 509 | trace_aspeed_smc_flash_read(fl->cs, addr, size, ret, |
bd6ce9a6 | 510 | aspeed_smc_flash_mode(fl)); |
924ed163 CLG |
511 | return ret; |
512 | } | |
513 | ||
f95c4bff CLG |
514 | /* |
515 | * TODO (clg@kaod.org): stolen from xilinx_spips.c. Should move to a | |
516 | * common include header. | |
517 | */ | |
518 | typedef enum { | |
519 | READ = 0x3, READ_4 = 0x13, | |
520 | FAST_READ = 0xb, FAST_READ_4 = 0x0c, | |
521 | DOR = 0x3b, DOR_4 = 0x3c, | |
522 | QOR = 0x6b, QOR_4 = 0x6c, | |
523 | DIOR = 0xbb, DIOR_4 = 0xbc, | |
524 | QIOR = 0xeb, QIOR_4 = 0xec, | |
525 | ||
526 | PP = 0x2, PP_4 = 0x12, | |
527 | DPP = 0xa2, | |
528 | QPP = 0x32, QPP_4 = 0x34, | |
529 | } FlashCMD; | |
530 | ||
531 | static int aspeed_smc_num_dummies(uint8_t command) | |
532 | { | |
533 | switch (command) { /* check for dummies */ | |
534 | case READ: /* no dummy bytes/cycles */ | |
535 | case PP: | |
536 | case DPP: | |
537 | case QPP: | |
538 | case READ_4: | |
539 | case PP_4: | |
540 | case QPP_4: | |
541 | return 0; | |
542 | case FAST_READ: | |
543 | case DOR: | |
544 | case QOR: | |
7faf6f17 | 545 | case FAST_READ_4: |
f95c4bff CLG |
546 | case DOR_4: |
547 | case QOR_4: | |
548 | return 1; | |
549 | case DIOR: | |
f95c4bff CLG |
550 | case DIOR_4: |
551 | return 2; | |
552 | case QIOR: | |
553 | case QIOR_4: | |
554 | return 4; | |
555 | default: | |
556 | return -1; | |
557 | } | |
558 | } | |
559 | ||
560 | static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, uint64_t data, | |
561 | unsigned size) | |
562 | { | |
563 | AspeedSMCState *s = fl->controller; | |
a779e37c | 564 | uint8_t addr_width = aspeed_smc_flash_addr_width(fl); |
f95c4bff | 565 | |
10f915e4 | 566 | trace_aspeed_smc_do_snoop(fl->cs, s->snoop_index, s->snoop_dummies, |
bd6ce9a6 CLG |
567 | (uint8_t) data & 0xff); |
568 | ||
f95c4bff CLG |
569 | if (s->snoop_index == SNOOP_OFF) { |
570 | return false; /* Do nothing */ | |
571 | ||
572 | } else if (s->snoop_index == SNOOP_START) { | |
573 | uint8_t cmd = data & 0xff; | |
574 | int ndummies = aspeed_smc_num_dummies(cmd); | |
575 | ||
576 | /* | |
577 | * No dummy cycles are expected with the current command. Turn | |
578 | * off snooping and let the transfer proceed normally. | |
579 | */ | |
580 | if (ndummies <= 0) { | |
581 | s->snoop_index = SNOOP_OFF; | |
582 | return false; | |
583 | } | |
584 | ||
585 | s->snoop_dummies = ndummies * 8; | |
586 | ||
587 | } else if (s->snoop_index >= addr_width + 1) { | |
588 | ||
589 | /* The SPI transfer has reached the dummy cycles sequence */ | |
590 | for (; s->snoop_dummies; s->snoop_dummies--) { | |
591 | ssi_transfer(s->spi, s->regs[R_DUMMY_DATA] & 0xff); | |
592 | } | |
593 | ||
594 | /* If no more dummy cycles are expected, turn off snooping */ | |
595 | if (!s->snoop_dummies) { | |
596 | s->snoop_index = SNOOP_OFF; | |
597 | } else { | |
598 | s->snoop_index += size; | |
599 | } | |
600 | ||
601 | /* | |
602 | * Dummy cycles have been faked already. Ignore the current | |
603 | * SPI transfer | |
604 | */ | |
605 | return true; | |
606 | } | |
607 | ||
608 | s->snoop_index += size; | |
609 | return false; | |
610 | } | |
611 | ||
924ed163 | 612 | static void aspeed_smc_flash_write(void *opaque, hwaddr addr, uint64_t data, |
b3d6b8f5 | 613 | unsigned size) |
924ed163 CLG |
614 | { |
615 | AspeedSMCFlash *fl = opaque; | |
fcdf2c59 | 616 | AspeedSMCState *s = fl->controller; |
924ed163 CLG |
617 | int i; |
618 | ||
10f915e4 | 619 | trace_aspeed_smc_flash_write(fl->cs, addr, size, data, |
bd6ce9a6 CLG |
620 | aspeed_smc_flash_mode(fl)); |
621 | ||
f248a9db | 622 | if (!aspeed_smc_is_writable(fl)) { |
32c54bd0 | 623 | aspeed_smc_error("flash is not writable at 0x%" HWADDR_PRIx, addr); |
924ed163 CLG |
624 | return; |
625 | } | |
626 | ||
fcdf2c59 CLG |
627 | switch (aspeed_smc_flash_mode(fl)) { |
628 | case CTRL_USERMODE: | |
f95c4bff CLG |
629 | if (aspeed_smc_do_snoop(fl, data, size)) { |
630 | break; | |
631 | } | |
632 | ||
fcdf2c59 CLG |
633 | for (i = 0; i < size; i++) { |
634 | ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); | |
635 | } | |
636 | break; | |
637 | case CTRL_WRITEMODE: | |
638 | aspeed_smc_flash_select(fl); | |
96c4be95 | 639 | aspeed_smc_flash_setup(fl, addr); |
fcdf2c59 CLG |
640 | |
641 | for (i = 0; i < size; i++) { | |
642 | ssi_transfer(s->spi, (data >> (8 * i)) & 0xff); | |
643 | } | |
924ed163 | 644 | |
fcdf2c59 CLG |
645 | aspeed_smc_flash_unselect(fl); |
646 | break; | |
647 | default: | |
32c54bd0 | 648 | aspeed_smc_error("invalid flash mode %d", aspeed_smc_flash_mode(fl)); |
924ed163 CLG |
649 | } |
650 | } | |
651 | ||
652 | static const MemoryRegionOps aspeed_smc_flash_ops = { | |
653 | .read = aspeed_smc_flash_read, | |
654 | .write = aspeed_smc_flash_write, | |
655 | .endianness = DEVICE_LITTLE_ENDIAN, | |
656 | .valid = { | |
657 | .min_access_size = 1, | |
658 | .max_access_size = 4, | |
659 | }, | |
7c1c69bc CLG |
660 | }; |
661 | ||
e7e741ca | 662 | static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t value) |
7c1c69bc | 663 | { |
f95c4bff | 664 | AspeedSMCState *s = fl->controller; |
e7e741ca CLG |
665 | bool unselect; |
666 | ||
667 | /* User mode selects the CS, other modes unselect */ | |
668 | unselect = (value & CTRL_CMD_MODE_MASK) != CTRL_USERMODE; | |
669 | ||
670 | /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ | |
10f915e4 | 671 | if (!(s->regs[s->r_ctrl0 + fl->cs] & CTRL_CE_STOP_ACTIVE) && |
e7e741ca CLG |
672 | value & CTRL_CE_STOP_ACTIVE) { |
673 | unselect = true; | |
674 | } | |
675 | ||
10f915e4 | 676 | s->regs[s->r_ctrl0 + fl->cs] = value; |
f95c4bff | 677 | |
e7e741ca | 678 | s->snoop_index = unselect ? SNOOP_OFF : SNOOP_START; |
7c1c69bc | 679 | |
e7e741ca | 680 | aspeed_smc_flash_do_select(fl, unselect); |
7c1c69bc CLG |
681 | } |
682 | ||
683 | static void aspeed_smc_reset(DeviceState *d) | |
684 | { | |
685 | AspeedSMCState *s = ASPEED_SMC(d); | |
30b6852c | 686 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
7c1c69bc CLG |
687 | int i; |
688 | ||
71255c48 CLG |
689 | if (asc->resets) { |
690 | memcpy(s->regs, asc->resets, sizeof s->regs); | |
691 | } else { | |
692 | memset(s->regs, 0, sizeof s->regs); | |
693 | } | |
7c1c69bc | 694 | |
27a2c66c CLG |
695 | for (i = 0; i < asc->cs_num_max; i++) { |
696 | DeviceState *dev = ssi_get_cs(s->spi, i); | |
697 | if (dev) { | |
698 | qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); | |
699 | qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line); | |
700 | } | |
701 | } | |
702 | ||
5ade579b | 703 | /* Unselect all peripherals */ |
ae945a00 | 704 | for (i = 0; i < asc->cs_num_max; ++i) { |
7c1c69bc | 705 | s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; |
1d247bd0 | 706 | qemu_set_irq(s->cs_lines[i], true); |
7c1c69bc CLG |
707 | } |
708 | ||
673b1f86 | 709 | /* setup the default segment register values and regions for all */ |
ae945a00 | 710 | for (i = 0; i < asc->cs_num_max; ++i) { |
673b1f86 | 711 | aspeed_smc_flash_set_segment_region(s, i, |
30b6852c | 712 | asc->segment_to_reg(s, &asc->segments[i])); |
a03cb1da | 713 | } |
0707b34d | 714 | |
f95c4bff CLG |
715 | s->snoop_index = SNOOP_OFF; |
716 | s->snoop_dummies = 0; | |
7c1c69bc CLG |
717 | } |
718 | ||
7c1c69bc CLG |
719 | static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) |
720 | { | |
721 | AspeedSMCState *s = ASPEED_SMC(opaque); | |
30b6852c | 722 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(opaque); |
7c1c69bc CLG |
723 | |
724 | addr >>= 2; | |
725 | ||
97c2ed5d | 726 | if (addr == s->r_conf || |
f286f04c | 727 | (addr >= s->r_timings && |
30b6852c | 728 | addr < s->r_timings + asc->nregs_timings) || |
97c2ed5d | 729 | addr == s->r_ce_ctrl || |
af453a5e | 730 | addr == R_CE_CMD_CTRL || |
2e1f0502 | 731 | addr == R_INTR_CTRL || |
9149af2a | 732 | addr == R_DUMMY_DATA || |
30b6852c CLG |
733 | (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) || |
734 | (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) || | |
735 | (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR) || | |
736 | (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR) || | |
737 | (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN) || | |
738 | (aspeed_smc_has_dma(asc) && addr == R_DMA_CHECKSUM) || | |
5ade579b | 739 | (addr >= R_SEG_ADDR0 && |
ae945a00 CLG |
740 | addr < R_SEG_ADDR0 + asc->cs_num_max) || |
741 | (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max)) { | |
bd6ce9a6 | 742 | |
e2804a1e | 743 | trace_aspeed_smc_read(addr << 2, size, s->regs[addr]); |
bd6ce9a6 | 744 | |
97c2ed5d CLG |
745 | return s->regs[addr]; |
746 | } else { | |
7c1c69bc | 747 | qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", |
97c2ed5d | 748 | __func__, addr); |
b617ca92 | 749 | return -1; |
7c1c69bc | 750 | } |
7c1c69bc CLG |
751 | } |
752 | ||
0d72c717 CLG |
753 | static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) |
754 | { | |
755 | /* HCLK/1 .. HCLK/16 */ | |
756 | const uint8_t hclk_divisors[] = { | |
757 | 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 | |
758 | }; | |
759 | int i; | |
760 | ||
761 | for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { | |
762 | if (hclk_mask == hclk_divisors[i]) { | |
763 | return i + 1; | |
764 | } | |
765 | } | |
766 | ||
32c54bd0 | 767 | aspeed_smc_error("invalid HCLK mask %x", hclk_mask); |
0d72c717 CLG |
768 | return 0; |
769 | } | |
770 | ||
771 | /* | |
772 | * When doing calibration, the SPI clock rate in the CE0 Control | |
773 | * Register and the read delay cycles in the Read Timing Compensation | |
774 | * Register are set using bit[11:4] of the DMA Control Register. | |
775 | */ | |
776 | static void aspeed_smc_dma_calibration(AspeedSMCState *s) | |
777 | { | |
778 | uint8_t delay = | |
779 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; | |
780 | uint8_t hclk_mask = | |
781 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; | |
782 | uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); | |
783 | uint32_t hclk_shift = (hclk_div - 1) << 2; | |
784 | uint8_t cs; | |
785 | ||
786 | /* | |
787 | * The Read Timing Compensation Register values apply to all CS on | |
788 | * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays | |
789 | */ | |
790 | if (hclk_div && hclk_div < 6) { | |
791 | s->regs[s->r_timings] &= ~(0xf << hclk_shift); | |
792 | s->regs[s->r_timings] |= delay << hclk_shift; | |
793 | } | |
794 | ||
795 | /* | |
796 | * TODO: compute the CS from the DMA address and the segment | |
797 | * registers. This is not really a problem for now because the | |
798 | * Timing Register values apply to all CS and software uses CS0 to | |
799 | * do calibration. | |
800 | */ | |
801 | cs = 0; | |
802 | s->regs[s->r_ctrl0 + cs] &= | |
803 | ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); | |
804 | s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); | |
805 | } | |
806 | ||
5258c2a6 CLG |
807 | /* |
808 | * Emulate read errors in the DMA Checksum Register for high | |
809 | * frequencies and optimistic settings of the Read Timing Compensation | |
810 | * Register. This will help in tuning the SPI timing calibration | |
811 | * algorithm. | |
812 | */ | |
813 | static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) | |
814 | { | |
815 | uint8_t delay = | |
816 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; | |
817 | uint8_t hclk_mask = | |
818 | (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; | |
819 | ||
820 | /* | |
821 | * Typical values of a palmetto-bmc machine. | |
822 | */ | |
823 | switch (aspeed_smc_hclk_divisor(hclk_mask)) { | |
824 | case 4 ... 16: | |
825 | return false; | |
826 | case 3: /* at least one HCLK cycle delay */ | |
827 | return (delay & 0x7) < 1; | |
828 | case 2: /* at least two HCLK cycle delay */ | |
829 | return (delay & 0x7) < 2; | |
830 | case 1: /* (> 100MHz) is above the max freq of the controller */ | |
831 | return true; | |
832 | default: | |
833 | g_assert_not_reached(); | |
834 | } | |
835 | } | |
836 | ||
c4e1f0b4 CLG |
837 | /* |
838 | * Accumulate the result of the reads to provide a checksum that will | |
839 | * be used to validate the read timing settings. | |
840 | */ | |
841 | static void aspeed_smc_dma_checksum(AspeedSMCState *s) | |
842 | { | |
843 | MemTxResult result; | |
844 | uint32_t data; | |
845 | ||
846 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { | |
32c54bd0 | 847 | aspeed_smc_error("invalid direction for DMA checksum"); |
c4e1f0b4 CLG |
848 | return; |
849 | } | |
850 | ||
0d72c717 CLG |
851 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { |
852 | aspeed_smc_dma_calibration(s); | |
853 | } | |
854 | ||
c4e1f0b4 CLG |
855 | while (s->regs[R_DMA_LEN]) { |
856 | data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], | |
857 | MEMTXATTRS_UNSPECIFIED, &result); | |
858 | if (result != MEMTX_OK) { | |
32c54bd0 CLG |
859 | aspeed_smc_error("Flash read failed @%08x", |
860 | s->regs[R_DMA_FLASH_ADDR]); | |
c4e1f0b4 CLG |
861 | return; |
862 | } | |
bd6ce9a6 | 863 | trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data); |
c4e1f0b4 CLG |
864 | |
865 | /* | |
866 | * When the DMA is on-going, the DMA registers are updated | |
867 | * with the current working addresses and length. | |
868 | */ | |
869 | s->regs[R_DMA_CHECKSUM] += data; | |
870 | s->regs[R_DMA_FLASH_ADDR] += 4; | |
871 | s->regs[R_DMA_LEN] -= 4; | |
872 | } | |
5258c2a6 CLG |
873 | |
874 | if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { | |
875 | s->regs[R_DMA_CHECKSUM] = 0xbadc0de; | |
876 | } | |
877 | ||
c4e1f0b4 CLG |
878 | } |
879 | ||
880 | static void aspeed_smc_dma_rw(AspeedSMCState *s) | |
881 | { | |
882 | MemTxResult result; | |
883 | uint32_t data; | |
884 | ||
4dabf395 CLG |
885 | trace_aspeed_smc_dma_rw(s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE ? |
886 | "write" : "read", | |
887 | s->regs[R_DMA_FLASH_ADDR], | |
888 | s->regs[R_DMA_DRAM_ADDR], | |
889 | s->regs[R_DMA_LEN]); | |
c4e1f0b4 CLG |
890 | while (s->regs[R_DMA_LEN]) { |
891 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { | |
892 | data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], | |
893 | MEMTXATTRS_UNSPECIFIED, &result); | |
894 | if (result != MEMTX_OK) { | |
32c54bd0 CLG |
895 | aspeed_smc_error("DRAM read failed @%08x", |
896 | s->regs[R_DMA_DRAM_ADDR]); | |
c4e1f0b4 CLG |
897 | return; |
898 | } | |
899 | ||
900 | address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], | |
901 | data, MEMTXATTRS_UNSPECIFIED, &result); | |
902 | if (result != MEMTX_OK) { | |
32c54bd0 CLG |
903 | aspeed_smc_error("Flash write failed @%08x", |
904 | s->regs[R_DMA_FLASH_ADDR]); | |
c4e1f0b4 CLG |
905 | return; |
906 | } | |
907 | } else { | |
908 | data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], | |
909 | MEMTXATTRS_UNSPECIFIED, &result); | |
910 | if (result != MEMTX_OK) { | |
32c54bd0 CLG |
911 | aspeed_smc_error("Flash read failed @%08x", |
912 | s->regs[R_DMA_FLASH_ADDR]); | |
c4e1f0b4 CLG |
913 | return; |
914 | } | |
915 | ||
916 | address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], | |
917 | data, MEMTXATTRS_UNSPECIFIED, &result); | |
918 | if (result != MEMTX_OK) { | |
32c54bd0 CLG |
919 | aspeed_smc_error("DRAM write failed @%08x", |
920 | s->regs[R_DMA_DRAM_ADDR]); | |
c4e1f0b4 CLG |
921 | return; |
922 | } | |
923 | } | |
924 | ||
925 | /* | |
926 | * When the DMA is on-going, the DMA registers are updated | |
927 | * with the current working addresses and length. | |
928 | */ | |
929 | s->regs[R_DMA_FLASH_ADDR] += 4; | |
930 | s->regs[R_DMA_DRAM_ADDR] += 4; | |
931 | s->regs[R_DMA_LEN] -= 4; | |
ae275f71 | 932 | s->regs[R_DMA_CHECKSUM] += data; |
c4e1f0b4 CLG |
933 | } |
934 | } | |
935 | ||
936 | static void aspeed_smc_dma_stop(AspeedSMCState *s) | |
937 | { | |
938 | /* | |
939 | * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the | |
940 | * engine is idle | |
941 | */ | |
942 | s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; | |
943 | s->regs[R_DMA_CHECKSUM] = 0; | |
944 | ||
945 | /* | |
946 | * Lower the DMA irq in any case. The IRQ control register could | |
947 | * have been cleared before disabling the DMA. | |
948 | */ | |
949 | qemu_irq_lower(s->irq); | |
950 | } | |
951 | ||
952 | /* | |
953 | * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA | |
954 | * can start even if the result of the previous was not collected. | |
955 | */ | |
956 | static bool aspeed_smc_dma_in_progress(AspeedSMCState *s) | |
957 | { | |
958 | return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && | |
959 | !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); | |
960 | } | |
961 | ||
962 | static void aspeed_smc_dma_done(AspeedSMCState *s) | |
963 | { | |
964 | s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; | |
965 | if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { | |
966 | qemu_irq_raise(s->irq); | |
967 | } | |
968 | } | |
969 | ||
1769a70e | 970 | static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) |
c4e1f0b4 CLG |
971 | { |
972 | if (!(dma_ctrl & DMA_CTRL_ENABLE)) { | |
973 | s->regs[R_DMA_CTRL] = dma_ctrl; | |
974 | ||
975 | aspeed_smc_dma_stop(s); | |
976 | return; | |
977 | } | |
978 | ||
979 | if (aspeed_smc_dma_in_progress(s)) { | |
32c54bd0 | 980 | aspeed_smc_error("DMA in progress !"); |
c4e1f0b4 CLG |
981 | return; |
982 | } | |
983 | ||
984 | s->regs[R_DMA_CTRL] = dma_ctrl; | |
985 | ||
986 | if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { | |
987 | aspeed_smc_dma_checksum(s); | |
988 | } else { | |
989 | aspeed_smc_dma_rw(s); | |
990 | } | |
991 | ||
992 | aspeed_smc_dma_done(s); | |
993 | } | |
994 | ||
1769a70e CLG |
995 | static inline bool aspeed_smc_dma_granted(AspeedSMCState *s) |
996 | { | |
30b6852c CLG |
997 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
998 | ||
999 | if (!(asc->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { | |
1769a70e CLG |
1000 | return true; |
1001 | } | |
1002 | ||
1003 | if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { | |
32c54bd0 | 1004 | aspeed_smc_error("DMA not granted"); |
1769a70e CLG |
1005 | return false; |
1006 | } | |
1007 | ||
1008 | return true; | |
1009 | } | |
1010 | ||
1011 | static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) | |
1012 | { | |
1013 | /* Preserve DMA bits */ | |
1014 | dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); | |
1015 | ||
1016 | if (dma_ctrl == 0xAEED0000) { | |
1017 | /* automatically grant request */ | |
1018 | s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); | |
1019 | return; | |
1020 | } | |
1021 | ||
1022 | /* clear request */ | |
1023 | if (dma_ctrl == 0xDEEA0000) { | |
1024 | s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); | |
1025 | return; | |
1026 | } | |
1027 | ||
1028 | if (!aspeed_smc_dma_granted(s)) { | |
32c54bd0 | 1029 | aspeed_smc_error("DMA not granted"); |
1769a70e CLG |
1030 | return; |
1031 | } | |
1032 | ||
1033 | aspeed_smc_dma_ctrl(s, dma_ctrl); | |
1034 | s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); | |
1035 | } | |
1036 | ||
7c1c69bc CLG |
1037 | static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, |
1038 | unsigned int size) | |
1039 | { | |
1040 | AspeedSMCState *s = ASPEED_SMC(opaque); | |
30b6852c | 1041 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
7c1c69bc CLG |
1042 | uint32_t value = data; |
1043 | ||
bd6ce9a6 CLG |
1044 | trace_aspeed_smc_write(addr, size, data); |
1045 | ||
e2804a1e CLG |
1046 | addr >>= 2; |
1047 | ||
97c2ed5d | 1048 | if (addr == s->r_conf || |
f286f04c | 1049 | (addr >= s->r_timings && |
30b6852c | 1050 | addr < s->r_timings + asc->nregs_timings) || |
97c2ed5d CLG |
1051 | addr == s->r_ce_ctrl) { |
1052 | s->regs[addr] = value; | |
ae945a00 | 1053 | } else if (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + asc->cs_num_max) { |
f248a9db | 1054 | int cs = addr - s->r_ctrl0; |
e7e741ca | 1055 | aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); |
a03cb1da | 1056 | } else if (addr >= R_SEG_ADDR0 && |
ae945a00 | 1057 | addr < R_SEG_ADDR0 + asc->cs_num_max) { |
a03cb1da CLG |
1058 | int cs = addr - R_SEG_ADDR0; |
1059 | ||
1060 | if (value != s->regs[R_SEG_ADDR0 + cs]) { | |
1061 | aspeed_smc_flash_set_segment(s, cs, value); | |
1062 | } | |
af453a5e CLG |
1063 | } else if (addr == R_CE_CMD_CTRL) { |
1064 | s->regs[addr] = value & 0xff; | |
9149af2a CLG |
1065 | } else if (addr == R_DUMMY_DATA) { |
1066 | s->regs[addr] = value & 0xff; | |
30b6852c | 1067 | } else if (aspeed_smc_has_wdt_control(asc) && addr == R_FMC_WDT2_CTRL) { |
45a904af | 1068 | s->regs[addr] = value & FMC_WDT2_CTRL_EN; |
c4e1f0b4 CLG |
1069 | } else if (addr == R_INTR_CTRL) { |
1070 | s->regs[addr] = value; | |
30b6852c CLG |
1071 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_CTRL) { |
1072 | asc->dma_ctrl(s, value); | |
1073 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_DRAM_ADDR && | |
1769a70e | 1074 | aspeed_smc_dma_granted(s)) { |
30b6852c CLG |
1075 | s->regs[addr] = DMA_DRAM_ADDR(asc, value); |
1076 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_FLASH_ADDR && | |
1769a70e | 1077 | aspeed_smc_dma_granted(s)) { |
30b6852c CLG |
1078 | s->regs[addr] = DMA_FLASH_ADDR(asc, value); |
1079 | } else if (aspeed_smc_has_dma(asc) && addr == R_DMA_LEN && | |
1769a70e | 1080 | aspeed_smc_dma_granted(s)) { |
c4e1f0b4 | 1081 | s->regs[addr] = DMA_LENGTH(value); |
97c2ed5d | 1082 | } else { |
7c1c69bc CLG |
1083 | qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", |
1084 | __func__, addr); | |
1085 | return; | |
1086 | } | |
7c1c69bc CLG |
1087 | } |
1088 | ||
1089 | static const MemoryRegionOps aspeed_smc_ops = { | |
1090 | .read = aspeed_smc_read, | |
1091 | .write = aspeed_smc_write, | |
1092 | .endianness = DEVICE_LITTLE_ENDIAN, | |
7c1c69bc CLG |
1093 | }; |
1094 | ||
f75b5331 CLG |
1095 | static void aspeed_smc_instance_init(Object *obj) |
1096 | { | |
1097 | AspeedSMCState *s = ASPEED_SMC(obj); | |
1098 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); | |
1099 | int i; | |
1100 | ||
ae945a00 | 1101 | for (i = 0; i < asc->cs_num_max; i++) { |
f75b5331 CLG |
1102 | object_initialize_child(obj, "flash[*]", &s->flashes[i], |
1103 | TYPE_ASPEED_SMC_FLASH); | |
1104 | } | |
1105 | } | |
1106 | ||
c4e1f0b4 CLG |
1107 | /* |
1108 | * Initialize the custom address spaces for DMAs | |
1109 | */ | |
1110 | static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp) | |
1111 | { | |
c4e1f0b4 CLG |
1112 | if (!s->dram_mr) { |
1113 | error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set"); | |
1114 | return; | |
1115 | } | |
1116 | ||
d0180a3a CLG |
1117 | address_space_init(&s->flash_as, &s->mmio_flash, |
1118 | TYPE_ASPEED_SMC ".dma-flash"); | |
1119 | address_space_init(&s->dram_as, s->dram_mr, | |
1120 | TYPE_ASPEED_SMC ".dma-dram"); | |
c4e1f0b4 CLG |
1121 | } |
1122 | ||
7c1c69bc CLG |
1123 | static void aspeed_smc_realize(DeviceState *dev, Error **errp) |
1124 | { | |
1125 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
1126 | AspeedSMCState *s = ASPEED_SMC(dev); | |
30b6852c | 1127 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); |
7c1c69bc | 1128 | int i; |
924ed163 | 1129 | hwaddr offset = 0; |
7c1c69bc | 1130 | |
7c1c69bc | 1131 | /* keep a copy under AspeedSMCState to speed up accesses */ |
30b6852c CLG |
1132 | s->r_conf = asc->r_conf; |
1133 | s->r_ce_ctrl = asc->r_ce_ctrl; | |
1134 | s->r_ctrl0 = asc->r_ctrl0; | |
1135 | s->r_timings = asc->r_timings; | |
1136 | s->conf_enable_w0 = asc->conf_enable_w0; | |
7c1c69bc | 1137 | |
c4e1f0b4 CLG |
1138 | /* DMA irq. Keep it first for the initialization in the SoC */ |
1139 | sysbus_init_irq(sbd, &s->irq); | |
1140 | ||
9bbdfe05 | 1141 | s->spi = ssi_create_bus(dev, NULL); |
7c1c69bc | 1142 | |
5ade579b | 1143 | /* Setup cs_lines for peripherals */ |
ae945a00 | 1144 | s->cs_lines = g_new0(qemu_irq, asc->cs_num_max); |
b22a2d40 | 1145 | qdev_init_gpio_out_named(DEVICE(s), s->cs_lines, "cs", asc->cs_num_max); |
7c1c69bc | 1146 | |
2da95fd8 | 1147 | /* The memory region for the controller registers */ |
7c1c69bc | 1148 | memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_ops, s, |
30b6852c | 1149 | TYPE_ASPEED_SMC, asc->nregs * 4); |
7c1c69bc | 1150 | sysbus_init_mmio(sbd, &s->mmio); |
924ed163 CLG |
1151 | |
1152 | /* | |
2da95fd8 CLG |
1153 | * The container memory region representing the address space |
1154 | * window in which the flash modules are mapped. The size and | |
1155 | * address depends on the SoC model and controller type. | |
924ed163 | 1156 | */ |
fc664254 CLG |
1157 | memory_region_init(&s->mmio_flash_container, OBJECT(s), |
1158 | TYPE_ASPEED_SMC ".container", | |
1159 | asc->flash_window_size); | |
1160 | sysbus_init_mmio(sbd, &s->mmio_flash_container); | |
1161 | ||
924ed163 | 1162 | memory_region_init_io(&s->mmio_flash, OBJECT(s), |
d0180a3a CLG |
1163 | &aspeed_smc_flash_default_ops, s, |
1164 | TYPE_ASPEED_SMC ".flash", | |
30b6852c | 1165 | asc->flash_window_size); |
fc664254 CLG |
1166 | memory_region_add_subregion(&s->mmio_flash_container, 0x0, |
1167 | &s->mmio_flash); | |
924ed163 | 1168 | |
2da95fd8 | 1169 | /* |
5ade579b | 1170 | * Let's create a sub memory region for each possible peripheral. All |
2da95fd8 CLG |
1171 | * have a configurable memory segment in the overall flash mapping |
1172 | * window of the controller but, there is not necessarily a flash | |
1173 | * module behind to handle the memory accesses. This depends on | |
1174 | * the board configuration. | |
1175 | */ | |
ae945a00 | 1176 | for (i = 0; i < asc->cs_num_max; ++i) { |
924ed163 CLG |
1177 | AspeedSMCFlash *fl = &s->flashes[i]; |
1178 | ||
f75b5331 CLG |
1179 | if (!object_property_set_link(OBJECT(fl), "controller", OBJECT(s), |
1180 | errp)) { | |
1181 | return; | |
1182 | } | |
1183 | if (!object_property_set_uint(OBJECT(fl), "cs", i, errp)) { | |
1184 | return; | |
1185 | } | |
1186 | if (!sysbus_realize(SYS_BUS_DEVICE(fl), errp)) { | |
1187 | return; | |
1188 | } | |
924ed163 | 1189 | |
924ed163 | 1190 | memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); |
6bb55e79 | 1191 | offset += asc->segments[i].size; |
924ed163 | 1192 | } |
c4e1f0b4 CLG |
1193 | |
1194 | /* DMA support */ | |
30b6852c | 1195 | if (aspeed_smc_has_dma(asc)) { |
c4e1f0b4 CLG |
1196 | aspeed_smc_dma_setup(s, errp); |
1197 | } | |
7c1c69bc CLG |
1198 | } |
1199 | ||
1200 | static const VMStateDescription vmstate_aspeed_smc = { | |
1201 | .name = "aspeed.smc", | |
f95c4bff CLG |
1202 | .version_id = 2, |
1203 | .minimum_version_id = 2, | |
0aa6c7df | 1204 | .fields = (const VMStateField[]) { |
7c1c69bc | 1205 | VMSTATE_UINT32_ARRAY(regs, AspeedSMCState, ASPEED_SMC_R_MAX), |
f95c4bff CLG |
1206 | VMSTATE_UINT8(snoop_index, AspeedSMCState), |
1207 | VMSTATE_UINT8(snoop_dummies, AspeedSMCState), | |
7c1c69bc CLG |
1208 | VMSTATE_END_OF_LIST() |
1209 | } | |
1210 | }; | |
1211 | ||
1212 | static Property aspeed_smc_properties[] = { | |
5258c2a6 | 1213 | DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), |
c4e1f0b4 CLG |
1214 | DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, |
1215 | TYPE_MEMORY_REGION, MemoryRegion *), | |
7c1c69bc CLG |
1216 | DEFINE_PROP_END_OF_LIST(), |
1217 | }; | |
1218 | ||
1219 | static void aspeed_smc_class_init(ObjectClass *klass, void *data) | |
1220 | { | |
1221 | DeviceClass *dc = DEVICE_CLASS(klass); | |
7c1c69bc CLG |
1222 | |
1223 | dc->realize = aspeed_smc_realize; | |
1224 | dc->reset = aspeed_smc_reset; | |
4f67d30b | 1225 | device_class_set_props(dc, aspeed_smc_properties); |
7c1c69bc | 1226 | dc->vmsd = &vmstate_aspeed_smc; |
7c1c69bc CLG |
1227 | } |
1228 | ||
1229 | static const TypeInfo aspeed_smc_info = { | |
1230 | .name = TYPE_ASPEED_SMC, | |
1231 | .parent = TYPE_SYS_BUS_DEVICE, | |
f75b5331 | 1232 | .instance_init = aspeed_smc_instance_init, |
7c1c69bc CLG |
1233 | .instance_size = sizeof(AspeedSMCState), |
1234 | .class_size = sizeof(AspeedSMCClass), | |
30b6852c | 1235 | .class_init = aspeed_smc_class_init, |
7c1c69bc CLG |
1236 | .abstract = true, |
1237 | }; | |
1238 | ||
f75b5331 CLG |
1239 | static void aspeed_smc_flash_realize(DeviceState *dev, Error **errp) |
1240 | { | |
1241 | AspeedSMCFlash *s = ASPEED_SMC_FLASH(dev); | |
f75b5331 CLG |
1242 | g_autofree char *name = g_strdup_printf(TYPE_ASPEED_SMC_FLASH ".%d", s->cs); |
1243 | ||
1244 | if (!s->controller) { | |
1245 | error_setg(errp, TYPE_ASPEED_SMC_FLASH ": 'controller' link not set"); | |
1246 | return; | |
1247 | } | |
1248 | ||
b84a9482 | 1249 | s->asc = ASPEED_SMC_GET_CLASS(s->controller); |
f75b5331 CLG |
1250 | |
1251 | /* | |
1252 | * Use the default segment value to size the memory region. This | |
1253 | * can be changed by FW at runtime. | |
1254 | */ | |
1255 | memory_region_init_io(&s->mmio, OBJECT(s), &aspeed_smc_flash_ops, | |
b84a9482 | 1256 | s, name, s->asc->segments[s->cs].size); |
f75b5331 CLG |
1257 | sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); |
1258 | } | |
1259 | ||
1260 | static Property aspeed_smc_flash_properties[] = { | |
1261 | DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0), | |
1262 | DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC, | |
1263 | AspeedSMCState *), | |
1264 | DEFINE_PROP_END_OF_LIST(), | |
1265 | }; | |
1266 | ||
1267 | static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data) | |
1268 | { | |
1269 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1270 | ||
1271 | dc->desc = "Aspeed SMC Flash device region"; | |
1272 | dc->realize = aspeed_smc_flash_realize; | |
1273 | device_class_set_props(dc, aspeed_smc_flash_properties); | |
1274 | } | |
1275 | ||
1276 | static const TypeInfo aspeed_smc_flash_info = { | |
1277 | .name = TYPE_ASPEED_SMC_FLASH, | |
1278 | .parent = TYPE_SYS_BUS_DEVICE, | |
1279 | .instance_size = sizeof(AspeedSMCFlash), | |
1280 | .class_init = aspeed_smc_flash_class_init, | |
1281 | }; | |
30b6852c CLG |
1282 | |
1283 | /* | |
1284 | * The Segment Registers of the AST2400 and AST2500 have a 8MB | |
1285 | * unit. The address range of a flash SPI peripheral is encoded with | |
1286 | * absolute addresses which should be part of the overall controller | |
1287 | * window. | |
1288 | */ | |
1289 | static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, | |
1290 | const AspeedSegments *seg) | |
7c1c69bc | 1291 | { |
30b6852c CLG |
1292 | uint32_t reg = 0; |
1293 | reg |= ((seg->addr >> 23) & SEG_START_MASK) << SEG_START_SHIFT; | |
1294 | reg |= (((seg->addr + seg->size) >> 23) & SEG_END_MASK) << SEG_END_SHIFT; | |
1295 | return reg; | |
1296 | } | |
7c1c69bc | 1297 | |
30b6852c CLG |
1298 | static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, |
1299 | uint32_t reg, AspeedSegments *seg) | |
1300 | { | |
1301 | seg->addr = ((reg >> SEG_START_SHIFT) & SEG_START_MASK) << 23; | |
1302 | seg->size = (((reg >> SEG_END_SHIFT) & SEG_END_MASK) << 23) - seg->addr; | |
1303 | } | |
1304 | ||
1305 | static const AspeedSegments aspeed_2400_smc_segments[] = { | |
1306 | { 0x10000000, 32 * MiB }, | |
1307 | }; | |
1308 | ||
1309 | static void aspeed_2400_smc_class_init(ObjectClass *klass, void *data) | |
1310 | { | |
1311 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1312 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1313 | ||
1314 | dc->desc = "Aspeed 2400 SMC Controller"; | |
1315 | asc->r_conf = R_CONF; | |
1316 | asc->r_ce_ctrl = R_CE_CTRL; | |
1317 | asc->r_ctrl0 = R_CTRL0; | |
1318 | asc->r_timings = R_TIMINGS; | |
1319 | asc->nregs_timings = 1; | |
1320 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1321 | asc->cs_num_max = 1; |
30b6852c CLG |
1322 | asc->segments = aspeed_2400_smc_segments; |
1323 | asc->flash_window_base = 0x10000000; | |
1324 | asc->flash_window_size = 0x6000000; | |
1325 | asc->features = 0x0; | |
1326 | asc->nregs = ASPEED_SMC_R_SMC_MAX; | |
1327 | asc->segment_to_reg = aspeed_smc_segment_to_reg; | |
1328 | asc->reg_to_segment = aspeed_smc_reg_to_segment; | |
1329 | asc->dma_ctrl = aspeed_smc_dma_ctrl; | |
1330 | } | |
1331 | ||
1332 | static const TypeInfo aspeed_2400_smc_info = { | |
1333 | .name = "aspeed.smc-ast2400", | |
1334 | .parent = TYPE_ASPEED_SMC, | |
1335 | .class_init = aspeed_2400_smc_class_init, | |
1336 | }; | |
1337 | ||
71255c48 CLG |
1338 | static const uint32_t aspeed_2400_fmc_resets[ASPEED_SMC_R_MAX] = { |
1339 | /* | |
1340 | * CE0 and CE1 types are HW strapped in SCU70. Do it here to | |
1341 | * simplify the model. | |
1342 | */ | |
1343 | [R_CONF] = CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0, | |
1344 | }; | |
1345 | ||
30b6852c CLG |
1346 | static const AspeedSegments aspeed_2400_fmc_segments[] = { |
1347 | { 0x20000000, 64 * MiB }, /* start address is readonly */ | |
1348 | { 0x24000000, 32 * MiB }, | |
1349 | { 0x26000000, 32 * MiB }, | |
1350 | { 0x28000000, 32 * MiB }, | |
1351 | { 0x2A000000, 32 * MiB } | |
1352 | }; | |
1353 | ||
1354 | static void aspeed_2400_fmc_class_init(ObjectClass *klass, void *data) | |
1355 | { | |
1356 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1357 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1358 | ||
1359 | dc->desc = "Aspeed 2400 FMC Controller"; | |
1360 | asc->r_conf = R_CONF; | |
1361 | asc->r_ce_ctrl = R_CE_CTRL; | |
1362 | asc->r_ctrl0 = R_CTRL0; | |
1363 | asc->r_timings = R_TIMINGS; | |
1364 | asc->nregs_timings = 1; | |
1365 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1366 | asc->cs_num_max = 5; |
30b6852c | 1367 | asc->segments = aspeed_2400_fmc_segments; |
7c8d2fc4 | 1368 | asc->segment_addr_mask = 0xffff0000; |
71255c48 | 1369 | asc->resets = aspeed_2400_fmc_resets; |
30b6852c CLG |
1370 | asc->flash_window_base = 0x20000000; |
1371 | asc->flash_window_size = 0x10000000; | |
1372 | asc->features = ASPEED_SMC_FEATURE_DMA; | |
1373 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1374 | asc->dma_dram_mask = 0x1FFFFFFC; | |
1375 | asc->nregs = ASPEED_SMC_R_MAX; | |
1376 | asc->segment_to_reg = aspeed_smc_segment_to_reg; | |
1377 | asc->reg_to_segment = aspeed_smc_reg_to_segment; | |
1378 | asc->dma_ctrl = aspeed_smc_dma_ctrl; | |
1379 | } | |
1380 | ||
1381 | static const TypeInfo aspeed_2400_fmc_info = { | |
1382 | .name = "aspeed.fmc-ast2400", | |
1383 | .parent = TYPE_ASPEED_SMC, | |
1384 | .class_init = aspeed_2400_fmc_class_init, | |
1385 | }; | |
1386 | ||
1387 | static const AspeedSegments aspeed_2400_spi1_segments[] = { | |
1388 | { 0x30000000, 64 * MiB }, | |
1389 | }; | |
1390 | ||
a779e37c CLG |
1391 | static int aspeed_2400_spi1_addr_width(const AspeedSMCState *s) |
1392 | { | |
1393 | return s->regs[R_SPI_CTRL0] & CTRL_AST2400_SPI_4BYTE ? 4 : 3; | |
1394 | } | |
1395 | ||
30b6852c CLG |
1396 | static void aspeed_2400_spi1_class_init(ObjectClass *klass, void *data) |
1397 | { | |
1398 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1399 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1400 | ||
1401 | dc->desc = "Aspeed 2400 SPI1 Controller"; | |
1402 | asc->r_conf = R_SPI_CONF; | |
1403 | asc->r_ce_ctrl = 0xff; | |
1404 | asc->r_ctrl0 = R_SPI_CTRL0; | |
1405 | asc->r_timings = R_SPI_TIMINGS; | |
1406 | asc->nregs_timings = 1; | |
1407 | asc->conf_enable_w0 = SPI_CONF_ENABLE_W0; | |
ae945a00 | 1408 | asc->cs_num_max = 1; |
30b6852c CLG |
1409 | asc->segments = aspeed_2400_spi1_segments; |
1410 | asc->flash_window_base = 0x30000000; | |
1411 | asc->flash_window_size = 0x10000000; | |
1412 | asc->features = 0x0; | |
1413 | asc->nregs = ASPEED_SMC_R_SPI_MAX; | |
1414 | asc->segment_to_reg = aspeed_smc_segment_to_reg; | |
1415 | asc->reg_to_segment = aspeed_smc_reg_to_segment; | |
1416 | asc->dma_ctrl = aspeed_smc_dma_ctrl; | |
a779e37c | 1417 | asc->addr_width = aspeed_2400_spi1_addr_width; |
30b6852c CLG |
1418 | } |
1419 | ||
1420 | static const TypeInfo aspeed_2400_spi1_info = { | |
1421 | .name = "aspeed.spi1-ast2400", | |
1422 | .parent = TYPE_ASPEED_SMC, | |
1423 | .class_init = aspeed_2400_spi1_class_init, | |
1424 | }; | |
1425 | ||
71255c48 CLG |
1426 | static const uint32_t aspeed_2500_fmc_resets[ASPEED_SMC_R_MAX] = { |
1427 | [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | | |
1428 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), | |
1429 | }; | |
1430 | ||
30b6852c CLG |
1431 | static const AspeedSegments aspeed_2500_fmc_segments[] = { |
1432 | { 0x20000000, 128 * MiB }, /* start address is readonly */ | |
1433 | { 0x28000000, 32 * MiB }, | |
1434 | { 0x2A000000, 32 * MiB }, | |
1435 | }; | |
1436 | ||
1437 | static void aspeed_2500_fmc_class_init(ObjectClass *klass, void *data) | |
1438 | { | |
1439 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1440 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1441 | ||
1442 | dc->desc = "Aspeed 2600 FMC Controller"; | |
1443 | asc->r_conf = R_CONF; | |
1444 | asc->r_ce_ctrl = R_CE_CTRL; | |
1445 | asc->r_ctrl0 = R_CTRL0; | |
1446 | asc->r_timings = R_TIMINGS; | |
1447 | asc->nregs_timings = 1; | |
1448 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1449 | asc->cs_num_max = 3; |
30b6852c | 1450 | asc->segments = aspeed_2500_fmc_segments; |
7c8d2fc4 | 1451 | asc->segment_addr_mask = 0xffff0000; |
71255c48 | 1452 | asc->resets = aspeed_2500_fmc_resets; |
30b6852c CLG |
1453 | asc->flash_window_base = 0x20000000; |
1454 | asc->flash_window_size = 0x10000000; | |
1455 | asc->features = ASPEED_SMC_FEATURE_DMA; | |
1456 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1457 | asc->dma_dram_mask = 0x3FFFFFFC; | |
1458 | asc->nregs = ASPEED_SMC_R_MAX; | |
1459 | asc->segment_to_reg = aspeed_smc_segment_to_reg; | |
1460 | asc->reg_to_segment = aspeed_smc_reg_to_segment; | |
1461 | asc->dma_ctrl = aspeed_smc_dma_ctrl; | |
1462 | } | |
1463 | ||
1464 | static const TypeInfo aspeed_2500_fmc_info = { | |
1465 | .name = "aspeed.fmc-ast2500", | |
1466 | .parent = TYPE_ASPEED_SMC, | |
1467 | .class_init = aspeed_2500_fmc_class_init, | |
1468 | }; | |
1469 | ||
1470 | static const AspeedSegments aspeed_2500_spi1_segments[] = { | |
1471 | { 0x30000000, 32 * MiB }, /* start address is readonly */ | |
1472 | { 0x32000000, 96 * MiB }, /* end address is readonly */ | |
1473 | }; | |
1474 | ||
1475 | static void aspeed_2500_spi1_class_init(ObjectClass *klass, void *data) | |
1476 | { | |
1477 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1478 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1479 | ||
1480 | dc->desc = "Aspeed 2600 SPI1 Controller"; | |
1481 | asc->r_conf = R_CONF; | |
1482 | asc->r_ce_ctrl = R_CE_CTRL; | |
1483 | asc->r_ctrl0 = R_CTRL0; | |
1484 | asc->r_timings = R_TIMINGS; | |
1485 | asc->nregs_timings = 1; | |
1486 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1487 | asc->cs_num_max = 2; |
30b6852c | 1488 | asc->segments = aspeed_2500_spi1_segments; |
7c8d2fc4 | 1489 | asc->segment_addr_mask = 0xffff0000; |
30b6852c CLG |
1490 | asc->flash_window_base = 0x30000000; |
1491 | asc->flash_window_size = 0x8000000; | |
1492 | asc->features = 0x0; | |
1493 | asc->nregs = ASPEED_SMC_R_MAX; | |
1494 | asc->segment_to_reg = aspeed_smc_segment_to_reg; | |
1495 | asc->reg_to_segment = aspeed_smc_reg_to_segment; | |
1496 | asc->dma_ctrl = aspeed_smc_dma_ctrl; | |
1497 | } | |
1498 | ||
1499 | static const TypeInfo aspeed_2500_spi1_info = { | |
1500 | .name = "aspeed.spi1-ast2500", | |
1501 | .parent = TYPE_ASPEED_SMC, | |
1502 | .class_init = aspeed_2500_spi1_class_init, | |
1503 | }; | |
1504 | ||
1505 | static const AspeedSegments aspeed_2500_spi2_segments[] = { | |
1506 | { 0x38000000, 32 * MiB }, /* start address is readonly */ | |
1507 | { 0x3A000000, 96 * MiB }, /* end address is readonly */ | |
1508 | }; | |
1509 | ||
1510 | static void aspeed_2500_spi2_class_init(ObjectClass *klass, void *data) | |
1511 | { | |
1512 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1513 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1514 | ||
1515 | dc->desc = "Aspeed 2600 SPI2 Controller"; | |
1516 | asc->r_conf = R_CONF; | |
1517 | asc->r_ce_ctrl = R_CE_CTRL; | |
1518 | asc->r_ctrl0 = R_CTRL0; | |
1519 | asc->r_timings = R_TIMINGS; | |
1520 | asc->nregs_timings = 1; | |
1521 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1522 | asc->cs_num_max = 2; |
30b6852c | 1523 | asc->segments = aspeed_2500_spi2_segments; |
7c8d2fc4 | 1524 | asc->segment_addr_mask = 0xffff0000; |
30b6852c CLG |
1525 | asc->flash_window_base = 0x38000000; |
1526 | asc->flash_window_size = 0x8000000; | |
1527 | asc->features = 0x0; | |
1528 | asc->nregs = ASPEED_SMC_R_MAX; | |
1529 | asc->segment_to_reg = aspeed_smc_segment_to_reg; | |
1530 | asc->reg_to_segment = aspeed_smc_reg_to_segment; | |
1531 | asc->dma_ctrl = aspeed_smc_dma_ctrl; | |
1532 | } | |
1533 | ||
1534 | static const TypeInfo aspeed_2500_spi2_info = { | |
1535 | .name = "aspeed.spi2-ast2500", | |
1536 | .parent = TYPE_ASPEED_SMC, | |
1537 | .class_init = aspeed_2500_spi2_class_init, | |
1538 | }; | |
1539 | ||
1540 | /* | |
1541 | * The Segment Registers of the AST2600 have a 1MB unit. The address | |
1542 | * range of a flash SPI peripheral is encoded with offsets in the overall | |
1543 | * controller window. The previous SoC AST2400 and AST2500 used | |
1544 | * absolute addresses. Only bits [27:20] are relevant and the end | |
1545 | * address is an upper bound limit. | |
1546 | */ | |
1547 | #define AST2600_SEG_ADDR_MASK 0x0ff00000 | |
1548 | ||
1549 | static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, | |
1550 | const AspeedSegments *seg) | |
1551 | { | |
1552 | uint32_t reg = 0; | |
1553 | ||
1554 | /* Disabled segments have a nil register */ | |
1555 | if (!seg->size) { | |
1556 | return 0; | |
1557 | } | |
1558 | ||
1559 | reg |= (seg->addr & AST2600_SEG_ADDR_MASK) >> 16; /* start offset */ | |
1560 | reg |= (seg->addr + seg->size - 1) & AST2600_SEG_ADDR_MASK; /* end offset */ | |
1561 | return reg; | |
1562 | } | |
1563 | ||
1564 | static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, | |
1565 | uint32_t reg, AspeedSegments *seg) | |
1566 | { | |
1567 | uint32_t start_offset = (reg << 16) & AST2600_SEG_ADDR_MASK; | |
1568 | uint32_t end_offset = reg & AST2600_SEG_ADDR_MASK; | |
1569 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); | |
1570 | ||
1571 | if (reg) { | |
1572 | seg->addr = asc->flash_window_base + start_offset; | |
1573 | seg->size = end_offset + MiB - start_offset; | |
1574 | } else { | |
1575 | seg->addr = asc->flash_window_base; | |
1576 | seg->size = 0; | |
7c1c69bc CLG |
1577 | } |
1578 | } | |
1579 | ||
71255c48 CLG |
1580 | static const uint32_t aspeed_2600_fmc_resets[ASPEED_SMC_R_MAX] = { |
1581 | [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | | |
1582 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1 | | |
1583 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE2), | |
1584 | }; | |
1585 | ||
30b6852c CLG |
1586 | static const AspeedSegments aspeed_2600_fmc_segments[] = { |
1587 | { 0x0, 128 * MiB }, /* start address is readonly */ | |
1588 | { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ | |
1589 | { 0x0, 0 }, /* disabled */ | |
1590 | }; | |
1591 | ||
1592 | static void aspeed_2600_fmc_class_init(ObjectClass *klass, void *data) | |
1593 | { | |
1594 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1595 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1596 | ||
1597 | dc->desc = "Aspeed 2600 FMC Controller"; | |
1598 | asc->r_conf = R_CONF; | |
1599 | asc->r_ce_ctrl = R_CE_CTRL; | |
1600 | asc->r_ctrl0 = R_CTRL0; | |
1601 | asc->r_timings = R_TIMINGS; | |
1602 | asc->nregs_timings = 1; | |
1603 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1604 | asc->cs_num_max = 3; |
30b6852c | 1605 | asc->segments = aspeed_2600_fmc_segments; |
7c8d2fc4 | 1606 | asc->segment_addr_mask = 0x0ff00ff0; |
71255c48 | 1607 | asc->resets = aspeed_2600_fmc_resets; |
30b6852c CLG |
1608 | asc->flash_window_base = 0x20000000; |
1609 | asc->flash_window_size = 0x10000000; | |
1610 | asc->features = ASPEED_SMC_FEATURE_DMA | | |
1611 | ASPEED_SMC_FEATURE_WDT_CONTROL; | |
1612 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1613 | asc->dma_dram_mask = 0x3FFFFFFC; | |
1614 | asc->nregs = ASPEED_SMC_R_MAX; | |
1615 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; | |
1616 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; | |
1617 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; | |
1618 | } | |
1619 | ||
1620 | static const TypeInfo aspeed_2600_fmc_info = { | |
1621 | .name = "aspeed.fmc-ast2600", | |
1622 | .parent = TYPE_ASPEED_SMC, | |
1623 | .class_init = aspeed_2600_fmc_class_init, | |
1624 | }; | |
1625 | ||
1626 | static const AspeedSegments aspeed_2600_spi1_segments[] = { | |
1627 | { 0x0, 128 * MiB }, /* start address is readonly */ | |
1628 | { 0x0, 0 }, /* disabled */ | |
1629 | }; | |
1630 | ||
1631 | static void aspeed_2600_spi1_class_init(ObjectClass *klass, void *data) | |
1632 | { | |
1633 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1634 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1635 | ||
1636 | dc->desc = "Aspeed 2600 SPI1 Controller"; | |
1637 | asc->r_conf = R_CONF; | |
1638 | asc->r_ce_ctrl = R_CE_CTRL; | |
1639 | asc->r_ctrl0 = R_CTRL0; | |
1640 | asc->r_timings = R_TIMINGS; | |
1641 | asc->nregs_timings = 2; | |
1642 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1643 | asc->cs_num_max = 2; |
30b6852c | 1644 | asc->segments = aspeed_2600_spi1_segments; |
7c8d2fc4 | 1645 | asc->segment_addr_mask = 0x0ff00ff0; |
30b6852c CLG |
1646 | asc->flash_window_base = 0x30000000; |
1647 | asc->flash_window_size = 0x10000000; | |
1648 | asc->features = ASPEED_SMC_FEATURE_DMA | | |
1649 | ASPEED_SMC_FEATURE_DMA_GRANT; | |
1650 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1651 | asc->dma_dram_mask = 0x3FFFFFFC; | |
1652 | asc->nregs = ASPEED_SMC_R_MAX; | |
1653 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; | |
1654 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; | |
1655 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; | |
1656 | } | |
1657 | ||
1658 | static const TypeInfo aspeed_2600_spi1_info = { | |
1659 | .name = "aspeed.spi1-ast2600", | |
1660 | .parent = TYPE_ASPEED_SMC, | |
1661 | .class_init = aspeed_2600_spi1_class_init, | |
1662 | }; | |
1663 | ||
1664 | static const AspeedSegments aspeed_2600_spi2_segments[] = { | |
1665 | { 0x0, 128 * MiB }, /* start address is readonly */ | |
1666 | { 0x0, 0 }, /* disabled */ | |
1667 | { 0x0, 0 }, /* disabled */ | |
1668 | }; | |
1669 | ||
1670 | static void aspeed_2600_spi2_class_init(ObjectClass *klass, void *data) | |
1671 | { | |
1672 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1673 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1674 | ||
1675 | dc->desc = "Aspeed 2600 SPI2 Controller"; | |
1676 | asc->r_conf = R_CONF; | |
1677 | asc->r_ce_ctrl = R_CE_CTRL; | |
1678 | asc->r_ctrl0 = R_CTRL0; | |
1679 | asc->r_timings = R_TIMINGS; | |
1680 | asc->nregs_timings = 3; | |
1681 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
ae945a00 | 1682 | asc->cs_num_max = 3; |
30b6852c | 1683 | asc->segments = aspeed_2600_spi2_segments; |
7c8d2fc4 | 1684 | asc->segment_addr_mask = 0x0ff00ff0; |
30b6852c CLG |
1685 | asc->flash_window_base = 0x50000000; |
1686 | asc->flash_window_size = 0x10000000; | |
1687 | asc->features = ASPEED_SMC_FEATURE_DMA | | |
1688 | ASPEED_SMC_FEATURE_DMA_GRANT; | |
1689 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1690 | asc->dma_dram_mask = 0x3FFFFFFC; | |
1691 | asc->nregs = ASPEED_SMC_R_MAX; | |
1692 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; | |
1693 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; | |
1694 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; | |
1695 | } | |
1696 | ||
1697 | static const TypeInfo aspeed_2600_spi2_info = { | |
1698 | .name = "aspeed.spi2-ast2600", | |
1699 | .parent = TYPE_ASPEED_SMC, | |
1700 | .class_init = aspeed_2600_spi2_class_init, | |
1701 | }; | |
1702 | ||
2850df6a SL |
1703 | /* |
1704 | * The FMC Segment Registers of the AST1030 have a 512KB unit. | |
1705 | * Only bits [27:19] are used for decoding. | |
1706 | */ | |
1707 | #define AST1030_SEG_ADDR_MASK 0x0ff80000 | |
1708 | ||
1709 | static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s, | |
1710 | const AspeedSegments *seg) | |
1711 | { | |
1712 | uint32_t reg = 0; | |
1713 | ||
1714 | /* Disabled segments have a nil register */ | |
1715 | if (!seg->size) { | |
1716 | return 0; | |
1717 | } | |
1718 | ||
1719 | reg |= (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ | |
1720 | reg |= (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end offset */ | |
1721 | return reg; | |
1722 | } | |
1723 | ||
1724 | static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s, | |
1725 | uint32_t reg, AspeedSegments *seg) | |
1726 | { | |
1727 | uint32_t start_offset = (reg << 16) & AST1030_SEG_ADDR_MASK; | |
1728 | uint32_t end_offset = reg & AST1030_SEG_ADDR_MASK; | |
1729 | AspeedSMCClass *asc = ASPEED_SMC_GET_CLASS(s); | |
1730 | ||
1731 | if (reg) { | |
1732 | seg->addr = asc->flash_window_base + start_offset; | |
1733 | seg->size = end_offset + (512 * KiB) - start_offset; | |
1734 | } else { | |
1735 | seg->addr = asc->flash_window_base; | |
1736 | seg->size = 0; | |
1737 | } | |
1738 | } | |
1739 | ||
1740 | static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] = { | |
1741 | [R_CONF] = (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | | |
1742 | CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), | |
1743 | }; | |
1744 | ||
1745 | static const AspeedSegments aspeed_1030_fmc_segments[] = { | |
1746 | { 0x0, 128 * MiB }, /* start address is readonly */ | |
1747 | { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kernel */ | |
1748 | { 0x0, 0 }, /* disabled */ | |
1749 | }; | |
1750 | ||
1751 | static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data) | |
1752 | { | |
1753 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1754 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1755 | ||
1756 | dc->desc = "Aspeed 1030 FMC Controller"; | |
1757 | asc->r_conf = R_CONF; | |
1758 | asc->r_ce_ctrl = R_CE_CTRL; | |
1759 | asc->r_ctrl0 = R_CTRL0; | |
1760 | asc->r_timings = R_TIMINGS; | |
1761 | asc->nregs_timings = 2; | |
1762 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
1763 | asc->cs_num_max = 2; | |
1764 | asc->segments = aspeed_1030_fmc_segments; | |
1765 | asc->segment_addr_mask = 0x0ff80ff8; | |
1766 | asc->resets = aspeed_1030_fmc_resets; | |
1767 | asc->flash_window_base = 0x80000000; | |
1768 | asc->flash_window_size = 0x10000000; | |
1769 | asc->features = ASPEED_SMC_FEATURE_DMA; | |
1770 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1771 | asc->dma_dram_mask = 0x000BFFFC; | |
1772 | asc->nregs = ASPEED_SMC_R_MAX; | |
1773 | asc->segment_to_reg = aspeed_1030_smc_segment_to_reg; | |
1774 | asc->reg_to_segment = aspeed_1030_smc_reg_to_segment; | |
1775 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; | |
1776 | } | |
1777 | ||
1778 | static const TypeInfo aspeed_1030_fmc_info = { | |
1779 | .name = "aspeed.fmc-ast1030", | |
1780 | .parent = TYPE_ASPEED_SMC, | |
1781 | .class_init = aspeed_1030_fmc_class_init, | |
1782 | }; | |
1783 | ||
1784 | static const AspeedSegments aspeed_1030_spi1_segments[] = { | |
1785 | { 0x0, 128 * MiB }, /* start address is readonly */ | |
1786 | { 0x0, 0 }, /* disabled */ | |
1787 | }; | |
1788 | ||
1789 | static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data) | |
1790 | { | |
1791 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1792 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1793 | ||
1794 | dc->desc = "Aspeed 1030 SPI1 Controller"; | |
1795 | asc->r_conf = R_CONF; | |
1796 | asc->r_ce_ctrl = R_CE_CTRL; | |
1797 | asc->r_ctrl0 = R_CTRL0; | |
1798 | asc->r_timings = R_TIMINGS; | |
1799 | asc->nregs_timings = 2; | |
1800 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
1801 | asc->cs_num_max = 2; | |
1802 | asc->segments = aspeed_1030_spi1_segments; | |
1803 | asc->segment_addr_mask = 0x0ff00ff0; | |
1804 | asc->flash_window_base = 0x90000000; | |
1805 | asc->flash_window_size = 0x10000000; | |
1806 | asc->features = ASPEED_SMC_FEATURE_DMA; | |
1807 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1808 | asc->dma_dram_mask = 0x000BFFFC; | |
1809 | asc->nregs = ASPEED_SMC_R_MAX; | |
1810 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; | |
1811 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; | |
1812 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; | |
1813 | } | |
1814 | ||
1815 | static const TypeInfo aspeed_1030_spi1_info = { | |
1816 | .name = "aspeed.spi1-ast1030", | |
1817 | .parent = TYPE_ASPEED_SMC, | |
1818 | .class_init = aspeed_1030_spi1_class_init, | |
1819 | }; | |
1820 | static const AspeedSegments aspeed_1030_spi2_segments[] = { | |
1821 | { 0x0, 128 * MiB }, /* start address is readonly */ | |
1822 | { 0x0, 0 }, /* disabled */ | |
1823 | }; | |
1824 | ||
1825 | static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data) | |
1826 | { | |
1827 | DeviceClass *dc = DEVICE_CLASS(klass); | |
1828 | AspeedSMCClass *asc = ASPEED_SMC_CLASS(klass); | |
1829 | ||
1830 | dc->desc = "Aspeed 1030 SPI2 Controller"; | |
1831 | asc->r_conf = R_CONF; | |
1832 | asc->r_ce_ctrl = R_CE_CTRL; | |
1833 | asc->r_ctrl0 = R_CTRL0; | |
1834 | asc->r_timings = R_TIMINGS; | |
1835 | asc->nregs_timings = 2; | |
1836 | asc->conf_enable_w0 = CONF_ENABLE_W0; | |
1837 | asc->cs_num_max = 2; | |
1838 | asc->segments = aspeed_1030_spi2_segments; | |
1839 | asc->segment_addr_mask = 0x0ff00ff0; | |
1840 | asc->flash_window_base = 0xb0000000; | |
1841 | asc->flash_window_size = 0x10000000; | |
1842 | asc->features = ASPEED_SMC_FEATURE_DMA; | |
1843 | asc->dma_flash_mask = 0x0FFFFFFC; | |
1844 | asc->dma_dram_mask = 0x000BFFFC; | |
1845 | asc->nregs = ASPEED_SMC_R_MAX; | |
1846 | asc->segment_to_reg = aspeed_2600_smc_segment_to_reg; | |
1847 | asc->reg_to_segment = aspeed_2600_smc_reg_to_segment; | |
1848 | asc->dma_ctrl = aspeed_2600_smc_dma_ctrl; | |
1849 | } | |
1850 | ||
1851 | static const TypeInfo aspeed_1030_spi2_info = { | |
1852 | .name = "aspeed.spi2-ast1030", | |
1853 | .parent = TYPE_ASPEED_SMC, | |
1854 | .class_init = aspeed_1030_spi2_class_init, | |
1855 | }; | |
1856 | ||
30b6852c CLG |
1857 | static void aspeed_smc_register_types(void) |
1858 | { | |
f75b5331 | 1859 | type_register_static(&aspeed_smc_flash_info); |
30b6852c CLG |
1860 | type_register_static(&aspeed_smc_info); |
1861 | type_register_static(&aspeed_2400_smc_info); | |
1862 | type_register_static(&aspeed_2400_fmc_info); | |
1863 | type_register_static(&aspeed_2400_spi1_info); | |
1864 | type_register_static(&aspeed_2500_fmc_info); | |
1865 | type_register_static(&aspeed_2500_spi1_info); | |
1866 | type_register_static(&aspeed_2500_spi2_info); | |
1867 | type_register_static(&aspeed_2600_fmc_info); | |
1868 | type_register_static(&aspeed_2600_spi1_info); | |
1869 | type_register_static(&aspeed_2600_spi2_info); | |
2850df6a SL |
1870 | type_register_static(&aspeed_1030_fmc_info); |
1871 | type_register_static(&aspeed_1030_spi1_info); | |
1872 | type_register_static(&aspeed_1030_spi2_info); | |
30b6852c CLG |
1873 | } |
1874 | ||
7c1c69bc | 1875 | type_init(aspeed_smc_register_types) |