[mirror_qemu.git] / hw / ssi / pl022.c

/*
 * Arm PrimeCell PL022 Synchronous Serial Port
 *
 * Copyright (c) 2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "hw/ssi/ssi.h"
#include "qemu/log.h"

//#define DEBUG_PL022 1

#ifdef DEBUG_PL022
#define DPRINTF(fmt, ...) \
do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

#define PL022_CR1_LBM 0x01
#define PL022_CR1_SSE 0x02
#define PL022_CR1_MS  0x04
#define PL022_CR1_SDO 0x08

#define PL022_SR_TFE  0x01
#define PL022_SR_TNF  0x02
#define PL022_SR_RNE  0x04
#define PL022_SR_RFF  0x08
#define PL022_SR_BSY  0x10

#define PL022_INT_ROR 0x01
#define PL022_INT_RT  0x04
#define PL022_INT_RX  0x04
#define PL022_INT_TX  0x08

#define TYPE_PL022 "pl022"
#define PL022(obj) OBJECT_CHECK(PL022State, (obj), TYPE_PL022)

typedef struct PL022State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t cr0;
    uint32_t cr1;
    uint32_t bitmask;
    uint32_t sr;
    uint32_t cpsr;
    uint32_t is;
    uint32_t im;
    /* The FIFO head points to the next empty entry.  */
    int tx_fifo_head;
    int rx_fifo_head;
    int tx_fifo_len;
    int rx_fifo_len;
    uint16_t tx_fifo[8];
    uint16_t rx_fifo[8];
    qemu_irq irq;
    SSIBus *ssi;
} PL022State;

static const unsigned char pl022_id[8] =
  { 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl022_update(PL022State *s)
{
    s->sr = 0;
    if (s->tx_fifo_len == 0)
        s->sr |= PL022_SR_TFE;
    if (s->tx_fifo_len != 8)
        s->sr |= PL022_SR_TNF;
    if (s->rx_fifo_len != 0)
        s->sr |= PL022_SR_RNE;
    if (s->rx_fifo_len == 8)
        s->sr |= PL022_SR_RFF;
    if (s->tx_fifo_len)
        s->sr |= PL022_SR_BSY;
    s->is = 0;
    if (s->rx_fifo_len >= 4)
        s->is |= PL022_INT_RX;
    if (s->tx_fifo_len <= 4)
        s->is |= PL022_INT_TX;

    qemu_set_irq(s->irq, (s->is & s->im) != 0);
}

static void pl022_xfer(PL022State *s)
{
    int i;
    int o;
    int val;

    if ((s->cr1 & PL022_CR1_SSE) == 0) {
        pl022_update(s);
        DPRINTF("Disabled\n");
        return;
    }

    DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
    i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
    o = s->rx_fifo_head;
    /* ??? We do not emulate the line speed.
       This may break some applications.  The are two problematic cases:
        (a) A driver feeds data into the TX FIFO until it is full,
         and only then drains the RX FIFO.  On real hardware the CPU can
         feed data fast enough that the RX fifo never gets chance to overflow.
        (b) A driver transmits data, deliberately allowing the RX FIFO to
         overflow because it ignores the RX data anyway.

       We choose to support (a) by stalling the transmit engine if it would
       cause the RX FIFO to overflow.  In practice much transmit-only code
       falls into (a) because it flushes the RX FIFO to determine when
       the transfer has completed.  */
    while (s->tx_fifo_len && s->rx_fifo_len < 8) {
        DPRINTF("xfer\n");
        val = s->tx_fifo[i];
        if (s->cr1 & PL022_CR1_LBM) {
            /* Loopback mode.  */
        } else {
            val = ssi_transfer(s->ssi, val);
        }
        s->rx_fifo[o] = val & s->bitmask;
        i = (i + 1) & 7;
        o = (o + 1) & 7;
        s->tx_fifo_len--;
        s->rx_fifo_len++;
    }
    s->rx_fifo_head = o;
    pl022_update(s);
}

static uint64_t pl022_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL022State *s = (PL022State *)opaque;
    int val;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return pl022_id[(offset - 0xfe0) >> 2];
    }
    switch (offset) {
    case 0x00: /* CR0 */
      return s->cr0;
    case 0x04: /* CR1 */
      return s->cr1;
    case 0x08: /* DR */
        if (s->rx_fifo_len) {
            val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
            DPRINTF("RX %02x\n", val);
            s->rx_fifo_len--;
            pl022_xfer(s);
        } else {
            val = 0;
        }
        return val;
    case 0x0c: /* SR */
        return s->sr;
    case 0x10: /* CPSR */
        return s->cpsr;
    case 0x14: /* IMSC */
        return s->im;
    case 0x18: /* RIS */
        return s->is;
    case 0x1c: /* MIS */
        return s->im & s->is;
    case 0x20: /* DMACR */
        /* Not implemented.  */
        return 0;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl022_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl022_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL022State *s = (PL022State *)opaque;

    switch (offset) {
    case 0x00: /* CR0 */
        s->cr0 = value;
        /* Clock rate and format are ignored.  */
        s->bitmask = (1 << ((value & 15) + 1)) - 1;
        break;
    case 0x04: /* CR1 */
        s->cr1 = value;
        if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE))
                   == (PL022_CR1_MS | PL022_CR1_SSE)) {
            BADF("SPI slave mode not implemented\n");
        }
        pl022_xfer(s);
        break;
    case 0x08: /* DR */
        if (s->tx_fifo_len < 8) {
            DPRINTF("TX %02x\n", (unsigned)value);
            s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
            s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
            s->tx_fifo_len++;
            pl022_xfer(s);
        }
        break;
    case 0x10: /* CPSR */
        /* Prescaler.  Ignored.  */
        s->cpsr = value & 0xff;
        break;
    case 0x14: /* IMSC */
        s->im = value;
        pl022_update(s);
        break;
    case 0x20: /* DMACR */
        if (value) {
            qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
        }
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl022_write: Bad offset %x\n", (int)offset);
    }
}

static void pl022_reset(PL022State *s)
{
    s->rx_fifo_len = 0;
    s->tx_fifo_len = 0;
    s->im = 0;
    s->is = PL022_INT_TX;
    s->sr = PL022_SR_TFE | PL022_SR_TNF;
}

static const MemoryRegionOps pl022_ops = {
    .read = pl022_read,
    .write = pl022_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pl022_post_load(void *opaque, int version_id)
{
    PL022State *s = opaque;

    if (s->tx_fifo_head < 0 ||
        s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) ||
        s->rx_fifo_head < 0 ||
        s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) {
        return -1;
    }
    return 0;
}

static const VMStateDescription vmstate_pl022 = {
    .name = "pl022_ssp",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = pl022_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cr0, PL022State),
        VMSTATE_UINT32(cr1, PL022State),
        VMSTATE_UINT32(bitmask, PL022State),
        VMSTATE_UINT32(sr, PL022State),
        VMSTATE_UINT32(cpsr, PL022State),
        VMSTATE_UINT32(is, PL022State),
        VMSTATE_UINT32(im, PL022State),
        VMSTATE_INT32(tx_fifo_head, PL022State),
        VMSTATE_INT32(rx_fifo_head, PL022State),
        VMSTATE_INT32(tx_fifo_len, PL022State),
        VMSTATE_INT32(rx_fifo_len, PL022State),
        VMSTATE_UINT16(tx_fifo[0], PL022State),
        VMSTATE_UINT16(rx_fifo[0], PL022State),
        VMSTATE_UINT16(tx_fifo[1], PL022State),
        VMSTATE_UINT16(rx_fifo[1], PL022State),
        VMSTATE_UINT16(tx_fifo[2], PL022State),
        VMSTATE_UINT16(rx_fifo[2], PL022State),
        VMSTATE_UINT16(tx_fifo[3], PL022State),
        VMSTATE_UINT16(rx_fifo[3], PL022State),
        VMSTATE_UINT16(tx_fifo[4], PL022State),
        VMSTATE_UINT16(rx_fifo[4], PL022State),
        VMSTATE_UINT16(tx_fifo[5], PL022State),
        VMSTATE_UINT16(rx_fifo[5], PL022State),
        VMSTATE_UINT16(tx_fifo[6], PL022State),
        VMSTATE_UINT16(rx_fifo[6], PL022State),
        VMSTATE_UINT16(tx_fifo[7], PL022State),
        VMSTATE_UINT16(rx_fifo[7], PL022State),
        VMSTATE_END_OF_LIST()
    }
};

static int pl022_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    PL022State *s = PL022(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    s->ssi = ssi_create_bus(dev, "ssi");
    pl022_reset(s);
    vmstate_register(dev, -1, &vmstate_pl022, s);
    return 0;
}

static void pl022_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

    sdc->init = pl022_init;
}

static const TypeInfo pl022_info = {
    .name          = TYPE_PL022,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL022State),
    .class_init    = pl022_class_init,
};

static void pl022_register_types(void)
{
    type_register_static(&pl022_info);
}

type_init(pl022_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* Arm PrimeCell PL022 Synchronous Serial Port
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
9ee6e8bb PB	8	*/
9ee6e8bb PB	9
17b7f2db	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/sysbus.h"
8fd06719	12	#include "hw/ssi/ssi.h"
03dd024f	13	#include "qemu/log.h"
9ee6e8bb PB	14
	15	//#define DEBUG_PL022 1
	16
	17	#ifdef DEBUG_PL022
001faf32 BS	18	#define DPRINTF(fmt, ...) \
	19	do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
	20	#define BADF(fmt, ...) \
	21	do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
9ee6e8bb	22	#else
001faf32 BS	23	#define DPRINTF(fmt, ...) do {} while(0)
	24	#define BADF(fmt, ...) \
	25	do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
9ee6e8bb PB	26	#endif
	27
	28	#define PL022_CR1_LBM 0x01
	29	#define PL022_CR1_SSE 0x02
	30	#define PL022_CR1_MS 0x04
	31	#define PL022_CR1_SDO 0x08
	32
	33	#define PL022_SR_TFE 0x01
	34	#define PL022_SR_TNF 0x02
	35	#define PL022_SR_RNE 0x04
	36	#define PL022_SR_RFF 0x08
	37	#define PL022_SR_BSY 0x10
	38
	39	#define PL022_INT_ROR 0x01
	40	#define PL022_INT_RT 0x04
	41	#define PL022_INT_RX 0x04
	42	#define PL022_INT_TX 0x08
	43
3d29bcee AF	44	#define TYPE_PL022 "pl022"
	45	#define PL022(obj) OBJECT_CHECK(PL022State, (obj), TYPE_PL022)
	46
ce556e0b	47	typedef struct PL022State {
3d29bcee AF	48	SysBusDevice parent_obj;
3d29bcee AF	49
02a59c37	50	MemoryRegion iomem;
9ee6e8bb PB	51	uint32_t cr0;
	52	uint32_t cr1;
	53	uint32_t bitmask;
	54	uint32_t sr;
	55	uint32_t cpsr;
	56	uint32_t is;
	57	uint32_t im;
	58	/* The FIFO head points to the next empty entry. */
	59	int tx_fifo_head;
	60	int rx_fifo_head;
	61	int tx_fifo_len;
	62	int rx_fifo_len;
	63	uint16_t tx_fifo[8];
	64	uint16_t rx_fifo[8];
	65	qemu_irq irq;
5493e33f	66	SSIBus *ssi;
ce556e0b	67	} PL022State;
9ee6e8bb PB	68
	69	static const unsigned char pl022_id[8] =
	70	{ 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	71
ce556e0b	72	static void pl022_update(PL022State *s)
9ee6e8bb PB	73	{
	74	s->sr = 0;
	75	if (s->tx_fifo_len == 0)
	76	s->sr \|= PL022_SR_TFE;
	77	if (s->tx_fifo_len != 8)
	78	s->sr \|= PL022_SR_TNF;
	79	if (s->rx_fifo_len != 0)
	80	s->sr \|= PL022_SR_RNE;
	81	if (s->rx_fifo_len == 8)
	82	s->sr \|= PL022_SR_RFF;
	83	if (s->tx_fifo_len)
	84	s->sr \|= PL022_SR_BSY;
	85	s->is = 0;
	86	if (s->rx_fifo_len >= 4)
	87	s->is \|= PL022_INT_RX;
	88	if (s->tx_fifo_len <= 4)
	89	s->is \|= PL022_INT_TX;
	90
	91	qemu_set_irq(s->irq, (s->is & s->im) != 0);
	92	}
	93
ce556e0b	94	static void pl022_xfer(PL022State *s)
9ee6e8bb PB	95	{
	96	int i;
	97	int o;
	98	int val;
	99
	100	if ((s->cr1 & PL022_CR1_SSE) == 0) {
	101	pl022_update(s);
	102	DPRINTF("Disabled\n");
	103	return;
	104	}
	105
	106	DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
	107	i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
	108	o = s->rx_fifo_head;
	109	/* ??? We do not emulate the line speed.
	110	This may break some applications. The are two problematic cases:
	111	(a) A driver feeds data into the TX FIFO until it is full,
	112	and only then drains the RX FIFO. On real hardware the CPU can
	113	feed data fast enough that the RX fifo never gets chance to overflow.
	114	(b) A driver transmits data, deliberately allowing the RX FIFO to
	115	overflow because it ignores the RX data anyway.
	116
	117	We choose to support (a) by stalling the transmit engine if it would
	118	cause the RX FIFO to overflow. In practice much transmit-only code
	119	falls into (a) because it flushes the RX FIFO to determine when
	120	the transfer has completed. */
	121	while (s->tx_fifo_len && s->rx_fifo_len < 8) {
	122	DPRINTF("xfer\n");
	123	val = s->tx_fifo[i];
	124	if (s->cr1 & PL022_CR1_LBM) {
	125	/* Loopback mode. */
9ee6e8bb	126	} else {
5493e33f	127	val = ssi_transfer(s->ssi, val);
9ee6e8bb PB	128	}
	129	s->rx_fifo[o] = val & s->bitmask;
	130	i = (i + 1) & 7;
	131	o = (o + 1) & 7;
	132	s->tx_fifo_len--;
	133	s->rx_fifo_len++;
	134	}
	135	s->rx_fifo_head = o;
	136	pl022_update(s);
	137	}
	138
a8170e5e	139	static uint64_t pl022_read(void *opaque, hwaddr offset,
02a59c37	140	unsigned size)
9ee6e8bb	141	{
ce556e0b	142	PL022State s = (PL022State )opaque;
9ee6e8bb PB	143	int val;
9ee6e8bb PB	144
9ee6e8bb PB	145	if (offset >= 0xfe0 && offset < 0x1000) {
	146	return pl022_id[(offset - 0xfe0) >> 2];
	147	}
	148	switch (offset) {
	149	case 0x00: /* CR0 */
	150	return s->cr0;
	151	case 0x04: /* CR1 */
	152	return s->cr1;
	153	case 0x08: /* DR */
	154	if (s->rx_fifo_len) {
	155	val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
	156	DPRINTF("RX %02x\n", val);
	157	s->rx_fifo_len--;
	158	pl022_xfer(s);
	159	} else {
	160	val = 0;
	161	}
	162	return val;
	163	case 0x0c: /* SR */
	164	return s->sr;
	165	case 0x10: /* CPSR */
	166	return s->cpsr;
	167	case 0x14: /* IMSC */
	168	return s->im;
	169	case 0x18: /* RIS */
	170	return s->is;
	171	case 0x1c: /* MIS */
	172	return s->im & s->is;
	173	case 0x20: /* DMACR */
	174	/* Not implemented. */
	175	return 0;
	176	default:
af83c32b PM	177	qemu_log_mask(LOG_GUEST_ERROR,
af83c32b PM	178	"pl022_read: Bad offset %x\n", (int)offset);
9ee6e8bb PB	179	return 0;
	180	}
	181	}
	182
a8170e5e	183	static void pl022_write(void *opaque, hwaddr offset,
02a59c37	184	uint64_t value, unsigned size)
9ee6e8bb	185	{
ce556e0b	186	PL022State s = (PL022State )opaque;
9ee6e8bb	187
9ee6e8bb PB	188	switch (offset) {
	189	case 0x00: /* CR0 */
	190	s->cr0 = value;
	191	/* Clock rate and format are ignored. */
	192	s->bitmask = (1 << ((value & 15) + 1)) - 1;
	193	break;
	194	case 0x04: /* CR1 */
	195	s->cr1 = value;
	196	if ((s->cr1 & (PL022_CR1_MS \| PL022_CR1_SSE))
	197	== (PL022_CR1_MS \| PL022_CR1_SSE)) {
	198	BADF("SPI slave mode not implemented\n");
	199	}
	200	pl022_xfer(s);
	201	break;
	202	case 0x08: /* DR */
	203	if (s->tx_fifo_len < 8) {
02a59c37	204	DPRINTF("TX %02x\n", (unsigned)value);
9ee6e8bb PB	205	s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
	206	s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
	207	s->tx_fifo_len++;
	208	pl022_xfer(s);
	209	}
	210	break;
	211	case 0x10: /* CPSR */
	212	/* Prescaler. Ignored. */
	213	s->cpsr = value & 0xff;
	214	break;
	215	case 0x14: /* IMSC */
	216	s->im = value;
	217	pl022_update(s);
	218	break;
	219	case 0x20: /* DMACR */
2ac71179	220	if (value) {
af83c32b	221	qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
2ac71179	222	}
9ee6e8bb PB	223	break;
9ee6e8bb PB	224	default:
af83c32b PM	225	qemu_log_mask(LOG_GUEST_ERROR,
af83c32b PM	226	"pl022_write: Bad offset %x\n", (int)offset);
9ee6e8bb PB	227	}
	228	}
	229
ce556e0b	230	static void pl022_reset(PL022State *s)
9ee6e8bb PB	231	{
	232	s->rx_fifo_len = 0;
	233	s->tx_fifo_len = 0;
	234	s->im = 0;
	235	s->is = PL022_INT_TX;
	236	s->sr = PL022_SR_TFE \| PL022_SR_TNF;
	237	}
	238
02a59c37 AK	239	static const MemoryRegionOps pl022_ops = {
	240	.read = pl022_read,
	241	.write = pl022_write,
	242	.endianness = DEVICE_NATIVE_ENDIAN,
9ee6e8bb PB	243	};
9ee6e8bb PB	244
d8d0a0bc MT	245	static int pl022_post_load(void *opaque, int version_id)
	246	{
	247	PL022State *s = opaque;
	248
	249	if (s->tx_fifo_head < 0 \|\|
	250	s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) \|\|
	251	s->rx_fifo_head < 0 \|\|
	252	s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) {
	253	return -1;
	254	}
	255	return 0;
	256	}
	257
075790c2 JQ	258	static const VMStateDescription vmstate_pl022 = {
	259	.name = "pl022_ssp",
	260	.version_id = 1,
	261	.minimum_version_id = 1,
d8d0a0bc	262	.post_load = pl022_post_load,
8f1e884b	263	.fields = (VMStateField[]) {
ce556e0b AF	264	VMSTATE_UINT32(cr0, PL022State),
	265	VMSTATE_UINT32(cr1, PL022State),
	266	VMSTATE_UINT32(bitmask, PL022State),
	267	VMSTATE_UINT32(sr, PL022State),
	268	VMSTATE_UINT32(cpsr, PL022State),
	269	VMSTATE_UINT32(is, PL022State),
	270	VMSTATE_UINT32(im, PL022State),
	271	VMSTATE_INT32(tx_fifo_head, PL022State),
	272	VMSTATE_INT32(rx_fifo_head, PL022State),
	273	VMSTATE_INT32(tx_fifo_len, PL022State),
	274	VMSTATE_INT32(rx_fifo_len, PL022State),
	275	VMSTATE_UINT16(tx_fifo[0], PL022State),
	276	VMSTATE_UINT16(rx_fifo[0], PL022State),
	277	VMSTATE_UINT16(tx_fifo[1], PL022State),
	278	VMSTATE_UINT16(rx_fifo[1], PL022State),
	279	VMSTATE_UINT16(tx_fifo[2], PL022State),
	280	VMSTATE_UINT16(rx_fifo[2], PL022State),
	281	VMSTATE_UINT16(tx_fifo[3], PL022State),
	282	VMSTATE_UINT16(rx_fifo[3], PL022State),
	283	VMSTATE_UINT16(tx_fifo[4], PL022State),
	284	VMSTATE_UINT16(rx_fifo[4], PL022State),
	285	VMSTATE_UINT16(tx_fifo[5], PL022State),
	286	VMSTATE_UINT16(rx_fifo[5], PL022State),
	287	VMSTATE_UINT16(tx_fifo[6], PL022State),
	288	VMSTATE_UINT16(rx_fifo[6], PL022State),
	289	VMSTATE_UINT16(tx_fifo[7], PL022State),
	290	VMSTATE_UINT16(rx_fifo[7], PL022State),
075790c2	291	VMSTATE_END_OF_LIST()
23e39294	292	}
075790c2	293	};
23e39294	294
3d29bcee	295	static int pl022_init(SysBusDevice *sbd)
9ee6e8bb	296	{
3d29bcee AF	297	DeviceState *dev = DEVICE(sbd);
3d29bcee AF	298	PL022State *s = PL022(dev);
9ee6e8bb	299
29776739	300	memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
3d29bcee AF	301	sysbus_init_mmio(sbd, &s->iomem);
	302	sysbus_init_irq(sbd, &s->irq);
	303	s->ssi = ssi_create_bus(dev, "ssi");
9ee6e8bb	304	pl022_reset(s);
3d29bcee	305	vmstate_register(dev, -1, &vmstate_pl022, s);
81a322d4	306	return 0;
9ee6e8bb	307	}
5493e33f	308
999e12bb AL	309	static void pl022_class_init(ObjectClass klass, void data)
	310	{
	311	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	312
	313	sdc->init = pl022_init;
	314	}
	315
8c43a6f0	316	static const TypeInfo pl022_info = {
3d29bcee	317	.name = TYPE_PL022,
39bffca2	318	.parent = TYPE_SYS_BUS_DEVICE,
ce556e0b	319	.instance_size = sizeof(PL022State),
39bffca2	320	.class_init = pl022_class_init,
999e12bb AL	321	};
999e12bb AL	322
83f7d43a	323	static void pl022_register_types(void)
5493e33f	324	{
39bffca2	325	type_register_static(&pl022_info);
5493e33f PB	326	}
5493e33f PB	327
83f7d43a	328	type_init(pl022_register_types)