[mirror_qemu.git] / hw / ssi / pl022.c

/*
 * Arm PrimeCell PL022 Synchronous Serial Port
 *
 * Copyright (c) 2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "hw/irq.h"
#include "hw/ssi/pl022.h"
#include "hw/ssi/ssi.h"
#include "qemu/log.h"
#include "qemu/module.h"

//#define DEBUG_PL022 1

#ifdef DEBUG_PL022
#define DPRINTF(fmt, ...) \
do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

#define PL022_CR1_LBM 0x01
#define PL022_CR1_SSE 0x02
#define PL022_CR1_MS  0x04
#define PL022_CR1_SDO 0x08

#define PL022_SR_TFE  0x01
#define PL022_SR_TNF  0x02
#define PL022_SR_RNE  0x04
#define PL022_SR_RFF  0x08
#define PL022_SR_BSY  0x10

#define PL022_INT_ROR 0x01
#define PL022_INT_RT  0x02
#define PL022_INT_RX  0x04
#define PL022_INT_TX  0x08

static const unsigned char pl022_id[8] =
  { 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl022_update(PL022State *s)
{
    s->sr = 0;
    if (s->tx_fifo_len == 0)
        s->sr |= PL022_SR_TFE;
    if (s->tx_fifo_len != 8)
        s->sr |= PL022_SR_TNF;
    if (s->rx_fifo_len != 0)
        s->sr |= PL022_SR_RNE;
    if (s->rx_fifo_len == 8)
        s->sr |= PL022_SR_RFF;
    if (s->tx_fifo_len)
        s->sr |= PL022_SR_BSY;
    s->is = 0;
    if (s->rx_fifo_len >= 4)
        s->is |= PL022_INT_RX;
    if (s->tx_fifo_len <= 4)
        s->is |= PL022_INT_TX;

    qemu_set_irq(s->irq, (s->is & s->im) != 0);
}

static void pl022_xfer(PL022State *s)
{
    int i;
    int o;
    int val;

    if ((s->cr1 & PL022_CR1_SSE) == 0) {
        pl022_update(s);
        DPRINTF("Disabled\n");
        return;
    }

    DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
    i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
    o = s->rx_fifo_head;
    /* ??? We do not emulate the line speed.
       This may break some applications.  The are two problematic cases:
        (a) A driver feeds data into the TX FIFO until it is full,
         and only then drains the RX FIFO.  On real hardware the CPU can
         feed data fast enough that the RX fifo never gets chance to overflow.
        (b) A driver transmits data, deliberately allowing the RX FIFO to
         overflow because it ignores the RX data anyway.

       We choose to support (a) by stalling the transmit engine if it would
       cause the RX FIFO to overflow.  In practice much transmit-only code
       falls into (a) because it flushes the RX FIFO to determine when
       the transfer has completed.  */
    while (s->tx_fifo_len && s->rx_fifo_len < 8) {
        DPRINTF("xfer\n");
        val = s->tx_fifo[i];
        if (s->cr1 & PL022_CR1_LBM) {
            /* Loopback mode.  */
        } else {
            val = ssi_transfer(s->ssi, val);
        }
        s->rx_fifo[o] = val & s->bitmask;
        i = (i + 1) & 7;
        o = (o + 1) & 7;
        s->tx_fifo_len--;
        s->rx_fifo_len++;
    }
    s->rx_fifo_head = o;
    pl022_update(s);
}

static uint64_t pl022_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL022State *s = (PL022State *)opaque;
    int val;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return pl022_id[(offset - 0xfe0) >> 2];
    }
    switch (offset) {
    case 0x00: /* CR0 */
      return s->cr0;
    case 0x04: /* CR1 */
      return s->cr1;
    case 0x08: /* DR */
        if (s->rx_fifo_len) {
            val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
            DPRINTF("RX %02x\n", val);
            s->rx_fifo_len--;
            pl022_xfer(s);
        } else {
            val = 0;
        }
        return val;
    case 0x0c: /* SR */
        return s->sr;
    case 0x10: /* CPSR */
        return s->cpsr;
    case 0x14: /* IMSC */
        return s->im;
    case 0x18: /* RIS */
        return s->is;
    case 0x1c: /* MIS */
        return s->im & s->is;
    case 0x24: /* DMACR */
        /* Not implemented.  */
        return 0;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl022_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl022_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL022State *s = (PL022State *)opaque;

    switch (offset) {
    case 0x00: /* CR0 */
        s->cr0 = value;
        /* Clock rate and format are ignored.  */
        s->bitmask = (1 << ((value & 15) + 1)) - 1;
        break;
    case 0x04: /* CR1 */
        s->cr1 = value;
        if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE))
                   == (PL022_CR1_MS | PL022_CR1_SSE)) {
            BADF("SPI slave mode not implemented\n");
        }
        pl022_xfer(s);
        break;
    case 0x08: /* DR */
        if (s->tx_fifo_len < 8) {
            DPRINTF("TX %02x\n", (unsigned)value);
            s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
            s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
            s->tx_fifo_len++;
            pl022_xfer(s);
        }
        break;
    case 0x10: /* CPSR */
        /* Prescaler.  Ignored.  */
        s->cpsr = value & 0xff;
        break;
    case 0x14: /* IMSC */
        s->im = value;
        pl022_update(s);
        break;
    case 0x20: /* ICR */
        /*
         * write-1-to-clear: bit 0 clears ROR, bit 1 clears RT;
         * RX and TX interrupts cannot be cleared this way.
         */
        value &= PL022_INT_ROR | PL022_INT_RT;
        s->is &= ~value;
        break;
    case 0x24: /* DMACR */
        if (value) {
            qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
        }
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl022_write: Bad offset %x\n", (int)offset);
    }
}

static void pl022_reset(DeviceState *dev)
{
    PL022State *s = PL022(dev);

    s->rx_fifo_len = 0;
    s->tx_fifo_len = 0;
    s->im = 0;
    s->is = PL022_INT_TX;
    s->sr = PL022_SR_TFE | PL022_SR_TNF;
}

static const MemoryRegionOps pl022_ops = {
    .read = pl022_read,
    .write = pl022_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pl022_post_load(void *opaque, int version_id)
{
    PL022State *s = opaque;

    if (s->tx_fifo_head < 0 ||
        s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) ||
        s->rx_fifo_head < 0 ||
        s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) {
        return -1;
    }
    return 0;
}

static const VMStateDescription vmstate_pl022 = {
    .name = "pl022_ssp",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = pl022_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cr0, PL022State),
        VMSTATE_UINT32(cr1, PL022State),
        VMSTATE_UINT32(bitmask, PL022State),
        VMSTATE_UINT32(sr, PL022State),
        VMSTATE_UINT32(cpsr, PL022State),
        VMSTATE_UINT32(is, PL022State),
        VMSTATE_UINT32(im, PL022State),
        VMSTATE_INT32(tx_fifo_head, PL022State),
        VMSTATE_INT32(rx_fifo_head, PL022State),
        VMSTATE_INT32(tx_fifo_len, PL022State),
        VMSTATE_INT32(rx_fifo_len, PL022State),
        VMSTATE_UINT16(tx_fifo[0], PL022State),
        VMSTATE_UINT16(rx_fifo[0], PL022State),
        VMSTATE_UINT16(tx_fifo[1], PL022State),
        VMSTATE_UINT16(rx_fifo[1], PL022State),
        VMSTATE_UINT16(tx_fifo[2], PL022State),
        VMSTATE_UINT16(rx_fifo[2], PL022State),
        VMSTATE_UINT16(tx_fifo[3], PL022State),
        VMSTATE_UINT16(rx_fifo[3], PL022State),
        VMSTATE_UINT16(tx_fifo[4], PL022State),
        VMSTATE_UINT16(rx_fifo[4], PL022State),
        VMSTATE_UINT16(tx_fifo[5], PL022State),
        VMSTATE_UINT16(rx_fifo[5], PL022State),
        VMSTATE_UINT16(tx_fifo[6], PL022State),
        VMSTATE_UINT16(rx_fifo[6], PL022State),
        VMSTATE_UINT16(tx_fifo[7], PL022State),
        VMSTATE_UINT16(rx_fifo[7], PL022State),
        VMSTATE_END_OF_LIST()
    }
};

static void pl022_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    PL022State *s = PL022(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    s->ssi = ssi_create_bus(dev, "ssi");
}

static void pl022_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = pl022_reset;
    dc->vmsd = &vmstate_pl022;
    dc->realize = pl022_realize;
}

static const TypeInfo pl022_info = {
    .name          = TYPE_PL022,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL022State),
    .class_init    = pl022_class_init,
};

static void pl022_register_types(void)
{
    type_register_static(&pl022_info);
}

type_init(pl022_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* Arm PrimeCell PL022 Synchronous Serial Port
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
9ee6e8bb PB	8	*/
9ee6e8bb PB	9
17b7f2db	10	#include "qemu/osdep.h"
83c9f4ca	11	#include "hw/sysbus.h"
d6454270	12	#include "migration/vmstate.h"
64552b6b	13	#include "hw/irq.h"
1d52866f	14	#include "hw/ssi/pl022.h"
8fd06719	15	#include "hw/ssi/ssi.h"
03dd024f	16	#include "qemu/log.h"
0b8fa32f	17	#include "qemu/module.h"
9ee6e8bb PB	18
	19	//#define DEBUG_PL022 1
	20
	21	#ifdef DEBUG_PL022
001faf32 BS	22	#define DPRINTF(fmt, ...) \
	23	do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
	24	#define BADF(fmt, ...) \
	25	do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
9ee6e8bb	26	#else
001faf32 BS	27	#define DPRINTF(fmt, ...) do {} while(0)
	28	#define BADF(fmt, ...) \
	29	do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
9ee6e8bb PB	30	#endif
	31
	32	#define PL022_CR1_LBM 0x01
	33	#define PL022_CR1_SSE 0x02
	34	#define PL022_CR1_MS 0x04
	35	#define PL022_CR1_SDO 0x08
	36
	37	#define PL022_SR_TFE 0x01
	38	#define PL022_SR_TNF 0x02
	39	#define PL022_SR_RNE 0x04
	40	#define PL022_SR_RFF 0x08
	41	#define PL022_SR_BSY 0x10
	42
	43	#define PL022_INT_ROR 0x01
139d941e	44	#define PL022_INT_RT 0x02
9ee6e8bb PB	45	#define PL022_INT_RX 0x04
	46	#define PL022_INT_TX 0x08
	47
9ee6e8bb PB	48	static const unsigned char pl022_id[8] =
	49	{ 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	50
ce556e0b	51	static void pl022_update(PL022State *s)
9ee6e8bb PB	52	{
	53	s->sr = 0;
	54	if (s->tx_fifo_len == 0)
	55	s->sr \|= PL022_SR_TFE;
	56	if (s->tx_fifo_len != 8)
	57	s->sr \|= PL022_SR_TNF;
	58	if (s->rx_fifo_len != 0)
	59	s->sr \|= PL022_SR_RNE;
	60	if (s->rx_fifo_len == 8)
	61	s->sr \|= PL022_SR_RFF;
	62	if (s->tx_fifo_len)
	63	s->sr \|= PL022_SR_BSY;
	64	s->is = 0;
	65	if (s->rx_fifo_len >= 4)
	66	s->is \|= PL022_INT_RX;
	67	if (s->tx_fifo_len <= 4)
	68	s->is \|= PL022_INT_TX;
	69
	70	qemu_set_irq(s->irq, (s->is & s->im) != 0);
	71	}
	72
ce556e0b	73	static void pl022_xfer(PL022State *s)
9ee6e8bb PB	74	{
	75	int i;
	76	int o;
	77	int val;
	78
	79	if ((s->cr1 & PL022_CR1_SSE) == 0) {
	80	pl022_update(s);
	81	DPRINTF("Disabled\n");
	82	return;
	83	}
	84
	85	DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
	86	i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
	87	o = s->rx_fifo_head;
	88	/* ??? We do not emulate the line speed.
	89	This may break some applications. The are two problematic cases:
	90	(a) A driver feeds data into the TX FIFO until it is full,
	91	and only then drains the RX FIFO. On real hardware the CPU can
	92	feed data fast enough that the RX fifo never gets chance to overflow.
	93	(b) A driver transmits data, deliberately allowing the RX FIFO to
	94	overflow because it ignores the RX data anyway.
	95
	96	We choose to support (a) by stalling the transmit engine if it would
	97	cause the RX FIFO to overflow. In practice much transmit-only code
	98	falls into (a) because it flushes the RX FIFO to determine when
	99	the transfer has completed. */
	100	while (s->tx_fifo_len && s->rx_fifo_len < 8) {
	101	DPRINTF("xfer\n");
	102	val = s->tx_fifo[i];
	103	if (s->cr1 & PL022_CR1_LBM) {
	104	/* Loopback mode. */
9ee6e8bb	105	} else {
5493e33f	106	val = ssi_transfer(s->ssi, val);
9ee6e8bb PB	107	}
	108	s->rx_fifo[o] = val & s->bitmask;
	109	i = (i + 1) & 7;
	110	o = (o + 1) & 7;
	111	s->tx_fifo_len--;
	112	s->rx_fifo_len++;
	113	}
	114	s->rx_fifo_head = o;
	115	pl022_update(s);
	116	}
	117
a8170e5e	118	static uint64_t pl022_read(void *opaque, hwaddr offset,
02a59c37	119	unsigned size)
9ee6e8bb	120	{
ce556e0b	121	PL022State s = (PL022State )opaque;
9ee6e8bb PB	122	int val;
9ee6e8bb PB	123
9ee6e8bb PB	124	if (offset >= 0xfe0 && offset < 0x1000) {
	125	return pl022_id[(offset - 0xfe0) >> 2];
	126	}
	127	switch (offset) {
	128	case 0x00: /* CR0 */
	129	return s->cr0;
	130	case 0x04: /* CR1 */
	131	return s->cr1;
	132	case 0x08: /* DR */
	133	if (s->rx_fifo_len) {
	134	val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
	135	DPRINTF("RX %02x\n", val);
	136	s->rx_fifo_len--;
	137	pl022_xfer(s);
	138	} else {
	139	val = 0;
	140	}
	141	return val;
	142	case 0x0c: /* SR */
	143	return s->sr;
	144	case 0x10: /* CPSR */
	145	return s->cpsr;
	146	case 0x14: /* IMSC */
	147	return s->im;
	148	case 0x18: /* RIS */
	149	return s->is;
	150	case 0x1c: /* MIS */
	151	return s->im & s->is;
7d3912f5	152	case 0x24: /* DMACR */
9ee6e8bb PB	153	/* Not implemented. */
	154	return 0;
	155	default:
af83c32b PM	156	qemu_log_mask(LOG_GUEST_ERROR,
af83c32b PM	157	"pl022_read: Bad offset %x\n", (int)offset);
9ee6e8bb PB	158	return 0;
	159	}
	160	}
	161
a8170e5e	162	static void pl022_write(void *opaque, hwaddr offset,
02a59c37	163	uint64_t value, unsigned size)
9ee6e8bb	164	{
ce556e0b	165	PL022State s = (PL022State )opaque;
9ee6e8bb	166
9ee6e8bb PB	167	switch (offset) {
	168	case 0x00: /* CR0 */
	169	s->cr0 = value;
	170	/* Clock rate and format are ignored. */
	171	s->bitmask = (1 << ((value & 15) + 1)) - 1;
	172	break;
	173	case 0x04: /* CR1 */
	174	s->cr1 = value;
	175	if ((s->cr1 & (PL022_CR1_MS \| PL022_CR1_SSE))
	176	== (PL022_CR1_MS \| PL022_CR1_SSE)) {
	177	BADF("SPI slave mode not implemented\n");
	178	}
	179	pl022_xfer(s);
	180	break;
	181	case 0x08: /* DR */
	182	if (s->tx_fifo_len < 8) {
02a59c37	183	DPRINTF("TX %02x\n", (unsigned)value);
9ee6e8bb PB	184	s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
	185	s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
	186	s->tx_fifo_len++;
	187	pl022_xfer(s);
	188	}
	189	break;
	190	case 0x10: /* CPSR */
	191	/* Prescaler. Ignored. */
	192	s->cpsr = value & 0xff;
	193	break;
	194	case 0x14: /* IMSC */
	195	s->im = value;
	196	pl022_update(s);
	197	break;
7d3912f5 PM	198	case 0x20: /* ICR */
	199	/*
	200	* write-1-to-clear: bit 0 clears ROR, bit 1 clears RT;
	201	* RX and TX interrupts cannot be cleared this way.
	202	*/
	203	value &= PL022_INT_ROR \| PL022_INT_RT;
	204	s->is &= ~value;
	205	break;
	206	case 0x24: /* DMACR */
2ac71179	207	if (value) {
af83c32b	208	qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
2ac71179	209	}
9ee6e8bb PB	210	break;
9ee6e8bb PB	211	default:
af83c32b PM	212	qemu_log_mask(LOG_GUEST_ERROR,
af83c32b PM	213	"pl022_write: Bad offset %x\n", (int)offset);
9ee6e8bb PB	214	}
	215	}
	216
66d9aa79	217	static void pl022_reset(DeviceState *dev)
9ee6e8bb	218	{
66d9aa79 PM	219	PL022State *s = PL022(dev);
66d9aa79 PM	220
9ee6e8bb PB	221	s->rx_fifo_len = 0;
	222	s->tx_fifo_len = 0;
	223	s->im = 0;
	224	s->is = PL022_INT_TX;
	225	s->sr = PL022_SR_TFE \| PL022_SR_TNF;
	226	}
	227
02a59c37 AK	228	static const MemoryRegionOps pl022_ops = {
	229	.read = pl022_read,
	230	.write = pl022_write,
	231	.endianness = DEVICE_NATIVE_ENDIAN,
9ee6e8bb PB	232	};
9ee6e8bb PB	233
d8d0a0bc MT	234	static int pl022_post_load(void *opaque, int version_id)
	235	{
	236	PL022State *s = opaque;
	237
	238	if (s->tx_fifo_head < 0 \|\|
	239	s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) \|\|
	240	s->rx_fifo_head < 0 \|\|
	241	s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) {
	242	return -1;
	243	}
	244	return 0;
	245	}
	246
075790c2 JQ	247	static const VMStateDescription vmstate_pl022 = {
	248	.name = "pl022_ssp",
	249	.version_id = 1,
	250	.minimum_version_id = 1,
d8d0a0bc	251	.post_load = pl022_post_load,
8f1e884b	252	.fields = (VMStateField[]) {
ce556e0b AF	253	VMSTATE_UINT32(cr0, PL022State),
	254	VMSTATE_UINT32(cr1, PL022State),
	255	VMSTATE_UINT32(bitmask, PL022State),
	256	VMSTATE_UINT32(sr, PL022State),
	257	VMSTATE_UINT32(cpsr, PL022State),
	258	VMSTATE_UINT32(is, PL022State),
	259	VMSTATE_UINT32(im, PL022State),
	260	VMSTATE_INT32(tx_fifo_head, PL022State),
	261	VMSTATE_INT32(rx_fifo_head, PL022State),
	262	VMSTATE_INT32(tx_fifo_len, PL022State),
	263	VMSTATE_INT32(rx_fifo_len, PL022State),
	264	VMSTATE_UINT16(tx_fifo[0], PL022State),
	265	VMSTATE_UINT16(rx_fifo[0], PL022State),
	266	VMSTATE_UINT16(tx_fifo[1], PL022State),
	267	VMSTATE_UINT16(rx_fifo[1], PL022State),
	268	VMSTATE_UINT16(tx_fifo[2], PL022State),
	269	VMSTATE_UINT16(rx_fifo[2], PL022State),
	270	VMSTATE_UINT16(tx_fifo[3], PL022State),
	271	VMSTATE_UINT16(rx_fifo[3], PL022State),
	272	VMSTATE_UINT16(tx_fifo[4], PL022State),
	273	VMSTATE_UINT16(rx_fifo[4], PL022State),
	274	VMSTATE_UINT16(tx_fifo[5], PL022State),
	275	VMSTATE_UINT16(rx_fifo[5], PL022State),
	276	VMSTATE_UINT16(tx_fifo[6], PL022State),
	277	VMSTATE_UINT16(rx_fifo[6], PL022State),
	278	VMSTATE_UINT16(tx_fifo[7], PL022State),
	279	VMSTATE_UINT16(rx_fifo[7], PL022State),
075790c2	280	VMSTATE_END_OF_LIST()
23e39294	281	}
075790c2	282	};
23e39294	283
13391a56	284	static void pl022_realize(DeviceState dev, Error *errp)
9ee6e8bb	285	{
13391a56	286	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
3d29bcee	287	PL022State *s = PL022(dev);
9ee6e8bb	288
29776739	289	memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
3d29bcee AF	290	sysbus_init_mmio(sbd, &s->iomem);
	291	sysbus_init_irq(sbd, &s->irq);
	292	s->ssi = ssi_create_bus(dev, "ssi");
9ee6e8bb	293	}
5493e33f	294
999e12bb AL	295	static void pl022_class_init(ObjectClass klass, void data)
999e12bb AL	296	{
66d9aa79	297	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	298
66d9aa79	299	dc->reset = pl022_reset;
275ff67f	300	dc->vmsd = &vmstate_pl022;
13391a56	301	dc->realize = pl022_realize;
999e12bb AL	302	}
999e12bb AL	303
8c43a6f0	304	static const TypeInfo pl022_info = {
3d29bcee	305	.name = TYPE_PL022,
39bffca2	306	.parent = TYPE_SYS_BUS_DEVICE,
ce556e0b	307	.instance_size = sizeof(PL022State),
39bffca2	308	.class_init = pl022_class_init,
999e12bb AL	309	};
999e12bb AL	310
83f7d43a	311	static void pl022_register_types(void)
5493e33f	312	{
39bffca2	313	type_register_static(&pl022_info);
5493e33f PB	314	}
5493e33f PB	315
83f7d43a	316	type_init(pl022_register_types)