[mirror_qemu.git] / hw / ssi / pl022.c

/*
 * Arm PrimeCell PL022 Synchronous Serial Port
 *
 * Copyright (c) 2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"
#include "hw/ssi/ssi.h"

//#define DEBUG_PL022 1

#ifdef DEBUG_PL022
#define DPRINTF(fmt, ...) \
do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
#define DPRINTF(fmt, ...) do {} while(0)
#define BADF(fmt, ...) \
do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
#endif

#define PL022_CR1_LBM 0x01
#define PL022_CR1_SSE 0x02
#define PL022_CR1_MS  0x04
#define PL022_CR1_SDO 0x08

#define PL022_SR_TFE  0x01
#define PL022_SR_TNF  0x02
#define PL022_SR_RNE  0x04
#define PL022_SR_RFF  0x08
#define PL022_SR_BSY  0x10

#define PL022_INT_ROR 0x01
#define PL022_INT_RT  0x04
#define PL022_INT_RX  0x04
#define PL022_INT_TX  0x08

#define TYPE_PL022 "pl022"
#define PL022(obj) OBJECT_CHECK(PL022State, (obj), TYPE_PL022)

typedef struct PL022State {
    SysBusDevice parent_obj;

    MemoryRegion iomem;
    uint32_t cr0;
    uint32_t cr1;
    uint32_t bitmask;
    uint32_t sr;
    uint32_t cpsr;
    uint32_t is;
    uint32_t im;
    /* The FIFO head points to the next empty entry.  */
    int tx_fifo_head;
    int rx_fifo_head;
    int tx_fifo_len;
    int rx_fifo_len;
    uint16_t tx_fifo[8];
    uint16_t rx_fifo[8];
    qemu_irq irq;
    SSIBus *ssi;
} PL022State;

static const unsigned char pl022_id[8] =
  { 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };

static void pl022_update(PL022State *s)
{
    s->sr = 0;
    if (s->tx_fifo_len == 0)
        s->sr |= PL022_SR_TFE;
    if (s->tx_fifo_len != 8)
        s->sr |= PL022_SR_TNF;
    if (s->rx_fifo_len != 0)
        s->sr |= PL022_SR_RNE;
    if (s->rx_fifo_len == 8)
        s->sr |= PL022_SR_RFF;
    if (s->tx_fifo_len)
        s->sr |= PL022_SR_BSY;
    s->is = 0;
    if (s->rx_fifo_len >= 4)
        s->is |= PL022_INT_RX;
    if (s->tx_fifo_len <= 4)
        s->is |= PL022_INT_TX;

    qemu_set_irq(s->irq, (s->is & s->im) != 0);
}

static void pl022_xfer(PL022State *s)
{
    int i;
    int o;
    int val;

    if ((s->cr1 & PL022_CR1_SSE) == 0) {
        pl022_update(s);
        DPRINTF("Disabled\n");
        return;
    }

    DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
    i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
    o = s->rx_fifo_head;
    /* ??? We do not emulate the line speed.
       This may break some applications.  The are two problematic cases:
        (a) A driver feeds data into the TX FIFO until it is full,
         and only then drains the RX FIFO.  On real hardware the CPU can
         feed data fast enough that the RX fifo never gets chance to overflow.
        (b) A driver transmits data, deliberately allowing the RX FIFO to
         overflow because it ignores the RX data anyway.

       We choose to support (a) by stalling the transmit engine if it would
       cause the RX FIFO to overflow.  In practice much transmit-only code
       falls into (a) because it flushes the RX FIFO to determine when
       the transfer has completed.  */
    while (s->tx_fifo_len && s->rx_fifo_len < 8) {
        DPRINTF("xfer\n");
        val = s->tx_fifo[i];
        if (s->cr1 & PL022_CR1_LBM) {
            /* Loopback mode.  */
        } else {
            val = ssi_transfer(s->ssi, val);
        }
        s->rx_fifo[o] = val & s->bitmask;
        i = (i + 1) & 7;
        o = (o + 1) & 7;
        s->tx_fifo_len--;
        s->rx_fifo_len++;
    }
    s->rx_fifo_head = o;
    pl022_update(s);
}

static uint64_t pl022_read(void *opaque, hwaddr offset,
                           unsigned size)
{
    PL022State *s = (PL022State *)opaque;
    int val;

    if (offset >= 0xfe0 && offset < 0x1000) {
        return pl022_id[(offset - 0xfe0) >> 2];
    }
    switch (offset) {
    case 0x00: /* CR0 */
      return s->cr0;
    case 0x04: /* CR1 */
      return s->cr1;
    case 0x08: /* DR */
        if (s->rx_fifo_len) {
            val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
            DPRINTF("RX %02x\n", val);
            s->rx_fifo_len--;
            pl022_xfer(s);
        } else {
            val = 0;
        }
        return val;
    case 0x0c: /* SR */
        return s->sr;
    case 0x10: /* CPSR */
        return s->cpsr;
    case 0x14: /* IMSC */
        return s->im;
    case 0x18: /* RIS */
        return s->is;
    case 0x1c: /* MIS */
        return s->im & s->is;
    case 0x20: /* DMACR */
        /* Not implemented.  */
        return 0;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl022_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

static void pl022_write(void *opaque, hwaddr offset,
                        uint64_t value, unsigned size)
{
    PL022State *s = (PL022State *)opaque;

    switch (offset) {
    case 0x00: /* CR0 */
        s->cr0 = value;
        /* Clock rate and format are ignored.  */
        s->bitmask = (1 << ((value & 15) + 1)) - 1;
        break;
    case 0x04: /* CR1 */
        s->cr1 = value;
        if ((s->cr1 & (PL022_CR1_MS | PL022_CR1_SSE))
                   == (PL022_CR1_MS | PL022_CR1_SSE)) {
            BADF("SPI slave mode not implemented\n");
        }
        pl022_xfer(s);
        break;
    case 0x08: /* DR */
        if (s->tx_fifo_len < 8) {
            DPRINTF("TX %02x\n", (unsigned)value);
            s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
            s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
            s->tx_fifo_len++;
            pl022_xfer(s);
        }
        break;
    case 0x10: /* CPSR */
        /* Prescaler.  Ignored.  */
        s->cpsr = value & 0xff;
        break;
    case 0x14: /* IMSC */
        s->im = value;
        pl022_update(s);
        break;
    case 0x20: /* DMACR */
        if (value) {
            qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
        }
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "pl022_write: Bad offset %x\n", (int)offset);
    }
}

static void pl022_reset(PL022State *s)
{
    s->rx_fifo_len = 0;
    s->tx_fifo_len = 0;
    s->im = 0;
    s->is = PL022_INT_TX;
    s->sr = PL022_SR_TFE | PL022_SR_TNF;
}

static const MemoryRegionOps pl022_ops = {
    .read = pl022_read,
    .write = pl022_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static int pl022_post_load(void *opaque, int version_id)
{
    PL022State *s = opaque;

    if (s->tx_fifo_head < 0 ||
        s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) ||
        s->rx_fifo_head < 0 ||
        s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) {
        return -1;
    }
    return 0;
}

static const VMStateDescription vmstate_pl022 = {
    .name = "pl022_ssp",
    .version_id = 1,
    .minimum_version_id = 1,
    .post_load = pl022_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(cr0, PL022State),
        VMSTATE_UINT32(cr1, PL022State),
        VMSTATE_UINT32(bitmask, PL022State),
        VMSTATE_UINT32(sr, PL022State),
        VMSTATE_UINT32(cpsr, PL022State),
        VMSTATE_UINT32(is, PL022State),
        VMSTATE_UINT32(im, PL022State),
        VMSTATE_INT32(tx_fifo_head, PL022State),
        VMSTATE_INT32(rx_fifo_head, PL022State),
        VMSTATE_INT32(tx_fifo_len, PL022State),
        VMSTATE_INT32(rx_fifo_len, PL022State),
        VMSTATE_UINT16(tx_fifo[0], PL022State),
        VMSTATE_UINT16(rx_fifo[0], PL022State),
        VMSTATE_UINT16(tx_fifo[1], PL022State),
        VMSTATE_UINT16(rx_fifo[1], PL022State),
        VMSTATE_UINT16(tx_fifo[2], PL022State),
        VMSTATE_UINT16(rx_fifo[2], PL022State),
        VMSTATE_UINT16(tx_fifo[3], PL022State),
        VMSTATE_UINT16(rx_fifo[3], PL022State),
        VMSTATE_UINT16(tx_fifo[4], PL022State),
        VMSTATE_UINT16(rx_fifo[4], PL022State),
        VMSTATE_UINT16(tx_fifo[5], PL022State),
        VMSTATE_UINT16(rx_fifo[5], PL022State),
        VMSTATE_UINT16(tx_fifo[6], PL022State),
        VMSTATE_UINT16(rx_fifo[6], PL022State),
        VMSTATE_UINT16(tx_fifo[7], PL022State),
        VMSTATE_UINT16(rx_fifo[7], PL022State),
        VMSTATE_END_OF_LIST()
    }
};

static int pl022_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    PL022State *s = PL022(dev);

    memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
    sysbus_init_mmio(sbd, &s->iomem);
    sysbus_init_irq(sbd, &s->irq);
    s->ssi = ssi_create_bus(dev, "ssi");
    pl022_reset(s);
    vmstate_register(dev, -1, &vmstate_pl022, s);
    return 0;
}

static void pl022_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);

    sdc->init = pl022_init;
}

static const TypeInfo pl022_info = {
    .name          = TYPE_PL022,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(PL022State),
    .class_init    = pl022_class_init,
};

static void pl022_register_types(void)
{
    type_register_static(&pl022_info);
}

type_init(pl022_register_types)
Commit	Line	Data
9ee6e8bb PB	1	/*
	2	* Arm PrimeCell PL022 Synchronous Serial Port
	3	*
	4	* Copyright (c) 2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
9ee6e8bb PB	8	*/
9ee6e8bb PB	9
83c9f4ca	10	#include "hw/sysbus.h"
8fd06719	11	#include "hw/ssi/ssi.h"
9ee6e8bb PB	12
	13	//#define DEBUG_PL022 1
	14
	15	#ifdef DEBUG_PL022
001faf32 BS	16	#define DPRINTF(fmt, ...) \
	17	do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
	18	#define BADF(fmt, ...) \
	19	do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
9ee6e8bb	20	#else
001faf32 BS	21	#define DPRINTF(fmt, ...) do {} while(0)
	22	#define BADF(fmt, ...) \
	23	do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
9ee6e8bb PB	24	#endif
	25
	26	#define PL022_CR1_LBM 0x01
	27	#define PL022_CR1_SSE 0x02
	28	#define PL022_CR1_MS 0x04
	29	#define PL022_CR1_SDO 0x08
	30
	31	#define PL022_SR_TFE 0x01
	32	#define PL022_SR_TNF 0x02
	33	#define PL022_SR_RNE 0x04
	34	#define PL022_SR_RFF 0x08
	35	#define PL022_SR_BSY 0x10
	36
	37	#define PL022_INT_ROR 0x01
	38	#define PL022_INT_RT 0x04
	39	#define PL022_INT_RX 0x04
	40	#define PL022_INT_TX 0x08
	41
3d29bcee AF	42	#define TYPE_PL022 "pl022"
	43	#define PL022(obj) OBJECT_CHECK(PL022State, (obj), TYPE_PL022)
	44
ce556e0b	45	typedef struct PL022State {
3d29bcee AF	46	SysBusDevice parent_obj;
3d29bcee AF	47
02a59c37	48	MemoryRegion iomem;
9ee6e8bb PB	49	uint32_t cr0;
	50	uint32_t cr1;
	51	uint32_t bitmask;
	52	uint32_t sr;
	53	uint32_t cpsr;
	54	uint32_t is;
	55	uint32_t im;
	56	/* The FIFO head points to the next empty entry. */
	57	int tx_fifo_head;
	58	int rx_fifo_head;
	59	int tx_fifo_len;
	60	int rx_fifo_len;
	61	uint16_t tx_fifo[8];
	62	uint16_t rx_fifo[8];
	63	qemu_irq irq;
5493e33f	64	SSIBus *ssi;
ce556e0b	65	} PL022State;
9ee6e8bb PB	66
	67	static const unsigned char pl022_id[8] =
	68	{ 0x22, 0x10, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
	69
ce556e0b	70	static void pl022_update(PL022State *s)
9ee6e8bb PB	71	{
	72	s->sr = 0;
	73	if (s->tx_fifo_len == 0)
	74	s->sr \|= PL022_SR_TFE;
	75	if (s->tx_fifo_len != 8)
	76	s->sr \|= PL022_SR_TNF;
	77	if (s->rx_fifo_len != 0)
	78	s->sr \|= PL022_SR_RNE;
	79	if (s->rx_fifo_len == 8)
	80	s->sr \|= PL022_SR_RFF;
	81	if (s->tx_fifo_len)
	82	s->sr \|= PL022_SR_BSY;
	83	s->is = 0;
	84	if (s->rx_fifo_len >= 4)
	85	s->is \|= PL022_INT_RX;
	86	if (s->tx_fifo_len <= 4)
	87	s->is \|= PL022_INT_TX;
	88
	89	qemu_set_irq(s->irq, (s->is & s->im) != 0);
	90	}
	91
ce556e0b	92	static void pl022_xfer(PL022State *s)
9ee6e8bb PB	93	{
	94	int i;
	95	int o;
	96	int val;
	97
	98	if ((s->cr1 & PL022_CR1_SSE) == 0) {
	99	pl022_update(s);
	100	DPRINTF("Disabled\n");
	101	return;
	102	}
	103
	104	DPRINTF("Maybe xfer %d/%d\n", s->tx_fifo_len, s->rx_fifo_len);
	105	i = (s->tx_fifo_head - s->tx_fifo_len) & 7;
	106	o = s->rx_fifo_head;
	107	/* ??? We do not emulate the line speed.
	108	This may break some applications. The are two problematic cases:
	109	(a) A driver feeds data into the TX FIFO until it is full,
	110	and only then drains the RX FIFO. On real hardware the CPU can
	111	feed data fast enough that the RX fifo never gets chance to overflow.
	112	(b) A driver transmits data, deliberately allowing the RX FIFO to
	113	overflow because it ignores the RX data anyway.
	114
	115	We choose to support (a) by stalling the transmit engine if it would
	116	cause the RX FIFO to overflow. In practice much transmit-only code
	117	falls into (a) because it flushes the RX FIFO to determine when
	118	the transfer has completed. */
	119	while (s->tx_fifo_len && s->rx_fifo_len < 8) {
	120	DPRINTF("xfer\n");
	121	val = s->tx_fifo[i];
	122	if (s->cr1 & PL022_CR1_LBM) {
	123	/* Loopback mode. */
9ee6e8bb	124	} else {
5493e33f	125	val = ssi_transfer(s->ssi, val);
9ee6e8bb PB	126	}
	127	s->rx_fifo[o] = val & s->bitmask;
	128	i = (i + 1) & 7;
	129	o = (o + 1) & 7;
	130	s->tx_fifo_len--;
	131	s->rx_fifo_len++;
	132	}
	133	s->rx_fifo_head = o;
	134	pl022_update(s);
	135	}
	136
a8170e5e	137	static uint64_t pl022_read(void *opaque, hwaddr offset,
02a59c37	138	unsigned size)
9ee6e8bb	139	{
ce556e0b	140	PL022State s = (PL022State )opaque;
9ee6e8bb PB	141	int val;
9ee6e8bb PB	142
9ee6e8bb PB	143	if (offset >= 0xfe0 && offset < 0x1000) {
	144	return pl022_id[(offset - 0xfe0) >> 2];
	145	}
	146	switch (offset) {
	147	case 0x00: /* CR0 */
	148	return s->cr0;
	149	case 0x04: /* CR1 */
	150	return s->cr1;
	151	case 0x08: /* DR */
	152	if (s->rx_fifo_len) {
	153	val = s->rx_fifo[(s->rx_fifo_head - s->rx_fifo_len) & 7];
	154	DPRINTF("RX %02x\n", val);
	155	s->rx_fifo_len--;
	156	pl022_xfer(s);
	157	} else {
	158	val = 0;
	159	}
	160	return val;
	161	case 0x0c: /* SR */
	162	return s->sr;
	163	case 0x10: /* CPSR */
	164	return s->cpsr;
	165	case 0x14: /* IMSC */
	166	return s->im;
	167	case 0x18: /* RIS */
	168	return s->is;
	169	case 0x1c: /* MIS */
	170	return s->im & s->is;
	171	case 0x20: /* DMACR */
	172	/* Not implemented. */
	173	return 0;
	174	default:
af83c32b PM	175	qemu_log_mask(LOG_GUEST_ERROR,
af83c32b PM	176	"pl022_read: Bad offset %x\n", (int)offset);
9ee6e8bb PB	177	return 0;
	178	}
	179	}
	180
a8170e5e	181	static void pl022_write(void *opaque, hwaddr offset,
02a59c37	182	uint64_t value, unsigned size)
9ee6e8bb	183	{
ce556e0b	184	PL022State s = (PL022State )opaque;
9ee6e8bb	185
9ee6e8bb PB	186	switch (offset) {
	187	case 0x00: /* CR0 */
	188	s->cr0 = value;
	189	/* Clock rate and format are ignored. */
	190	s->bitmask = (1 << ((value & 15) + 1)) - 1;
	191	break;
	192	case 0x04: /* CR1 */
	193	s->cr1 = value;
	194	if ((s->cr1 & (PL022_CR1_MS \| PL022_CR1_SSE))
	195	== (PL022_CR1_MS \| PL022_CR1_SSE)) {
	196	BADF("SPI slave mode not implemented\n");
	197	}
	198	pl022_xfer(s);
	199	break;
	200	case 0x08: /* DR */
	201	if (s->tx_fifo_len < 8) {
02a59c37	202	DPRINTF("TX %02x\n", (unsigned)value);
9ee6e8bb PB	203	s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
	204	s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
	205	s->tx_fifo_len++;
	206	pl022_xfer(s);
	207	}
	208	break;
	209	case 0x10: /* CPSR */
	210	/* Prescaler. Ignored. */
	211	s->cpsr = value & 0xff;
	212	break;
	213	case 0x14: /* IMSC */
	214	s->im = value;
	215	pl022_update(s);
	216	break;
	217	case 0x20: /* DMACR */
2ac71179	218	if (value) {
af83c32b	219	qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
2ac71179	220	}
9ee6e8bb PB	221	break;
9ee6e8bb PB	222	default:
af83c32b PM	223	qemu_log_mask(LOG_GUEST_ERROR,
af83c32b PM	224	"pl022_write: Bad offset %x\n", (int)offset);
9ee6e8bb PB	225	}
	226	}
	227
ce556e0b	228	static void pl022_reset(PL022State *s)
9ee6e8bb PB	229	{
	230	s->rx_fifo_len = 0;
	231	s->tx_fifo_len = 0;
	232	s->im = 0;
	233	s->is = PL022_INT_TX;
	234	s->sr = PL022_SR_TFE \| PL022_SR_TNF;
	235	}
	236
02a59c37 AK	237	static const MemoryRegionOps pl022_ops = {
	238	.read = pl022_read,
	239	.write = pl022_write,
	240	.endianness = DEVICE_NATIVE_ENDIAN,
9ee6e8bb PB	241	};
9ee6e8bb PB	242
d8d0a0bc MT	243	static int pl022_post_load(void *opaque, int version_id)
	244	{
	245	PL022State *s = opaque;
	246
	247	if (s->tx_fifo_head < 0 \|\|
	248	s->tx_fifo_head >= ARRAY_SIZE(s->tx_fifo) \|\|
	249	s->rx_fifo_head < 0 \|\|
	250	s->rx_fifo_head >= ARRAY_SIZE(s->rx_fifo)) {
	251	return -1;
	252	}
	253	return 0;
	254	}
	255
075790c2 JQ	256	static const VMStateDescription vmstate_pl022 = {
	257	.name = "pl022_ssp",
	258	.version_id = 1,
	259	.minimum_version_id = 1,
d8d0a0bc	260	.post_load = pl022_post_load,
8f1e884b	261	.fields = (VMStateField[]) {
ce556e0b AF	262	VMSTATE_UINT32(cr0, PL022State),
	263	VMSTATE_UINT32(cr1, PL022State),
	264	VMSTATE_UINT32(bitmask, PL022State),
	265	VMSTATE_UINT32(sr, PL022State),
	266	VMSTATE_UINT32(cpsr, PL022State),
	267	VMSTATE_UINT32(is, PL022State),
	268	VMSTATE_UINT32(im, PL022State),
	269	VMSTATE_INT32(tx_fifo_head, PL022State),
	270	VMSTATE_INT32(rx_fifo_head, PL022State),
	271	VMSTATE_INT32(tx_fifo_len, PL022State),
	272	VMSTATE_INT32(rx_fifo_len, PL022State),
	273	VMSTATE_UINT16(tx_fifo[0], PL022State),
	274	VMSTATE_UINT16(rx_fifo[0], PL022State),
	275	VMSTATE_UINT16(tx_fifo[1], PL022State),
	276	VMSTATE_UINT16(rx_fifo[1], PL022State),
	277	VMSTATE_UINT16(tx_fifo[2], PL022State),
	278	VMSTATE_UINT16(rx_fifo[2], PL022State),
	279	VMSTATE_UINT16(tx_fifo[3], PL022State),
	280	VMSTATE_UINT16(rx_fifo[3], PL022State),
	281	VMSTATE_UINT16(tx_fifo[4], PL022State),
	282	VMSTATE_UINT16(rx_fifo[4], PL022State),
	283	VMSTATE_UINT16(tx_fifo[5], PL022State),
	284	VMSTATE_UINT16(rx_fifo[5], PL022State),
	285	VMSTATE_UINT16(tx_fifo[6], PL022State),
	286	VMSTATE_UINT16(rx_fifo[6], PL022State),
	287	VMSTATE_UINT16(tx_fifo[7], PL022State),
	288	VMSTATE_UINT16(rx_fifo[7], PL022State),
075790c2	289	VMSTATE_END_OF_LIST()
23e39294	290	}
075790c2	291	};
23e39294	292
3d29bcee	293	static int pl022_init(SysBusDevice *sbd)
9ee6e8bb	294	{
3d29bcee AF	295	DeviceState *dev = DEVICE(sbd);
3d29bcee AF	296	PL022State *s = PL022(dev);
9ee6e8bb	297
29776739	298	memory_region_init_io(&s->iomem, OBJECT(s), &pl022_ops, s, "pl022", 0x1000);
3d29bcee AF	299	sysbus_init_mmio(sbd, &s->iomem);
	300	sysbus_init_irq(sbd, &s->irq);
	301	s->ssi = ssi_create_bus(dev, "ssi");
9ee6e8bb	302	pl022_reset(s);
3d29bcee	303	vmstate_register(dev, -1, &vmstate_pl022, s);
81a322d4	304	return 0;
9ee6e8bb	305	}
5493e33f	306
999e12bb AL	307	static void pl022_class_init(ObjectClass klass, void data)
	308	{
	309	SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
	310
	311	sdc->init = pl022_init;
	312	}
	313
8c43a6f0	314	static const TypeInfo pl022_info = {
3d29bcee	315	.name = TYPE_PL022,
39bffca2	316	.parent = TYPE_SYS_BUS_DEVICE,
ce556e0b	317	.instance_size = sizeof(PL022State),
39bffca2	318	.class_init = pl022_class_init,
999e12bb AL	319	};
999e12bb AL	320
83f7d43a	321	static void pl022_register_types(void)
5493e33f	322	{
39bffca2	323	type_register_static(&pl022_info);
5493e33f PB	324	}
5493e33f PB	325
83f7d43a	326	type_init(pl022_register_types)