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Commit | Line | Data |
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420557e8 | 1 | /* |
ee76f82e | 2 | * QEMU Sun4m & Sun4d & Sun4c System Emulator |
5fafdf24 | 3 | * |
b81b3b10 | 4 | * Copyright (c) 2003-2005 Fabrice Bellard |
5fafdf24 | 5 | * |
420557e8 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
87ecb68b PB |
24 | #include "hw.h" |
25 | #include "qemu-timer.h" | |
26 | #include "sun4m.h" | |
27 | #include "nvram.h" | |
28 | #include "sparc32_dma.h" | |
29 | #include "fdc.h" | |
30 | #include "sysemu.h" | |
31 | #include "net.h" | |
32 | #include "boards.h" | |
d2c63fc1 BS |
33 | #include "firmware_abi.h" |
34 | ||
b3a23197 | 35 | //#define DEBUG_IRQ |
420557e8 | 36 | |
36cd9210 BS |
37 | /* |
38 | * Sun4m architecture was used in the following machines: | |
39 | * | |
40 | * SPARCserver 6xxMP/xx | |
41 | * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15), SPARCclassic X (4/10) | |
42 | * SPARCstation LX/ZX (4/30) | |
43 | * SPARCstation Voyager | |
44 | * SPARCstation 10/xx, SPARCserver 10/xx | |
45 | * SPARCstation 5, SPARCserver 5 | |
46 | * SPARCstation 20/xx, SPARCserver 20 | |
47 | * SPARCstation 4 | |
48 | * | |
7d85892b BS |
49 | * Sun4d architecture was used in the following machines: |
50 | * | |
51 | * SPARCcenter 2000 | |
52 | * SPARCserver 1000 | |
53 | * | |
ee76f82e BS |
54 | * Sun4c architecture was used in the following machines: |
55 | * SPARCstation 1/1+, SPARCserver 1/1+ | |
56 | * SPARCstation SLC | |
57 | * SPARCstation IPC | |
58 | * SPARCstation ELC | |
59 | * SPARCstation IPX | |
60 | * | |
36cd9210 BS |
61 | * See for example: http://www.sunhelp.org/faq/sunref1.html |
62 | */ | |
63 | ||
b3a23197 BS |
64 | #ifdef DEBUG_IRQ |
65 | #define DPRINTF(fmt, args...) \ | |
66 | do { printf("CPUIRQ: " fmt , ##args); } while (0) | |
67 | #else | |
68 | #define DPRINTF(fmt, args...) | |
69 | #endif | |
70 | ||
420557e8 | 71 | #define KERNEL_LOAD_ADDR 0x00004000 |
b6f479d3 | 72 | #define CMDLINE_ADDR 0x007ff000 |
713c45fa | 73 | #define INITRD_LOAD_ADDR 0x00800000 |
aa6ad6fe | 74 | #define PROM_SIZE_MAX (512 * 1024) |
40ce0a9a | 75 | #define PROM_VADDR 0xffd00000 |
f930d07e | 76 | #define PROM_FILENAME "openbios-sparc32" |
b8174937 | 77 | |
ba3c64fb | 78 | #define MAX_CPUS 16 |
b3a23197 | 79 | #define MAX_PILS 16 |
420557e8 | 80 | |
36cd9210 | 81 | struct hwdef { |
5dcb6b91 BS |
82 | target_phys_addr_t iommu_base, slavio_base; |
83 | target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base; | |
84 | target_phys_addr_t serial_base, fd_base; | |
4c2485de | 85 | target_phys_addr_t idreg_base, dma_base, esp_base, le_base; |
5dcb6b91 | 86 | target_phys_addr_t tcx_base, cs_base, power_base; |
7eb0c8e8 BS |
87 | target_phys_addr_t ecc_base; |
88 | uint32_t ecc_version; | |
ee76f82e | 89 | target_phys_addr_t sun4c_intctl_base, sun4c_counter_base; |
36cd9210 | 90 | long vram_size, nvram_size; |
6341fdcb BS |
91 | // IRQ numbers are not PIL ones, but master interrupt controller |
92 | // register bit numbers except for clock_irq, which indexes cpu | |
93 | // interrupt controller register | |
d7edfd27 | 94 | int intctl_g_intr, esp_irq, le_irq, clock_irq, clock1_irq; |
36cd9210 BS |
95 | int ser_irq, ms_kb_irq, fd_irq, me_irq, cs_irq; |
96 | int machine_id; // For NVRAM | |
7fbfb139 | 97 | uint32_t iommu_version; |
e0353fe2 | 98 | uint32_t intbit_to_level[32]; |
3ebf5aaf BS |
99 | uint64_t max_mem; |
100 | const char * const default_cpu_model; | |
36cd9210 BS |
101 | }; |
102 | ||
7d85892b BS |
103 | #define MAX_IOUNITS 5 |
104 | ||
105 | struct sun4d_hwdef { | |
106 | target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base; | |
107 | target_phys_addr_t counter_base, nvram_base, ms_kb_base; | |
108 | target_phys_addr_t serial_base; | |
109 | target_phys_addr_t espdma_base, esp_base; | |
110 | target_phys_addr_t ledma_base, le_base; | |
111 | target_phys_addr_t tcx_base; | |
112 | target_phys_addr_t sbi_base; | |
113 | unsigned long vram_size, nvram_size; | |
114 | // IRQ numbers are not PIL ones, but SBI register bit numbers | |
115 | int esp_irq, le_irq, clock_irq, clock1_irq; | |
116 | int ser_irq, ms_kb_irq, me_irq; | |
117 | int machine_id; // For NVRAM | |
118 | uint32_t iounit_version; | |
119 | uint64_t max_mem; | |
120 | const char * const default_cpu_model; | |
121 | }; | |
122 | ||
420557e8 FB |
123 | /* TSC handling */ |
124 | ||
125 | uint64_t cpu_get_tsc() | |
126 | { | |
127 | return qemu_get_clock(vm_clock); | |
128 | } | |
129 | ||
6f7e9aec FB |
130 | int DMA_get_channel_mode (int nchan) |
131 | { | |
132 | return 0; | |
133 | } | |
134 | int DMA_read_memory (int nchan, void *buf, int pos, int size) | |
135 | { | |
136 | return 0; | |
137 | } | |
138 | int DMA_write_memory (int nchan, void *buf, int pos, int size) | |
139 | { | |
140 | return 0; | |
141 | } | |
142 | void DMA_hold_DREQ (int nchan) {} | |
143 | void DMA_release_DREQ (int nchan) {} | |
144 | void DMA_schedule(int nchan) {} | |
145 | void DMA_run (void) {} | |
146 | void DMA_init (int high_page_enable) {} | |
147 | void DMA_register_channel (int nchan, | |
148 | DMA_transfer_handler transfer_handler, | |
149 | void *opaque) | |
150 | { | |
151 | } | |
152 | ||
6f7e9aec FB |
153 | extern int nographic; |
154 | ||
819385c5 | 155 | static void nvram_init(m48t59_t *nvram, uint8_t *macaddr, const char *cmdline, |
d2c63fc1 | 156 | const char *boot_devices, uint32_t RAM_size, |
f930d07e BS |
157 | uint32_t kernel_size, |
158 | int width, int height, int depth, | |
7d85892b | 159 | int machine_id, const char *arch) |
e80cfcfc | 160 | { |
d2c63fc1 | 161 | unsigned int i; |
66508601 | 162 | uint32_t start, end; |
d2c63fc1 BS |
163 | uint8_t image[0x1ff0]; |
164 | ohwcfg_v3_t *header = (ohwcfg_v3_t *)ℑ | |
165 | struct sparc_arch_cfg *sparc_header; | |
166 | struct OpenBIOS_nvpart_v1 *part_header; | |
167 | ||
168 | memset(image, '\0', sizeof(image)); | |
e80cfcfc | 169 | |
6f7e9aec | 170 | // Try to match PPC NVRAM |
d2c63fc1 BS |
171 | strcpy(header->struct_ident, "QEMU_BIOS"); |
172 | header->struct_version = cpu_to_be32(3); /* structure v3 */ | |
173 | ||
174 | header->nvram_size = cpu_to_be16(0x2000); | |
175 | header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t)); | |
176 | header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg)); | |
7d85892b | 177 | strcpy(header->arch, arch); |
d2c63fc1 BS |
178 | header->nb_cpus = smp_cpus & 0xff; |
179 | header->RAM0_base = 0; | |
180 | header->RAM0_size = cpu_to_be64((uint64_t)RAM_size); | |
181 | strcpy(header->boot_devices, boot_devices); | |
182 | header->nboot_devices = strlen(boot_devices) & 0xff; | |
183 | header->kernel_image = cpu_to_be64((uint64_t)KERNEL_LOAD_ADDR); | |
184 | header->kernel_size = cpu_to_be64((uint64_t)kernel_size); | |
b6f479d3 | 185 | if (cmdline) { |
f930d07e | 186 | strcpy(phys_ram_base + CMDLINE_ADDR, cmdline); |
d2c63fc1 BS |
187 | header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR); |
188 | header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline)); | |
b6f479d3 | 189 | } |
d2c63fc1 BS |
190 | // XXX add initrd_image, initrd_size |
191 | header->width = cpu_to_be16(width); | |
192 | header->height = cpu_to_be16(height); | |
193 | header->depth = cpu_to_be16(depth); | |
194 | if (nographic) | |
195 | header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS); | |
196 | ||
197 | header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8)); | |
198 | ||
199 | // Architecture specific header | |
200 | start = sizeof(ohwcfg_v3_t); | |
201 | sparc_header = (struct sparc_arch_cfg *)&image[start]; | |
202 | sparc_header->valid = 0; | |
203 | start += sizeof(struct sparc_arch_cfg); | |
b6f479d3 | 204 | |
66508601 BS |
205 | // OpenBIOS nvram variables |
206 | // Variable partition | |
d2c63fc1 BS |
207 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
208 | part_header->signature = OPENBIOS_PART_SYSTEM; | |
209 | strcpy(part_header->name, "system"); | |
66508601 | 210 | |
d2c63fc1 | 211 | end = start + sizeof(struct OpenBIOS_nvpart_v1); |
66508601 | 212 | for (i = 0; i < nb_prom_envs; i++) |
d2c63fc1 BS |
213 | end = OpenBIOS_set_var(image, end, prom_envs[i]); |
214 | ||
215 | // End marker | |
216 | image[end++] = '\0'; | |
66508601 | 217 | |
66508601 | 218 | end = start + ((end - start + 15) & ~15); |
d2c63fc1 | 219 | OpenBIOS_finish_partition(part_header, end - start); |
66508601 BS |
220 | |
221 | // free partition | |
222 | start = end; | |
d2c63fc1 BS |
223 | part_header = (struct OpenBIOS_nvpart_v1 *)&image[start]; |
224 | part_header->signature = OPENBIOS_PART_FREE; | |
225 | strcpy(part_header->name, "free"); | |
66508601 BS |
226 | |
227 | end = 0x1fd0; | |
d2c63fc1 BS |
228 | OpenBIOS_finish_partition(part_header, end - start); |
229 | ||
230 | Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, machine_id); | |
231 | ||
232 | for (i = 0; i < sizeof(image); i++) | |
233 | m48t59_write(nvram, i, image[i]); | |
e80cfcfc FB |
234 | } |
235 | ||
236 | static void *slavio_intctl; | |
237 | ||
238 | void pic_info() | |
239 | { | |
7d85892b BS |
240 | if (slavio_intctl) |
241 | slavio_pic_info(slavio_intctl); | |
e80cfcfc FB |
242 | } |
243 | ||
244 | void irq_info() | |
245 | { | |
7d85892b BS |
246 | if (slavio_intctl) |
247 | slavio_irq_info(slavio_intctl); | |
e80cfcfc FB |
248 | } |
249 | ||
327ac2e7 BS |
250 | void cpu_check_irqs(CPUState *env) |
251 | { | |
252 | if (env->pil_in && (env->interrupt_index == 0 || | |
253 | (env->interrupt_index & ~15) == TT_EXTINT)) { | |
254 | unsigned int i; | |
255 | ||
256 | for (i = 15; i > 0; i--) { | |
257 | if (env->pil_in & (1 << i)) { | |
258 | int old_interrupt = env->interrupt_index; | |
259 | ||
260 | env->interrupt_index = TT_EXTINT | i; | |
261 | if (old_interrupt != env->interrupt_index) | |
262 | cpu_interrupt(env, CPU_INTERRUPT_HARD); | |
263 | break; | |
264 | } | |
265 | } | |
266 | } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) { | |
267 | env->interrupt_index = 0; | |
268 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); | |
269 | } | |
270 | } | |
271 | ||
b3a23197 BS |
272 | static void cpu_set_irq(void *opaque, int irq, int level) |
273 | { | |
274 | CPUState *env = opaque; | |
275 | ||
276 | if (level) { | |
277 | DPRINTF("Raise CPU IRQ %d\n", irq); | |
b3a23197 | 278 | env->halted = 0; |
327ac2e7 BS |
279 | env->pil_in |= 1 << irq; |
280 | cpu_check_irqs(env); | |
b3a23197 BS |
281 | } else { |
282 | DPRINTF("Lower CPU IRQ %d\n", irq); | |
327ac2e7 BS |
283 | env->pil_in &= ~(1 << irq); |
284 | cpu_check_irqs(env); | |
b3a23197 BS |
285 | } |
286 | } | |
287 | ||
288 | static void dummy_cpu_set_irq(void *opaque, int irq, int level) | |
289 | { | |
290 | } | |
291 | ||
3475187d FB |
292 | static void *slavio_misc; |
293 | ||
294 | void qemu_system_powerdown(void) | |
295 | { | |
296 | slavio_set_power_fail(slavio_misc, 1); | |
297 | } | |
298 | ||
c68ea704 FB |
299 | static void main_cpu_reset(void *opaque) |
300 | { | |
301 | CPUState *env = opaque; | |
3d29fbef BS |
302 | |
303 | cpu_reset(env); | |
304 | env->halted = 0; | |
305 | } | |
306 | ||
307 | static void secondary_cpu_reset(void *opaque) | |
308 | { | |
309 | CPUState *env = opaque; | |
310 | ||
c68ea704 | 311 | cpu_reset(env); |
3d29fbef | 312 | env->halted = 1; |
c68ea704 FB |
313 | } |
314 | ||
3ebf5aaf BS |
315 | static unsigned long sun4m_load_kernel(const char *kernel_filename, |
316 | const char *kernel_cmdline, | |
317 | const char *initrd_filename) | |
318 | { | |
319 | int linux_boot; | |
320 | unsigned int i; | |
321 | long initrd_size, kernel_size; | |
322 | ||
323 | linux_boot = (kernel_filename != NULL); | |
324 | ||
325 | kernel_size = 0; | |
326 | if (linux_boot) { | |
327 | kernel_size = load_elf(kernel_filename, -0xf0000000ULL, NULL, NULL, | |
328 | NULL); | |
329 | if (kernel_size < 0) | |
330 | kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
331 | if (kernel_size < 0) | |
332 | kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR); | |
333 | if (kernel_size < 0) { | |
334 | fprintf(stderr, "qemu: could not load kernel '%s'\n", | |
335 | kernel_filename); | |
336 | exit(1); | |
337 | } | |
338 | ||
339 | /* load initrd */ | |
340 | initrd_size = 0; | |
341 | if (initrd_filename) { | |
342 | initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR); | |
343 | if (initrd_size < 0) { | |
344 | fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", | |
345 | initrd_filename); | |
346 | exit(1); | |
347 | } | |
348 | } | |
349 | if (initrd_size > 0) { | |
350 | for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) { | |
351 | if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i) | |
352 | == 0x48647253) { // HdrS | |
353 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR); | |
354 | stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size); | |
355 | break; | |
356 | } | |
357 | } | |
358 | } | |
359 | } | |
360 | return kernel_size; | |
361 | } | |
362 | ||
363 | static void sun4m_hw_init(const struct hwdef *hwdef, int RAM_size, | |
364 | const char *boot_device, | |
365 | DisplayState *ds, const char *kernel_filename, | |
366 | const char *kernel_cmdline, | |
367 | const char *initrd_filename, const char *cpu_model) | |
36cd9210 | 368 | |
420557e8 | 369 | { |
ba3c64fb | 370 | CPUState *env, *envs[MAX_CPUS]; |
713c45fa | 371 | unsigned int i; |
b3ceef24 | 372 | void *iommu, *espdma, *ledma, *main_esp, *nvram; |
b3a23197 | 373 | qemu_irq *cpu_irqs[MAX_CPUS], *slavio_irq, *slavio_cpu_irq, |
d7edfd27 | 374 | *espdma_irq, *ledma_irq; |
2d069bab | 375 | qemu_irq *esp_reset, *le_reset; |
3ebf5aaf BS |
376 | unsigned long prom_offset, kernel_size; |
377 | int ret; | |
378 | char buf[1024]; | |
e4bcb14c TS |
379 | BlockDriverState *fd[MAX_FD]; |
380 | int index; | |
420557e8 | 381 | |
ba3c64fb | 382 | /* init CPUs */ |
3ebf5aaf BS |
383 | if (!cpu_model) |
384 | cpu_model = hwdef->default_cpu_model; | |
b3a23197 | 385 | |
ba3c64fb | 386 | for(i = 0; i < smp_cpus; i++) { |
aaed909a FB |
387 | env = cpu_init(cpu_model); |
388 | if (!env) { | |
389 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); | |
390 | exit(1); | |
391 | } | |
392 | cpu_sparc_set_id(env, i); | |
ba3c64fb | 393 | envs[i] = env; |
3d29fbef BS |
394 | if (i == 0) { |
395 | qemu_register_reset(main_cpu_reset, env); | |
396 | } else { | |
397 | qemu_register_reset(secondary_cpu_reset, env); | |
ba3c64fb | 398 | env->halted = 1; |
3d29fbef | 399 | } |
ba3c64fb | 400 | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); |
b3a23197 | 401 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); |
3ebf5aaf | 402 | env->prom_addr = hwdef->slavio_base; |
ba3c64fb | 403 | } |
b3a23197 BS |
404 | |
405 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
406 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
407 | ||
3ebf5aaf | 408 | |
420557e8 | 409 | /* allocate RAM */ |
3ebf5aaf BS |
410 | if ((uint64_t)RAM_size > hwdef->max_mem) { |
411 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", | |
412 | (unsigned int)RAM_size / (1024 * 1024), | |
413 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); | |
414 | exit(1); | |
415 | } | |
b3ceef24 | 416 | cpu_register_physical_memory(0, RAM_size, 0); |
420557e8 | 417 | |
3ebf5aaf BS |
418 | /* load boot prom */ |
419 | prom_offset = RAM_size + hwdef->vram_size; | |
420 | cpu_register_physical_memory(hwdef->slavio_base, | |
421 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
422 | TARGET_PAGE_MASK, | |
423 | prom_offset | IO_MEM_ROM); | |
424 | ||
425 | if (bios_name == NULL) | |
426 | bios_name = PROM_FILENAME; | |
427 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
428 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
429 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
430 | ret = load_image(buf, phys_ram_base + prom_offset); | |
431 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
432 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
433 | buf); | |
434 | exit(1); | |
435 | } | |
4c2485de | 436 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; |
3ebf5aaf BS |
437 | |
438 | /* set up devices */ | |
36cd9210 | 439 | slavio_intctl = slavio_intctl_init(hwdef->intctl_base, |
5dcb6b91 | 440 | hwdef->intctl_base + 0x10000ULL, |
d537cf6c | 441 | &hwdef->intbit_to_level[0], |
d7edfd27 | 442 | &slavio_irq, &slavio_cpu_irq, |
b3a23197 | 443 | cpu_irqs, |
d7edfd27 | 444 | hwdef->clock_irq); |
b3a23197 | 445 | |
4c2485de BS |
446 | if (hwdef->idreg_base != (target_phys_addr_t)-1) { |
447 | stl_raw(phys_ram_base + prom_offset, 0xfe810103); | |
448 | ||
449 | cpu_register_physical_memory(hwdef->idreg_base, sizeof(uint32_t), | |
450 | prom_offset | IO_MEM_ROM); | |
451 | } | |
452 | ||
ff403da6 BS |
453 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
454 | slavio_irq[hwdef->me_irq]); | |
455 | ||
5aca8c3b | 456 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], |
2d069bab BS |
457 | iommu, &espdma_irq, &esp_reset); |
458 | ||
5aca8c3b | 459 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, |
2d069bab BS |
460 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, |
461 | &le_reset); | |
ba3c64fb | 462 | |
eee0b836 BS |
463 | if (graphic_depth != 8 && graphic_depth != 24) { |
464 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
465 | exit (1); | |
466 | } | |
b3ceef24 | 467 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, |
eee0b836 | 468 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); |
dbe06e18 BS |
469 | |
470 | if (nd_table[0].model == NULL | |
471 | || strcmp(nd_table[0].model, "lance") == 0) { | |
2d069bab | 472 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); |
c4a7060c BS |
473 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
474 | fprintf(stderr, "qemu: Supported NICs: lance\n"); | |
475 | exit (1); | |
dbe06e18 BS |
476 | } else { |
477 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
478 | exit (1); | |
a41b2ff2 | 479 | } |
dbe06e18 | 480 | |
d537cf6c PB |
481 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, |
482 | hwdef->nvram_size, 8); | |
81732d19 BS |
483 | |
484 | slavio_timer_init_all(hwdef->counter_base, slavio_irq[hwdef->clock1_irq], | |
19f8e5dd | 485 | slavio_cpu_irq, smp_cpus); |
81732d19 | 486 | |
577390ff BS |
487 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], |
488 | nographic); | |
b81b3b10 FB |
489 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device |
490 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
d537cf6c PB |
491 | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], |
492 | serial_hds[1], serial_hds[0]); | |
741402f9 | 493 | |
e4bcb14c TS |
494 | if (hwdef->fd_base != (target_phys_addr_t)-1) { |
495 | /* there is zero or one floppy drive */ | |
496 | fd[1] = fd[0] = NULL; | |
497 | index = drive_get_index(IF_FLOPPY, 0, 0); | |
498 | if (index != -1) | |
499 | fd[0] = drives_table[index].bdrv; | |
2d069bab | 500 | |
e4bcb14c TS |
501 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd); |
502 | } | |
503 | ||
504 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
505 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
506 | exit(1); | |
507 | } | |
508 | ||
509 | main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq, | |
2d069bab | 510 | esp_reset); |
f1587550 | 511 | |
e4bcb14c TS |
512 | for (i = 0; i < ESP_MAX_DEVS; i++) { |
513 | index = drive_get_index(IF_SCSI, 0, i); | |
514 | if (index == -1) | |
515 | continue; | |
516 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); | |
f1587550 TS |
517 | } |
518 | ||
5dcb6b91 | 519 | slavio_misc = slavio_misc_init(hwdef->slavio_base, hwdef->power_base, |
d537cf6c | 520 | slavio_irq[hwdef->me_irq]); |
5dcb6b91 | 521 | if (hwdef->cs_base != (target_phys_addr_t)-1) |
803b3c7b | 522 | cs_init(hwdef->cs_base, hwdef->cs_irq, slavio_intctl); |
b3ceef24 | 523 | |
3ebf5aaf BS |
524 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, |
525 | initrd_filename); | |
36cd9210 | 526 | |
36cd9210 | 527 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, |
b3ceef24 | 528 | boot_device, RAM_size, kernel_size, graphic_width, |
7d85892b | 529 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4m"); |
7eb0c8e8 BS |
530 | |
531 | if (hwdef->ecc_base != (target_phys_addr_t)-1) | |
532 | ecc_init(hwdef->ecc_base, hwdef->ecc_version); | |
36cd9210 BS |
533 | } |
534 | ||
ee76f82e BS |
535 | static void sun4c_hw_init(const struct hwdef *hwdef, int RAM_size, |
536 | const char *boot_device, | |
537 | DisplayState *ds, const char *kernel_filename, | |
538 | const char *kernel_cmdline, | |
539 | const char *initrd_filename, const char *cpu_model) | |
540 | { | |
541 | CPUState *env; | |
542 | unsigned int i; | |
543 | void *iommu, *espdma, *ledma, *main_esp, *nvram; | |
544 | qemu_irq *cpu_irqs, *slavio_irq, *espdma_irq, *ledma_irq; | |
545 | qemu_irq *esp_reset, *le_reset; | |
546 | unsigned long prom_offset, kernel_size; | |
547 | int ret; | |
548 | char buf[1024]; | |
549 | BlockDriverState *fd[MAX_FD]; | |
550 | int index; | |
551 | ||
552 | /* init CPU */ | |
553 | if (!cpu_model) | |
554 | cpu_model = hwdef->default_cpu_model; | |
555 | ||
556 | env = cpu_init(cpu_model); | |
557 | if (!env) { | |
558 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); | |
559 | exit(1); | |
560 | } | |
561 | ||
562 | cpu_sparc_set_id(env, 0); | |
563 | ||
564 | qemu_register_reset(main_cpu_reset, env); | |
565 | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); | |
566 | cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); | |
cebb73aa | 567 | env->prom_addr = hwdef->slavio_base; |
ee76f82e BS |
568 | |
569 | /* allocate RAM */ | |
570 | if ((uint64_t)RAM_size > hwdef->max_mem) { | |
571 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", | |
572 | (unsigned int)RAM_size / (1024 * 1024), | |
573 | (unsigned int)hwdef->max_mem / (1024 * 1024)); | |
574 | exit(1); | |
575 | } | |
576 | cpu_register_physical_memory(0, RAM_size, 0); | |
577 | ||
578 | /* load boot prom */ | |
579 | prom_offset = RAM_size + hwdef->vram_size; | |
580 | cpu_register_physical_memory(hwdef->slavio_base, | |
581 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
582 | TARGET_PAGE_MASK, | |
583 | prom_offset | IO_MEM_ROM); | |
584 | ||
585 | if (bios_name == NULL) | |
586 | bios_name = PROM_FILENAME; | |
587 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
588 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
589 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
590 | ret = load_image(buf, phys_ram_base + prom_offset); | |
591 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
592 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
593 | buf); | |
594 | exit(1); | |
595 | } | |
596 | prom_offset += (ret + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK; | |
597 | ||
598 | /* set up devices */ | |
599 | slavio_intctl = sun4c_intctl_init(hwdef->sun4c_intctl_base, | |
600 | &slavio_irq, cpu_irqs); | |
601 | ||
ff403da6 BS |
602 | iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version, |
603 | slavio_irq[hwdef->me_irq]); | |
ee76f82e BS |
604 | |
605 | espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[hwdef->esp_irq], | |
606 | iommu, &espdma_irq, &esp_reset); | |
607 | ||
608 | ledma = sparc32_dma_init(hwdef->dma_base + 16ULL, | |
609 | slavio_irq[hwdef->le_irq], iommu, &ledma_irq, | |
610 | &le_reset); | |
611 | ||
612 | if (graphic_depth != 8 && graphic_depth != 24) { | |
613 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
614 | exit (1); | |
615 | } | |
616 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, | |
617 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); | |
618 | ||
619 | if (nd_table[0].model == NULL | |
620 | || strcmp(nd_table[0].model, "lance") == 0) { | |
621 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); | |
622 | } else if (strcmp(nd_table[0].model, "?") == 0) { | |
623 | fprintf(stderr, "qemu: Supported NICs: lance\n"); | |
624 | exit (1); | |
625 | } else { | |
626 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
627 | exit (1); | |
628 | } | |
629 | ||
630 | nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, | |
4aed2c33 | 631 | hwdef->nvram_size, 2); |
ee76f82e BS |
632 | |
633 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[hwdef->ms_kb_irq], | |
634 | nographic); | |
635 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device | |
636 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
637 | slavio_serial_init(hwdef->serial_base, slavio_irq[hwdef->ser_irq], | |
638 | serial_hds[1], serial_hds[0]); | |
639 | ||
640 | if (hwdef->fd_base != (target_phys_addr_t)-1) { | |
641 | /* there is zero or one floppy drive */ | |
642 | fd[1] = fd[0] = NULL; | |
643 | index = drive_get_index(IF_FLOPPY, 0, 0); | |
644 | if (index != -1) | |
645 | fd[0] = drives_table[index].bdrv; | |
646 | ||
647 | sun4m_fdctrl_init(slavio_irq[hwdef->fd_irq], hwdef->fd_base, fd); | |
648 | } | |
649 | ||
650 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
651 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
652 | exit(1); | |
653 | } | |
654 | ||
655 | main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq, | |
656 | esp_reset); | |
657 | ||
658 | for (i = 0; i < ESP_MAX_DEVS; i++) { | |
659 | index = drive_get_index(IF_SCSI, 0, i); | |
660 | if (index == -1) | |
661 | continue; | |
662 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); | |
663 | } | |
664 | ||
665 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, | |
666 | initrd_filename); | |
667 | ||
668 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
669 | boot_device, RAM_size, kernel_size, graphic_width, | |
670 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4c"); | |
671 | } | |
672 | ||
36cd9210 BS |
673 | static const struct hwdef hwdefs[] = { |
674 | /* SS-5 */ | |
675 | { | |
676 | .iommu_base = 0x10000000, | |
677 | .tcx_base = 0x50000000, | |
678 | .cs_base = 0x6c000000, | |
384ccb5d | 679 | .slavio_base = 0x70000000, |
36cd9210 BS |
680 | .ms_kb_base = 0x71000000, |
681 | .serial_base = 0x71100000, | |
682 | .nvram_base = 0x71200000, | |
683 | .fd_base = 0x71400000, | |
684 | .counter_base = 0x71d00000, | |
685 | .intctl_base = 0x71e00000, | |
4c2485de | 686 | .idreg_base = 0x78000000, |
36cd9210 BS |
687 | .dma_base = 0x78400000, |
688 | .esp_base = 0x78800000, | |
689 | .le_base = 0x78c00000, | |
5dcb6b91 | 690 | .power_base = 0x7a000000, |
7eb0c8e8 | 691 | .ecc_base = -1, |
ee76f82e BS |
692 | .sun4c_intctl_base = -1, |
693 | .sun4c_counter_base = -1, | |
36cd9210 BS |
694 | .vram_size = 0x00100000, |
695 | .nvram_size = 0x2000, | |
696 | .esp_irq = 18, | |
697 | .le_irq = 16, | |
6341fdcb | 698 | .clock_irq = 14, |
36cd9210 BS |
699 | .clock1_irq = 19, |
700 | .ms_kb_irq = 14, | |
701 | .ser_irq = 15, | |
702 | .fd_irq = 22, | |
703 | .me_irq = 30, | |
704 | .cs_irq = 5, | |
705 | .machine_id = 0x80, | |
cf3102ac | 706 | .iommu_version = 0x05000000, |
e0353fe2 | 707 | .intbit_to_level = { |
f930d07e BS |
708 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
709 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 710 | }, |
3ebf5aaf BS |
711 | .max_mem = 0x10000000, |
712 | .default_cpu_model = "Fujitsu MB86904", | |
e0353fe2 BS |
713 | }, |
714 | /* SS-10 */ | |
e0353fe2 | 715 | { |
5dcb6b91 BS |
716 | .iommu_base = 0xfe0000000ULL, |
717 | .tcx_base = 0xe20000000ULL, | |
803b3c7b | 718 | .cs_base = -1, |
5dcb6b91 BS |
719 | .slavio_base = 0xff0000000ULL, |
720 | .ms_kb_base = 0xff1000000ULL, | |
721 | .serial_base = 0xff1100000ULL, | |
722 | .nvram_base = 0xff1200000ULL, | |
723 | .fd_base = 0xff1700000ULL, | |
724 | .counter_base = 0xff1300000ULL, | |
725 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 726 | .idreg_base = 0xef0000000ULL, |
5dcb6b91 BS |
727 | .dma_base = 0xef0400000ULL, |
728 | .esp_base = 0xef0800000ULL, | |
729 | .le_base = 0xef0c00000ULL, | |
730 | .power_base = 0xefa000000ULL, | |
7eb0c8e8 BS |
731 | .ecc_base = 0xf00000000ULL, |
732 | .ecc_version = 0x10000000, // version 0, implementation 1 | |
ee76f82e BS |
733 | .sun4c_intctl_base = -1, |
734 | .sun4c_counter_base = -1, | |
e0353fe2 BS |
735 | .vram_size = 0x00100000, |
736 | .nvram_size = 0x2000, | |
737 | .esp_irq = 18, | |
738 | .le_irq = 16, | |
6341fdcb | 739 | .clock_irq = 14, |
e0353fe2 BS |
740 | .clock1_irq = 19, |
741 | .ms_kb_irq = 14, | |
742 | .ser_irq = 15, | |
743 | .fd_irq = 22, | |
744 | .me_irq = 30, | |
803b3c7b BS |
745 | .cs_irq = -1, |
746 | .machine_id = 0x72, | |
7fbfb139 | 747 | .iommu_version = 0x03000000, |
e0353fe2 | 748 | .intbit_to_level = { |
f930d07e BS |
749 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, |
750 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
e0353fe2 | 751 | }, |
3ebf5aaf BS |
752 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
753 | .default_cpu_model = "TI SuperSparc II", | |
36cd9210 | 754 | }, |
6a3b9cc9 BS |
755 | /* SS-600MP */ |
756 | { | |
757 | .iommu_base = 0xfe0000000ULL, | |
758 | .tcx_base = 0xe20000000ULL, | |
759 | .cs_base = -1, | |
760 | .slavio_base = 0xff0000000ULL, | |
761 | .ms_kb_base = 0xff1000000ULL, | |
762 | .serial_base = 0xff1100000ULL, | |
763 | .nvram_base = 0xff1200000ULL, | |
764 | .fd_base = -1, | |
765 | .counter_base = 0xff1300000ULL, | |
766 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 767 | .idreg_base = -1, |
6a3b9cc9 BS |
768 | .dma_base = 0xef0081000ULL, |
769 | .esp_base = 0xef0080000ULL, | |
770 | .le_base = 0xef0060000ULL, | |
771 | .power_base = 0xefa000000ULL, | |
7eb0c8e8 BS |
772 | .ecc_base = 0xf00000000ULL, |
773 | .ecc_version = 0x00000000, // version 0, implementation 0 | |
ee76f82e BS |
774 | .sun4c_intctl_base = -1, |
775 | .sun4c_counter_base = -1, | |
6a3b9cc9 BS |
776 | .vram_size = 0x00100000, |
777 | .nvram_size = 0x2000, | |
778 | .esp_irq = 18, | |
779 | .le_irq = 16, | |
6341fdcb | 780 | .clock_irq = 14, |
6a3b9cc9 BS |
781 | .clock1_irq = 19, |
782 | .ms_kb_irq = 14, | |
783 | .ser_irq = 15, | |
784 | .fd_irq = 22, | |
785 | .me_irq = 30, | |
786 | .cs_irq = -1, | |
787 | .machine_id = 0x71, | |
7fbfb139 | 788 | .iommu_version = 0x01000000, |
6a3b9cc9 BS |
789 | .intbit_to_level = { |
790 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
791 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
792 | }, | |
3ebf5aaf BS |
793 | .max_mem = 0xffffffff, // XXX actually first 62GB ok |
794 | .default_cpu_model = "TI SuperSparc II", | |
6a3b9cc9 | 795 | }, |
ae40972f BS |
796 | /* SS-20 */ |
797 | { | |
798 | .iommu_base = 0xfe0000000ULL, | |
799 | .tcx_base = 0xe20000000ULL, | |
800 | .cs_base = -1, | |
801 | .slavio_base = 0xff0000000ULL, | |
802 | .ms_kb_base = 0xff1000000ULL, | |
803 | .serial_base = 0xff1100000ULL, | |
804 | .nvram_base = 0xff1200000ULL, | |
805 | .fd_base = 0xff1700000ULL, | |
806 | .counter_base = 0xff1300000ULL, | |
807 | .intctl_base = 0xff1400000ULL, | |
4c2485de | 808 | .idreg_base = 0xef0000000ULL, |
ae40972f BS |
809 | .dma_base = 0xef0400000ULL, |
810 | .esp_base = 0xef0800000ULL, | |
811 | .le_base = 0xef0c00000ULL, | |
812 | .power_base = 0xefa000000ULL, | |
813 | .ecc_base = 0xf00000000ULL, | |
814 | .ecc_version = 0x20000000, // version 0, implementation 2 | |
ee76f82e BS |
815 | .sun4c_intctl_base = -1, |
816 | .sun4c_counter_base = -1, | |
ae40972f BS |
817 | .vram_size = 0x00100000, |
818 | .nvram_size = 0x2000, | |
819 | .esp_irq = 18, | |
820 | .le_irq = 16, | |
6341fdcb | 821 | .clock_irq = 14, |
ae40972f BS |
822 | .clock1_irq = 19, |
823 | .ms_kb_irq = 14, | |
824 | .ser_irq = 15, | |
825 | .fd_irq = 22, | |
826 | .me_irq = 30, | |
827 | .cs_irq = -1, | |
828 | .machine_id = 0x72, | |
829 | .iommu_version = 0x13000000, | |
830 | .intbit_to_level = { | |
831 | 2, 3, 5, 7, 9, 11, 0, 14, 3, 5, 7, 9, 11, 13, 12, 12, | |
832 | 6, 0, 4, 10, 8, 0, 11, 0, 0, 0, 0, 0, 15, 0, 15, 0, | |
833 | }, | |
834 | .max_mem = 0xffffffff, // XXX actually first 62GB ok | |
835 | .default_cpu_model = "TI SuperSparc II", | |
836 | }, | |
ee76f82e BS |
837 | /* SS-2 */ |
838 | { | |
839 | .iommu_base = 0xf8000000, | |
840 | .tcx_base = 0xfe000000, | |
841 | .cs_base = -1, | |
842 | .slavio_base = 0xf6000000, | |
843 | .ms_kb_base = 0xf0000000, | |
844 | .serial_base = 0xf1000000, | |
845 | .nvram_base = 0xf2000000, | |
846 | .fd_base = 0xf7200000, | |
847 | .counter_base = -1, | |
848 | .intctl_base = -1, | |
849 | .dma_base = 0xf8400000, | |
850 | .esp_base = 0xf8800000, | |
851 | .le_base = 0xf8c00000, | |
852 | .power_base = -1, | |
853 | .sun4c_intctl_base = 0xf5000000, | |
854 | .sun4c_counter_base = 0xf3000000, | |
855 | .vram_size = 0x00100000, | |
4aed2c33 | 856 | .nvram_size = 0x800, |
ee76f82e BS |
857 | .esp_irq = 2, |
858 | .le_irq = 3, | |
859 | .clock_irq = 5, | |
860 | .clock1_irq = 7, | |
861 | .ms_kb_irq = 1, | |
862 | .ser_irq = 1, | |
863 | .fd_irq = 1, | |
864 | .me_irq = 1, | |
865 | .cs_irq = -1, | |
866 | .machine_id = 0x55, | |
867 | .max_mem = 0x10000000, | |
868 | .default_cpu_model = "Cypress CY7C601", | |
869 | }, | |
36cd9210 BS |
870 | }; |
871 | ||
36cd9210 | 872 | /* SPARCstation 5 hardware initialisation */ |
b881c2c6 BS |
873 | static void ss5_init(int RAM_size, int vga_ram_size, |
874 | const char *boot_device, DisplayState *ds, | |
875 | const char *kernel_filename, const char *kernel_cmdline, | |
876 | const char *initrd_filename, const char *cpu_model) | |
36cd9210 | 877 | { |
3ebf5aaf BS |
878 | sun4m_hw_init(&hwdefs[0], RAM_size, boot_device, ds, kernel_filename, |
879 | kernel_cmdline, initrd_filename, cpu_model); | |
420557e8 | 880 | } |
c0e564d5 | 881 | |
e0353fe2 | 882 | /* SPARCstation 10 hardware initialisation */ |
b881c2c6 BS |
883 | static void ss10_init(int RAM_size, int vga_ram_size, |
884 | const char *boot_device, DisplayState *ds, | |
885 | const char *kernel_filename, const char *kernel_cmdline, | |
886 | const char *initrd_filename, const char *cpu_model) | |
e0353fe2 | 887 | { |
3ebf5aaf BS |
888 | sun4m_hw_init(&hwdefs[1], RAM_size, boot_device, ds, kernel_filename, |
889 | kernel_cmdline, initrd_filename, cpu_model); | |
e0353fe2 BS |
890 | } |
891 | ||
6a3b9cc9 | 892 | /* SPARCserver 600MP hardware initialisation */ |
b881c2c6 BS |
893 | static void ss600mp_init(int RAM_size, int vga_ram_size, |
894 | const char *boot_device, DisplayState *ds, | |
6a3b9cc9 BS |
895 | const char *kernel_filename, const char *kernel_cmdline, |
896 | const char *initrd_filename, const char *cpu_model) | |
897 | { | |
3ebf5aaf BS |
898 | sun4m_hw_init(&hwdefs[2], RAM_size, boot_device, ds, kernel_filename, |
899 | kernel_cmdline, initrd_filename, cpu_model); | |
6a3b9cc9 BS |
900 | } |
901 | ||
ae40972f BS |
902 | /* SPARCstation 20 hardware initialisation */ |
903 | static void ss20_init(int RAM_size, int vga_ram_size, | |
904 | const char *boot_device, DisplayState *ds, | |
905 | const char *kernel_filename, const char *kernel_cmdline, | |
906 | const char *initrd_filename, const char *cpu_model) | |
907 | { | |
908 | sun4m_hw_init(&hwdefs[3], RAM_size, boot_device, ds, kernel_filename, | |
909 | kernel_cmdline, initrd_filename, cpu_model); | |
910 | } | |
911 | ||
ee76f82e BS |
912 | /* SPARCstation 2 hardware initialisation */ |
913 | static void ss2_init(int RAM_size, int vga_ram_size, | |
914 | const char *boot_device, DisplayState *ds, | |
915 | const char *kernel_filename, const char *kernel_cmdline, | |
916 | const char *initrd_filename, const char *cpu_model) | |
917 | { | |
918 | sun4c_hw_init(&hwdefs[4], RAM_size, boot_device, ds, kernel_filename, | |
919 | kernel_cmdline, initrd_filename, cpu_model); | |
920 | } | |
921 | ||
36cd9210 BS |
922 | QEMUMachine ss5_machine = { |
923 | "SS-5", | |
924 | "Sun4m platform, SPARCstation 5", | |
925 | ss5_init, | |
c0e564d5 | 926 | }; |
e0353fe2 BS |
927 | |
928 | QEMUMachine ss10_machine = { | |
929 | "SS-10", | |
930 | "Sun4m platform, SPARCstation 10", | |
931 | ss10_init, | |
932 | }; | |
6a3b9cc9 BS |
933 | |
934 | QEMUMachine ss600mp_machine = { | |
935 | "SS-600MP", | |
936 | "Sun4m platform, SPARCserver 600MP", | |
937 | ss600mp_init, | |
938 | }; | |
ae40972f BS |
939 | |
940 | QEMUMachine ss20_machine = { | |
941 | "SS-20", | |
942 | "Sun4m platform, SPARCstation 20", | |
943 | ss20_init, | |
944 | }; | |
945 | ||
ee76f82e BS |
946 | QEMUMachine ss2_machine = { |
947 | "SS-2", | |
948 | "Sun4c platform, SPARCstation 2", | |
949 | ss2_init, | |
950 | }; | |
7d85892b BS |
951 | |
952 | static const struct sun4d_hwdef sun4d_hwdefs[] = { | |
953 | /* SS-1000 */ | |
954 | { | |
955 | .iounit_bases = { | |
956 | 0xfe0200000ULL, | |
957 | 0xfe1200000ULL, | |
958 | 0xfe2200000ULL, | |
959 | 0xfe3200000ULL, | |
960 | -1, | |
961 | }, | |
962 | .tcx_base = 0x820000000ULL, | |
963 | .slavio_base = 0xf00000000ULL, | |
964 | .ms_kb_base = 0xf00240000ULL, | |
965 | .serial_base = 0xf00200000ULL, | |
966 | .nvram_base = 0xf00280000ULL, | |
967 | .counter_base = 0xf00300000ULL, | |
968 | .espdma_base = 0x800081000ULL, | |
969 | .esp_base = 0x800080000ULL, | |
970 | .ledma_base = 0x800040000ULL, | |
971 | .le_base = 0x800060000ULL, | |
972 | .sbi_base = 0xf02800000ULL, | |
973 | .vram_size = 0x00100000, | |
974 | .nvram_size = 0x2000, | |
975 | .esp_irq = 3, | |
976 | .le_irq = 4, | |
977 | .clock_irq = 14, | |
978 | .clock1_irq = 10, | |
979 | .ms_kb_irq = 12, | |
980 | .ser_irq = 12, | |
981 | .machine_id = 0x80, | |
982 | .iounit_version = 0x03000000, | |
983 | .max_mem = 0xffffffff, // XXX actually first 62GB ok | |
984 | .default_cpu_model = "TI SuperSparc II", | |
985 | }, | |
986 | /* SS-2000 */ | |
987 | { | |
988 | .iounit_bases = { | |
989 | 0xfe0200000ULL, | |
990 | 0xfe1200000ULL, | |
991 | 0xfe2200000ULL, | |
992 | 0xfe3200000ULL, | |
993 | 0xfe4200000ULL, | |
994 | }, | |
995 | .tcx_base = 0x820000000ULL, | |
996 | .slavio_base = 0xf00000000ULL, | |
997 | .ms_kb_base = 0xf00240000ULL, | |
998 | .serial_base = 0xf00200000ULL, | |
999 | .nvram_base = 0xf00280000ULL, | |
1000 | .counter_base = 0xf00300000ULL, | |
1001 | .espdma_base = 0x800081000ULL, | |
1002 | .esp_base = 0x800080000ULL, | |
1003 | .ledma_base = 0x800040000ULL, | |
1004 | .le_base = 0x800060000ULL, | |
1005 | .sbi_base = 0xf02800000ULL, | |
1006 | .vram_size = 0x00100000, | |
1007 | .nvram_size = 0x2000, | |
1008 | .esp_irq = 3, | |
1009 | .le_irq = 4, | |
1010 | .clock_irq = 14, | |
1011 | .clock1_irq = 10, | |
1012 | .ms_kb_irq = 12, | |
1013 | .ser_irq = 12, | |
1014 | .machine_id = 0x80, | |
1015 | .iounit_version = 0x03000000, | |
1016 | .max_mem = 0xffffffff, // XXX actually first 62GB ok | |
1017 | .default_cpu_model = "TI SuperSparc II", | |
1018 | }, | |
1019 | }; | |
1020 | ||
1021 | static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, int RAM_size, | |
1022 | const char *boot_device, | |
1023 | DisplayState *ds, const char *kernel_filename, | |
1024 | const char *kernel_cmdline, | |
1025 | const char *initrd_filename, const char *cpu_model) | |
1026 | { | |
1027 | CPUState *env, *envs[MAX_CPUS]; | |
1028 | unsigned int i; | |
1029 | void *iounits[MAX_IOUNITS], *espdma, *ledma, *main_esp, *nvram, *sbi; | |
1030 | qemu_irq *cpu_irqs[MAX_CPUS], *sbi_irq, *sbi_cpu_irq, | |
1031 | *espdma_irq, *ledma_irq; | |
1032 | qemu_irq *esp_reset, *le_reset; | |
1033 | unsigned long prom_offset, kernel_size; | |
1034 | int ret; | |
1035 | char buf[1024]; | |
1036 | int index; | |
1037 | ||
1038 | /* init CPUs */ | |
1039 | if (!cpu_model) | |
1040 | cpu_model = hwdef->default_cpu_model; | |
1041 | ||
1042 | for (i = 0; i < smp_cpus; i++) { | |
1043 | env = cpu_init(cpu_model); | |
1044 | if (!env) { | |
1045 | fprintf(stderr, "Unable to find Sparc CPU definition\n"); | |
1046 | exit(1); | |
1047 | } | |
1048 | cpu_sparc_set_id(env, i); | |
1049 | envs[i] = env; | |
1050 | if (i == 0) { | |
1051 | qemu_register_reset(main_cpu_reset, env); | |
1052 | } else { | |
1053 | qemu_register_reset(secondary_cpu_reset, env); | |
1054 | env->halted = 1; | |
1055 | } | |
1056 | register_savevm("cpu", i, 3, cpu_save, cpu_load, env); | |
1057 | cpu_irqs[i] = qemu_allocate_irqs(cpu_set_irq, envs[i], MAX_PILS); | |
1058 | env->prom_addr = hwdef->slavio_base; | |
1059 | } | |
1060 | ||
1061 | for (i = smp_cpus; i < MAX_CPUS; i++) | |
1062 | cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS); | |
1063 | ||
1064 | /* allocate RAM */ | |
1065 | if ((uint64_t)RAM_size > hwdef->max_mem) { | |
1066 | fprintf(stderr, "qemu: Too much memory for this machine: %d, maximum %d\n", | |
1067 | (unsigned int)RAM_size / (1024 * 1024), | |
1068 | (unsigned int)(hwdef->max_mem / (1024 * 1024))); | |
1069 | exit(1); | |
1070 | } | |
1071 | cpu_register_physical_memory(0, RAM_size, 0); | |
1072 | ||
1073 | /* load boot prom */ | |
1074 | prom_offset = RAM_size + hwdef->vram_size; | |
1075 | cpu_register_physical_memory(hwdef->slavio_base, | |
1076 | (PROM_SIZE_MAX + TARGET_PAGE_SIZE - 1) & | |
1077 | TARGET_PAGE_MASK, | |
1078 | prom_offset | IO_MEM_ROM); | |
1079 | ||
1080 | if (bios_name == NULL) | |
1081 | bios_name = PROM_FILENAME; | |
1082 | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name); | |
1083 | ret = load_elf(buf, hwdef->slavio_base - PROM_VADDR, NULL, NULL, NULL); | |
1084 | if (ret < 0 || ret > PROM_SIZE_MAX) | |
1085 | ret = load_image(buf, phys_ram_base + prom_offset); | |
1086 | if (ret < 0 || ret > PROM_SIZE_MAX) { | |
1087 | fprintf(stderr, "qemu: could not load prom '%s'\n", | |
1088 | buf); | |
1089 | exit(1); | |
1090 | } | |
1091 | ||
1092 | /* set up devices */ | |
1093 | sbi = sbi_init(hwdef->sbi_base, &sbi_irq, &sbi_cpu_irq, cpu_irqs); | |
1094 | ||
1095 | for (i = 0; i < MAX_IOUNITS; i++) | |
1096 | if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1) | |
ff403da6 BS |
1097 | iounits[i] = iommu_init(hwdef->iounit_bases[i], |
1098 | hwdef->iounit_version, | |
1099 | sbi_irq[hwdef->me_irq]); | |
7d85892b BS |
1100 | |
1101 | espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[hwdef->esp_irq], | |
1102 | iounits[0], &espdma_irq, &esp_reset); | |
1103 | ||
1104 | ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[hwdef->le_irq], | |
1105 | iounits[0], &ledma_irq, &le_reset); | |
1106 | ||
1107 | if (graphic_depth != 8 && graphic_depth != 24) { | |
1108 | fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth); | |
1109 | exit (1); | |
1110 | } | |
1111 | tcx_init(ds, hwdef->tcx_base, phys_ram_base + RAM_size, RAM_size, | |
1112 | hwdef->vram_size, graphic_width, graphic_height, graphic_depth); | |
1113 | ||
1114 | if (nd_table[0].model == NULL | |
1115 | || strcmp(nd_table[0].model, "lance") == 0) { | |
1116 | lance_init(&nd_table[0], hwdef->le_base, ledma, *ledma_irq, le_reset); | |
1117 | } else if (strcmp(nd_table[0].model, "?") == 0) { | |
1118 | fprintf(stderr, "qemu: Supported NICs: lance\n"); | |
1119 | exit (1); | |
1120 | } else { | |
1121 | fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd_table[0].model); | |
1122 | exit (1); | |
1123 | } | |
1124 | ||
1125 | nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, | |
1126 | hwdef->nvram_size, 8); | |
1127 | ||
1128 | slavio_timer_init_all(hwdef->counter_base, sbi_irq[hwdef->clock1_irq], | |
1129 | sbi_cpu_irq, smp_cpus); | |
1130 | ||
1131 | slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[hwdef->ms_kb_irq], | |
1132 | nographic); | |
1133 | // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device | |
1134 | // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device | |
1135 | slavio_serial_init(hwdef->serial_base, sbi_irq[hwdef->ser_irq], | |
1136 | serial_hds[1], serial_hds[0]); | |
1137 | ||
1138 | if (drive_get_max_bus(IF_SCSI) > 0) { | |
1139 | fprintf(stderr, "qemu: too many SCSI bus\n"); | |
1140 | exit(1); | |
1141 | } | |
1142 | ||
1143 | main_esp = esp_init(hwdef->esp_base, espdma, *espdma_irq, | |
1144 | esp_reset); | |
1145 | ||
1146 | for (i = 0; i < ESP_MAX_DEVS; i++) { | |
1147 | index = drive_get_index(IF_SCSI, 0, i); | |
1148 | if (index == -1) | |
1149 | continue; | |
1150 | esp_scsi_attach(main_esp, drives_table[index].bdrv, i); | |
1151 | } | |
1152 | ||
1153 | kernel_size = sun4m_load_kernel(kernel_filename, kernel_cmdline, | |
1154 | initrd_filename); | |
1155 | ||
1156 | nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, | |
1157 | boot_device, RAM_size, kernel_size, graphic_width, | |
1158 | graphic_height, graphic_depth, hwdef->machine_id, "Sun4d"); | |
1159 | } | |
1160 | ||
1161 | /* SPARCserver 1000 hardware initialisation */ | |
1162 | static void ss1000_init(int RAM_size, int vga_ram_size, | |
1163 | const char *boot_device, DisplayState *ds, | |
1164 | const char *kernel_filename, const char *kernel_cmdline, | |
1165 | const char *initrd_filename, const char *cpu_model) | |
1166 | { | |
1167 | sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, ds, kernel_filename, | |
1168 | kernel_cmdline, initrd_filename, cpu_model); | |
1169 | } | |
1170 | ||
1171 | /* SPARCcenter 2000 hardware initialisation */ | |
1172 | static void ss2000_init(int RAM_size, int vga_ram_size, | |
1173 | const char *boot_device, DisplayState *ds, | |
1174 | const char *kernel_filename, const char *kernel_cmdline, | |
1175 | const char *initrd_filename, const char *cpu_model) | |
1176 | { | |
1177 | sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, ds, kernel_filename, | |
1178 | kernel_cmdline, initrd_filename, cpu_model); | |
1179 | } | |
1180 | ||
1181 | QEMUMachine ss1000_machine = { | |
1182 | "SS-1000", | |
1183 | "Sun4d platform, SPARCserver 1000", | |
1184 | ss1000_init, | |
1185 | }; | |
1186 | ||
1187 | QEMUMachine ss2000_machine = { | |
1188 | "SS-2000", | |
1189 | "Sun4d platform, SPARCcenter 2000", | |
1190 | ss2000_init, | |
1191 | }; |