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420557e8 1/*
ee76f82e 2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
5fafdf24 3 *
b81b3b10 4 * Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24 5 *
420557e8
FB
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
9d07d757 24#include "sysbus.h"
87ecb68b
PB
25#include "qemu-timer.h"
26#include "sun4m.h"
27#include "nvram.h"
28#include "sparc32_dma.h"
29#include "fdc.h"
30#include "sysemu.h"
31#include "net.h"
32#include "boards.h"
d2c63fc1 33#include "firmware_abi.h"
1cd3af54 34#include "esp.h"
22548760
BS
35#include "pc.h"
36#include "isa.h"
3cce6243 37#include "fw_cfg.h"
b4ed08e0 38#include "escc.h"
676d9b9b 39#include "empty_slot.h"
4b48bf05 40#include "qdev-addr.h"
ca20cf32
BS
41#include "loader.h"
42#include "elf.h"
2446333c 43#include "blockdev.h"
97bf4851 44#include "trace.h"
420557e8 45
36cd9210
BS
46/*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
77f193da
BS
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
36cd9210
BS
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
7d85892b
BS
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
ee76f82e
BS
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
36cd9210
BS
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
420557e8 74#define KERNEL_LOAD_ADDR 0x00004000
b6f479d3 75#define CMDLINE_ADDR 0x007ff000
713c45fa 76#define INITRD_LOAD_ADDR 0x00800000
a7227727 77#define PROM_SIZE_MAX (1024 * 1024)
40ce0a9a 78#define PROM_VADDR 0xffd00000
f930d07e 79#define PROM_FILENAME "openbios-sparc32"
3cce6243 80#define CFG_ADDR 0xd00000510ULL
fbfcf955 81#define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
b8174937 82
ba3c64fb 83#define MAX_CPUS 16
b3a23197 84#define MAX_PILS 16
9a62fb24 85#define MAX_VSIMMS 4
420557e8 86
b4ed08e0
BS
87#define ESCC_CLOCK 4915200
88
8137cde8 89struct sun4m_hwdef {
3386376c 90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
c227f099
AL
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
c5de386a 93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
c227f099 94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
9a62fb24
BB
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
c227f099 99 target_phys_addr_t ecc_base;
3ebf5aaf
BS
100 uint64_t max_mem;
101 const char * const default_cpu_model;
61999750
BS
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
36cd9210
BS
106};
107
7d85892b
BS
108#define MAX_IOUNITS 5
109
110struct sun4d_hwdef {
c227f099
AL
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
7d85892b
BS
118 uint64_t max_mem;
119 const char * const default_cpu_model;
61999750
BS
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
7d85892b
BS
123};
124
8137cde8 125struct sun4c_hwdef {
c227f099
AL
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
8137cde8
BS
131 uint64_t max_mem;
132 const char * const default_cpu_model;
61999750
BS
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
8137cde8
BS
136};
137
6f7e9aec
FB
138int DMA_get_channel_mode (int nchan)
139{
140 return 0;
141}
142int DMA_read_memory (int nchan, void *buf, int pos, int size)
143{
144 return 0;
145}
146int DMA_write_memory (int nchan, void *buf, int pos, int size)
147{
148 return 0;
149}
150void DMA_hold_DREQ (int nchan) {}
151void DMA_release_DREQ (int nchan) {}
152void DMA_schedule(int nchan) {}
4556bd8b
BS
153
154void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155{
156}
157
6f7e9aec
FB
158void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161{
162}
163
513f789f 164static int fw_cfg_boot_set(void *opaque, const char *boot_device)
81864572 165{
513f789f 166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
81864572
BS
167 return 0;
168}
169
43a34704
BS
170static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
f930d07e 173 int width, int height, int depth,
905fdcb5 174 int nvram_machine_id, const char *arch)
e80cfcfc 175{
d2c63fc1 176 unsigned int i;
66508601 177 uint32_t start, end;
d2c63fc1 178 uint8_t image[0x1ff0];
d2c63fc1
BS
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
e80cfcfc 182
513f789f 183 start = 0;
b6f479d3 184
66508601
BS
185 // OpenBIOS nvram variables
186 // Variable partition
d2c63fc1
BS
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
363a37d5 189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
66508601 190
d2c63fc1 191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
66508601 192 for (i = 0; i < nb_prom_envs; i++)
d2c63fc1
BS
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
66508601 197
66508601 198 end = start + ((end - start + 15) & ~15);
d2c63fc1 199 OpenBIOS_finish_partition(part_header, end - start);
66508601
BS
200
201 // free partition
202 start = end;
d2c63fc1
BS
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
363a37d5 205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
66508601
BS
206
207 end = 0x1fd0;
d2c63fc1
BS
208 OpenBIOS_finish_partition(part_header, end - start);
209
905fdcb5
BS
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
d2c63fc1
BS
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
e80cfcfc
FB
215}
216
d453c2c3 217static DeviceState *slavio_intctl;
e80cfcfc 218
661f1929 219void sun4m_pic_info(Monitor *mon)
e80cfcfc 220{
7d85892b 221 if (slavio_intctl)
376253ec 222 slavio_pic_info(mon, slavio_intctl);
e80cfcfc
FB
223}
224
661f1929 225void sun4m_irq_info(Monitor *mon)
e80cfcfc 226{
7d85892b 227 if (slavio_intctl)
376253ec 228 slavio_irq_info(mon, slavio_intctl);
e80cfcfc
FB
229}
230
327ac2e7
BS
231void cpu_check_irqs(CPUState *env)
232{
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
f32d7ec5 242 if (old_interrupt != env->interrupt_index) {
97bf4851 243 trace_sun4m_cpu_interrupt(i);
327ac2e7 244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
f32d7ec5 245 }
327ac2e7
BS
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
97bf4851 250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
327ac2e7
BS
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254}
255
94ad5b00
PB
256static void cpu_kick_irq(CPUState *env)
257{
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261}
262
b3a23197
BS
263static void cpu_set_irq(void *opaque, int irq, int level)
264{
265 CPUState *env = opaque;
266
267 if (level) {
97bf4851 268 trace_sun4m_cpu_set_irq_raise(irq);
327ac2e7 269 env->pil_in |= 1 << irq;
94ad5b00 270 cpu_kick_irq(env);
b3a23197 271 } else {
97bf4851 272 trace_sun4m_cpu_set_irq_lower(irq);
327ac2e7
BS
273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
b3a23197
BS
275 }
276}
277
278static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279{
280}
281
c68ea704
FB
282static void main_cpu_reset(void *opaque)
283{
284 CPUState *env = opaque;
3d29fbef
BS
285
286 cpu_reset(env);
287 env->halted = 0;
288}
289
290static void secondary_cpu_reset(void *opaque)
291{
292 CPUState *env = opaque;
293
c68ea704 294 cpu_reset(env);
3d29fbef 295 env->halted = 1;
c68ea704
FB
296}
297
6d0c293d
BS
298static void cpu_halt_signal(void *opaque, int irq, int level)
299{
300 if (level && cpu_single_env)
301 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
302}
303
409dbce5
AJ
304static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
305{
306 return addr - 0xf0000000ULL;
307}
308
3ebf5aaf 309static unsigned long sun4m_load_kernel(const char *kernel_filename,
293f78bc 310 const char *initrd_filename,
c227f099 311 ram_addr_t RAM_size)
3ebf5aaf
BS
312{
313 int linux_boot;
314 unsigned int i;
315 long initrd_size, kernel_size;
3c178e72 316 uint8_t *ptr;
3ebf5aaf
BS
317
318 linux_boot = (kernel_filename != NULL);
319
320 kernel_size = 0;
321 if (linux_boot) {
ca20cf32
BS
322 int bswap_needed;
323
324#ifdef BSWAP_NEEDED
325 bswap_needed = 1;
326#else
327 bswap_needed = 0;
328#endif
409dbce5
AJ
329 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
330 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
3ebf5aaf 331 if (kernel_size < 0)
293f78bc 332 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
ca20cf32
BS
333 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
334 TARGET_PAGE_SIZE);
3ebf5aaf 335 if (kernel_size < 0)
293f78bc
BS
336 kernel_size = load_image_targphys(kernel_filename,
337 KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR);
3ebf5aaf
BS
339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
293f78bc
BS
348 initrd_size = load_image_targphys(initrd_filename,
349 INITRD_LOAD_ADDR,
350 RAM_size - INITRD_LOAD_ADDR);
3ebf5aaf
BS
351 if (initrd_size < 0) {
352 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353 initrd_filename);
354 exit(1);
355 }
356 }
357 if (initrd_size > 0) {
358 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
3c178e72
GH
359 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
360 if (ldl_p(ptr) == 0x48647253) { // HdrS
361 stl_p(ptr + 16, INITRD_LOAD_ADDR);
362 stl_p(ptr + 20, initrd_size);
3ebf5aaf
BS
363 break;
364 }
365 }
366 }
367 }
368 return kernel_size;
369}
370
c227f099 371static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
4b48bf05
BS
372{
373 DeviceState *dev;
374 SysBusDevice *s;
375
376 dev = qdev_create(NULL, "iommu");
377 qdev_prop_set_uint32(dev, "version", version);
e23a1b33 378 qdev_init_nofail(dev);
4b48bf05
BS
379 s = sysbus_from_qdev(dev);
380 sysbus_connect_irq(s, 0, irq);
381 sysbus_mmio_map(s, 0, addr);
382
383 return s;
384}
385
c227f099 386static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
86d1c388 387 void *iommu, qemu_irq *dev_irq, int is_ledma)
74ff8d90
BS
388{
389 DeviceState *dev;
390 SysBusDevice *s;
391
392 dev = qdev_create(NULL, "sparc32_dma");
393 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
86d1c388 394 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
e23a1b33 395 qdev_init_nofail(dev);
74ff8d90
BS
396 s = sysbus_from_qdev(dev);
397 sysbus_connect_irq(s, 0, parent_irq);
398 *dev_irq = qdev_get_gpio_in(dev, 0);
399 sysbus_mmio_map(s, 0, daddr);
400
401 return s;
402}
403
c227f099 404static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
74ff8d90 405 void *dma_opaque, qemu_irq irq)
9d07d757
PB
406{
407 DeviceState *dev;
408 SysBusDevice *s;
74ff8d90 409 qemu_irq reset;
9d07d757
PB
410
411 qemu_check_nic_model(&nd_table[0], "lance");
412
413 dev = qdev_create(NULL, "lance");
76224833 414 qdev_set_nic_properties(dev, nd);
daa65491 415 qdev_prop_set_ptr(dev, "dma", dma_opaque);
e23a1b33 416 qdev_init_nofail(dev);
9d07d757
PB
417 s = sysbus_from_qdev(dev);
418 sysbus_mmio_map(s, 0, leaddr);
419 sysbus_connect_irq(s, 0, irq);
74ff8d90
BS
420 reset = qdev_get_gpio_in(dev, 0);
421 qdev_connect_gpio_out(dma_opaque, 0, reset);
9d07d757
PB
422}
423
c227f099
AL
424static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425 target_phys_addr_t addrg,
462eda24 426 qemu_irq **parent_irq)
4b48bf05
BS
427{
428 DeviceState *dev;
429 SysBusDevice *s;
430 unsigned int i, j;
431
432 dev = qdev_create(NULL, "slavio_intctl");
e23a1b33 433 qdev_init_nofail(dev);
4b48bf05
BS
434
435 s = sysbus_from_qdev(dev);
436
437 for (i = 0; i < MAX_CPUS; i++) {
438 for (j = 0; j < MAX_PILS; j++) {
439 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440 }
441 }
442 sysbus_mmio_map(s, 0, addrg);
443 for (i = 0; i < MAX_CPUS; i++) {
444 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445 }
446
447 return dev;
448}
449
450#define SYS_TIMER_OFFSET 0x10000ULL
451#define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452
c227f099 453static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
4b48bf05
BS
454 qemu_irq *cpu_irqs, unsigned int num_cpus)
455{
456 DeviceState *dev;
457 SysBusDevice *s;
458 unsigned int i;
459
460 dev = qdev_create(NULL, "slavio_timer");
461 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
e23a1b33 462 qdev_init_nofail(dev);
4b48bf05
BS
463 s = sysbus_from_qdev(dev);
464 sysbus_connect_irq(s, 0, master_irq);
465 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466
467 for (i = 0; i < MAX_CPUS; i++) {
c227f099 468 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
4b48bf05
BS
469 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470 }
471}
472
473#define MISC_LEDS 0x01600000
474#define MISC_CFG 0x01800000
475#define MISC_DIAG 0x01a00000
476#define MISC_MDM 0x01b00000
477#define MISC_SYS 0x01f00000
478
c227f099
AL
479static void slavio_misc_init(target_phys_addr_t base,
480 target_phys_addr_t aux1_base,
481 target_phys_addr_t aux2_base, qemu_irq irq,
b2b6f6ec 482 qemu_irq fdc_tc)
4b48bf05
BS
483{
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "slavio_misc");
e23a1b33 488 qdev_init_nofail(dev);
4b48bf05
BS
489 s = sysbus_from_qdev(dev);
490 if (base) {
491 /* 8 bit registers */
492 /* Slavio control */
493 sysbus_mmio_map(s, 0, base + MISC_CFG);
494 /* Diagnostics */
495 sysbus_mmio_map(s, 1, base + MISC_DIAG);
496 /* Modem control */
497 sysbus_mmio_map(s, 2, base + MISC_MDM);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s, 3, base + MISC_LEDS);
501 /* 32 bit registers */
502 /* System control */
503 sysbus_mmio_map(s, 4, base + MISC_SYS);
504 }
505 if (aux1_base) {
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s, 5, aux1_base);
508 }
509 if (aux2_base) {
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s, 6, aux2_base);
512 }
513 sysbus_connect_irq(s, 0, irq);
514 sysbus_connect_irq(s, 1, fdc_tc);
d9c32310 515 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
4b48bf05
BS
516}
517
c227f099 518static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
4b48bf05
BS
519{
520 DeviceState *dev;
521 SysBusDevice *s;
522
523 dev = qdev_create(NULL, "eccmemctl");
524 qdev_prop_set_uint32(dev, "version", version);
e23a1b33 525 qdev_init_nofail(dev);
4b48bf05
BS
526 s = sysbus_from_qdev(dev);
527 sysbus_connect_irq(s, 0, irq);
528 sysbus_mmio_map(s, 0, base);
529 if (version == 0) { // SS-600MP only
530 sysbus_mmio_map(s, 1, base + 0x1000);
531 }
532}
533
c227f099 534static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
4b48bf05
BS
535{
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "apc");
e23a1b33 540 qdev_init_nofail(dev);
4b48bf05
BS
541 s = sysbus_from_qdev(dev);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s, 0, power_base);
544 sysbus_connect_irq(s, 0, cpu_halt);
545}
546
c227f099 547static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
4b48bf05
BS
548 int height, int depth)
549{
550 DeviceState *dev;
551 SysBusDevice *s;
552
553 dev = qdev_create(NULL, "SUNW,tcx");
554 qdev_prop_set_taddr(dev, "addr", addr);
555 qdev_prop_set_uint32(dev, "vram_size", vram_size);
556 qdev_prop_set_uint16(dev, "width", width);
557 qdev_prop_set_uint16(dev, "height", height);
558 qdev_prop_set_uint16(dev, "depth", depth);
e23a1b33 559 qdev_init_nofail(dev);
4b48bf05
BS
560 s = sysbus_from_qdev(dev);
561 /* 8-bit plane */
562 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563 /* DAC */
564 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565 /* TEC (dummy) */
566 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569 if (depth == 24) {
570 /* 24-bit plane */
571 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572 /* Control plane */
573 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574 } else {
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577 }
578}
579
325f2747
BS
580/* NCR89C100/MACIO Internal ID register */
581static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582
c227f099 583static void idreg_init(target_phys_addr_t addr)
325f2747
BS
584{
585 DeviceState *dev;
586 SysBusDevice *s;
587
588 dev = qdev_create(NULL, "macio_idreg");
e23a1b33 589 qdev_init_nofail(dev);
325f2747
BS
590 s = sysbus_from_qdev(dev);
591
592 sysbus_mmio_map(s, 0, addr);
593 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594}
595
3150fa50
AK
596typedef struct IDRegState {
597 SysBusDevice busdev;
598 MemoryRegion mem;
599} IDRegState;
600
81a322d4 601static int idreg_init1(SysBusDevice *dev)
325f2747 602{
3150fa50 603 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
325f2747 604
c5705a77
AK
605 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
606 vmstate_register_ram_global(&s->mem);
3150fa50 607 memory_region_set_readonly(&s->mem, true);
750ecd44 608 sysbus_init_mmio(dev, &s->mem);
81a322d4 609 return 0;
325f2747
BS
610}
611
999e12bb
AL
612static void idreg_class_init(ObjectClass *klass, void *data)
613{
614 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
615
616 k->init = idreg_init1;
617}
618
39bffca2
AL
619static TypeInfo idreg_info = {
620 .name = "macio_idreg",
621 .parent = TYPE_SYS_BUS_DEVICE,
622 .instance_size = sizeof(IDRegState),
623 .class_init = idreg_class_init,
325f2747
BS
624};
625
3150fa50
AK
626typedef struct AFXState {
627 SysBusDevice busdev;
628 MemoryRegion mem;
629} AFXState;
630
c5de386a
AT
631/* SS-5 TCX AFX register */
632static void afx_init(target_phys_addr_t addr)
633{
634 DeviceState *dev;
635 SysBusDevice *s;
636
637 dev = qdev_create(NULL, "tcx_afx");
638 qdev_init_nofail(dev);
639 s = sysbus_from_qdev(dev);
640
641 sysbus_mmio_map(s, 0, addr);
642}
643
644static int afx_init1(SysBusDevice *dev)
645{
3150fa50 646 AFXState *s = FROM_SYSBUS(AFXState, dev);
c5de386a 647
c5705a77
AK
648 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
649 vmstate_register_ram_global(&s->mem);
750ecd44 650 sysbus_init_mmio(dev, &s->mem);
c5de386a
AT
651 return 0;
652}
653
999e12bb
AL
654static void afx_class_init(ObjectClass *klass, void *data)
655{
656 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
657
658 k->init = afx_init1;
659}
660
39bffca2
AL
661static TypeInfo afx_info = {
662 .name = "tcx_afx",
663 .parent = TYPE_SYS_BUS_DEVICE,
664 .instance_size = sizeof(AFXState),
665 .class_init = afx_class_init,
c5de386a
AT
666};
667
3150fa50
AK
668typedef struct PROMState {
669 SysBusDevice busdev;
670 MemoryRegion prom;
671} PROMState;
672
f48f6569 673/* Boot PROM (OpenBIOS) */
409dbce5
AJ
674static uint64_t translate_prom_address(void *opaque, uint64_t addr)
675{
676 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
677 return addr + *base_addr - PROM_VADDR;
678}
679
c227f099 680static void prom_init(target_phys_addr_t addr, const char *bios_name)
f48f6569
BS
681{
682 DeviceState *dev;
683 SysBusDevice *s;
684 char *filename;
685 int ret;
686
687 dev = qdev_create(NULL, "openprom");
e23a1b33 688 qdev_init_nofail(dev);
f48f6569
BS
689 s = sysbus_from_qdev(dev);
690
691 sysbus_mmio_map(s, 0, addr);
692
693 /* load boot prom */
694 if (bios_name == NULL) {
695 bios_name = PROM_FILENAME;
696 }
697 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
698 if (filename) {
409dbce5
AJ
699 ret = load_elf(filename, translate_prom_address, &addr, NULL,
700 NULL, NULL, 1, ELF_MACHINE, 0);
f48f6569
BS
701 if (ret < 0 || ret > PROM_SIZE_MAX) {
702 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
703 }
7267c094 704 g_free(filename);
f48f6569
BS
705 } else {
706 ret = -1;
707 }
708 if (ret < 0 || ret > PROM_SIZE_MAX) {
709 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
710 exit(1);
711 }
712}
713
81a322d4 714static int prom_init1(SysBusDevice *dev)
f48f6569 715{
3150fa50 716 PROMState *s = FROM_SYSBUS(PROMState, dev);
f48f6569 717
c5705a77
AK
718 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
719 vmstate_register_ram_global(&s->prom);
3150fa50 720 memory_region_set_readonly(&s->prom, true);
750ecd44 721 sysbus_init_mmio(dev, &s->prom);
81a322d4 722 return 0;
f48f6569
BS
723}
724
999e12bb
AL
725static Property prom_properties[] = {
726 {/* end of property list */},
727};
728
729static void prom_class_init(ObjectClass *klass, void *data)
730{
39bffca2 731 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL
732 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
733
734 k->init = prom_init1;
39bffca2 735 dc->props = prom_properties;
999e12bb
AL
736}
737
39bffca2
AL
738static TypeInfo prom_info = {
739 .name = "openprom",
740 .parent = TYPE_SYS_BUS_DEVICE,
741 .instance_size = sizeof(PROMState),
742 .class_init = prom_class_init,
f48f6569
BS
743};
744
ee6847d1
GH
745typedef struct RamDevice
746{
747 SysBusDevice busdev;
3150fa50 748 MemoryRegion ram;
04843626 749 uint64_t size;
ee6847d1
GH
750} RamDevice;
751
a350db85 752/* System RAM */
81a322d4 753static int ram_init1(SysBusDevice *dev)
a350db85 754{
ee6847d1 755 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
a350db85 756
c5705a77
AK
757 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
758 vmstate_register_ram_global(&d->ram);
750ecd44 759 sysbus_init_mmio(dev, &d->ram);
81a322d4 760 return 0;
a350db85
BS
761}
762
c227f099 763static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
a350db85
BS
764 uint64_t max_mem)
765{
766 DeviceState *dev;
767 SysBusDevice *s;
ee6847d1 768 RamDevice *d;
a350db85
BS
769
770 /* allocate RAM */
771 if ((uint64_t)RAM_size > max_mem) {
772 fprintf(stderr,
773 "qemu: Too much memory for this machine: %d, maximum %d\n",
774 (unsigned int)(RAM_size / (1024 * 1024)),
775 (unsigned int)(max_mem / (1024 * 1024)));
776 exit(1);
777 }
778 dev = qdev_create(NULL, "memory");
a350db85
BS
779 s = sysbus_from_qdev(dev);
780
ee6847d1
GH
781 d = FROM_SYSBUS(RamDevice, s);
782 d->size = RAM_size;
e23a1b33 783 qdev_init_nofail(dev);
ee6847d1 784
a350db85
BS
785 sysbus_mmio_map(s, 0, addr);
786}
787
999e12bb
AL
788static Property ram_properties[] = {
789 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
790 DEFINE_PROP_END_OF_LIST(),
791};
792
793static void ram_class_init(ObjectClass *klass, void *data)
794{
39bffca2 795 DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb
AL
796 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
797
798 k->init = ram_init1;
39bffca2 799 dc->props = ram_properties;
999e12bb
AL
800}
801
39bffca2
AL
802static TypeInfo ram_info = {
803 .name = "memory",
804 .parent = TYPE_SYS_BUS_DEVICE,
805 .instance_size = sizeof(RamDevice),
806 .class_init = ram_class_init,
a350db85
BS
807};
808
89835363
BS
809static void cpu_devinit(const char *cpu_model, unsigned int id,
810 uint64_t prom_addr, qemu_irq **cpu_irqs)
666713c0
BS
811{
812 CPUState *env;
813
814 env = cpu_init(cpu_model);
815 if (!env) {
816 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
817 exit(1);
818 }
819
820 cpu_sparc_set_id(env, id);
821 if (id == 0) {
822 qemu_register_reset(main_cpu_reset, env);
823 } else {
824 qemu_register_reset(secondary_cpu_reset, env);
825 env->halted = 1;
826 }
827 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
828 env->prom_addr = prom_addr;
666713c0
BS
829}
830
c227f099 831static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
3ebf5aaf 832 const char *boot_device,
3023f332 833 const char *kernel_filename,
3ebf5aaf
BS
834 const char *kernel_cmdline,
835 const char *initrd_filename, const char *cpu_model)
420557e8 836{
713c45fa 837 unsigned int i;
cfb9de9c 838 void *iommu, *espdma, *ledma, *nvram;
a1961a4b 839 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
6f6260c7 840 espdma_irq, ledma_irq;
73d74342 841 qemu_irq esp_reset, dma_enable;
2582cfa0 842 qemu_irq fdc_tc;
6d0c293d 843 qemu_irq *cpu_halt;
5c6602c5 844 unsigned long kernel_size;
fd8014e1 845 DriveInfo *fd[MAX_FD];
3cce6243 846 void *fw_cfg;
9a62fb24 847 unsigned int num_vsimms;
420557e8 848
ba3c64fb 849 /* init CPUs */
3ebf5aaf
BS
850 if (!cpu_model)
851 cpu_model = hwdef->default_cpu_model;
b3a23197 852
ba3c64fb 853 for(i = 0; i < smp_cpus; i++) {
89835363 854 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
ba3c64fb 855 }
b3a23197
BS
856
857 for (i = smp_cpus; i < MAX_CPUS; i++)
858 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
859
3ebf5aaf 860
3ebf5aaf 861 /* set up devices */
a350db85 862 ram_init(0, RAM_size, hwdef->max_mem);
676d9b9b
AT
863 /* models without ECC don't trap when missing ram is accessed */
864 if (!hwdef->ecc_base) {
865 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
866 }
a350db85 867
f48f6569
BS
868 prom_init(hwdef->slavio_base, bios_name);
869
d453c2c3
BS
870 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
871 hwdef->intctl_base + 0x10000ULL,
462eda24 872 cpu_irqs);
a1961a4b
BS
873
874 for (i = 0; i < 32; i++) {
d453c2c3 875 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
a1961a4b
BS
876 }
877 for (i = 0; i < MAX_CPUS; i++) {
d453c2c3 878 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
a1961a4b 879 }
b3a23197 880
fe096129 881 if (hwdef->idreg_base) {
325f2747 882 idreg_init(hwdef->idreg_base);
4c2485de
BS
883 }
884
c5de386a
AT
885 if (hwdef->afx_base) {
886 afx_init(hwdef->afx_base);
887 }
888
ff403da6 889 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
c533e0b3 890 slavio_irq[30]);
ff403da6 891
3386376c
AT
892 if (hwdef->iommu_pad_base) {
893 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
894 Software shouldn't use aliased addresses, neither should it crash
895 when does. Using empty_slot instead of aliasing can help with
896 debugging such accesses */
897 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
898 }
899
c533e0b3 900 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
86d1c388 901 iommu, &espdma_irq, 0);
2d069bab 902
5aca8c3b 903 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
86d1c388 904 slavio_irq[16], iommu, &ledma_irq, 1);
ba3c64fb 905
eee0b836
BS
906 if (graphic_depth != 8 && graphic_depth != 24) {
907 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
908 exit (1);
909 }
9a62fb24
BB
910 num_vsimms = 0;
911 if (num_vsimms == 0) {
912 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
913 graphic_depth);
914 }
915
916 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
917 /* vsimm registers probed by OBP */
918 if (hwdef->vsimm[i].reg_base) {
919 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
920 }
921 }
922
923 if (hwdef->sx_base) {
924 empty_slot_init(hwdef->sx_base, 0x2000);
925 }
dbe06e18 926
74ff8d90 927 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
dbe06e18 928
d95d8f1c 929 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
81732d19 930
c533e0b3 931 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
81732d19 932
c533e0b3 933 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
993fbfdb 934 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
b81b3b10
FB
935 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
936 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
c533e0b3 937 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
aeeb69c7 938 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
741402f9 939
6d0c293d 940 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
b2b6f6ec
BS
941 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
942 slavio_irq[30], fdc_tc);
943
2582cfa0
BS
944 if (hwdef->apc_base) {
945 apc_init(hwdef->apc_base, cpu_halt[0]);
946 }
2be17ebd 947
fe096129 948 if (hwdef->fd_base) {
e4bcb14c 949 /* there is zero or one floppy drive */
309e60bd 950 memset(fd, 0, sizeof(fd));
fd8014e1 951 fd[0] = drive_get(IF_FLOPPY, 0, 0);
c533e0b3 952 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
2582cfa0 953 &fdc_tc);
e4bcb14c
TS
954 }
955
956 if (drive_get_max_bus(IF_SCSI) > 0) {
957 fprintf(stderr, "qemu: too many SCSI bus\n");
958 exit(1);
959 }
960
cfb9de9c
PB
961 esp_init(hwdef->esp_base, 2,
962 espdma_memory_read, espdma_memory_write,
73d74342 963 espdma, espdma_irq, &esp_reset, &dma_enable);
74ff8d90 964
73d74342
BS
965 qdev_connect_gpio_out(espdma, 0, esp_reset);
966 qdev_connect_gpio_out(espdma, 1, dma_enable);
f1587550 967
fa28ec52
BS
968 if (hwdef->cs_base) {
969 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
c533e0b3 970 slavio_irq[5]);
fa28ec52 971 }
b3ceef24 972
9a62fb24
BB
973 if (hwdef->dbri_base) {
974 /* ISDN chip with attached CS4215 audio codec */
975 /* prom space */
976 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
977 /* reg space */
978 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
979 }
980
981 if (hwdef->bpp_base) {
982 /* parallel port */
983 empty_slot_init(hwdef->bpp_base, 0x20);
984 }
985
293f78bc
BS
986 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
987 RAM_size);
36cd9210 988
36cd9210 989 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
b3ceef24 990 boot_device, RAM_size, kernel_size, graphic_width,
905fdcb5
BS
991 graphic_height, graphic_depth, hwdef->nvram_machine_id,
992 "Sun4m");
7eb0c8e8 993
fe096129 994 if (hwdef->ecc_base)
c533e0b3 995 ecc_init(hwdef->ecc_base, slavio_irq[28],
e42c20b4 996 hwdef->ecc_version);
3cce6243
BS
997
998 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
999 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
905fdcb5
BS
1000 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1001 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
fbfcf955 1002 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
513f789f
BS
1003 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1004 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1005 if (kernel_cmdline) {
1006 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
3c178e72 1007 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
6bb4ca57
BS
1008 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1009 (uint8_t*)strdup(kernel_cmdline),
1010 strlen(kernel_cmdline) + 1);
748a4ee3
BS
1011 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1012 strlen(kernel_cmdline) + 1);
513f789f
BS
1013 } else {
1014 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
748a4ee3 1015 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
513f789f
BS
1016 }
1017 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1018 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1019 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1020 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
36cd9210
BS
1021}
1022
905fdcb5
BS
1023enum {
1024 ss2_id = 0,
1025 ss5_id = 32,
1026 vger_id,
1027 lx_id,
1028 ss4_id,
1029 scls_id,
1030 sbook_id,
1031 ss10_id = 64,
1032 ss20_id,
1033 ss600mp_id,
1034 ss1000_id = 96,
1035 ss2000_id,
1036};
1037
8137cde8 1038static const struct sun4m_hwdef sun4m_hwdefs[] = {
36cd9210
BS
1039 /* SS-5 */
1040 {
1041 .iommu_base = 0x10000000,
3386376c
AT
1042 .iommu_pad_base = 0x10004000,
1043 .iommu_pad_len = 0x0fffb000,
36cd9210
BS
1044 .tcx_base = 0x50000000,
1045 .cs_base = 0x6c000000,
384ccb5d 1046 .slavio_base = 0x70000000,
36cd9210
BS
1047 .ms_kb_base = 0x71000000,
1048 .serial_base = 0x71100000,
1049 .nvram_base = 0x71200000,
1050 .fd_base = 0x71400000,
1051 .counter_base = 0x71d00000,
1052 .intctl_base = 0x71e00000,
4c2485de 1053 .idreg_base = 0x78000000,
36cd9210
BS
1054 .dma_base = 0x78400000,
1055 .esp_base = 0x78800000,
1056 .le_base = 0x78c00000,
127fc407 1057 .apc_base = 0x6a000000,
c5de386a 1058 .afx_base = 0x6e000000,
0019ad53
BS
1059 .aux1_base = 0x71900000,
1060 .aux2_base = 0x71910000,
905fdcb5
BS
1061 .nvram_machine_id = 0x80,
1062 .machine_id = ss5_id,
cf3102ac 1063 .iommu_version = 0x05000000,
3ebf5aaf
BS
1064 .max_mem = 0x10000000,
1065 .default_cpu_model = "Fujitsu MB86904",
e0353fe2
BS
1066 },
1067 /* SS-10 */
e0353fe2 1068 {
5dcb6b91
BS
1069 .iommu_base = 0xfe0000000ULL,
1070 .tcx_base = 0xe20000000ULL,
5dcb6b91
BS
1071 .slavio_base = 0xff0000000ULL,
1072 .ms_kb_base = 0xff1000000ULL,
1073 .serial_base = 0xff1100000ULL,
1074 .nvram_base = 0xff1200000ULL,
1075 .fd_base = 0xff1700000ULL,
1076 .counter_base = 0xff1300000ULL,
1077 .intctl_base = 0xff1400000ULL,
4c2485de 1078 .idreg_base = 0xef0000000ULL,
5dcb6b91
BS
1079 .dma_base = 0xef0400000ULL,
1080 .esp_base = 0xef0800000ULL,
1081 .le_base = 0xef0c00000ULL,
0019ad53 1082 .apc_base = 0xefa000000ULL, // XXX should not exist
127fc407
BS
1083 .aux1_base = 0xff1800000ULL,
1084 .aux2_base = 0xff1a01000ULL,
7eb0c8e8
BS
1085 .ecc_base = 0xf00000000ULL,
1086 .ecc_version = 0x10000000, // version 0, implementation 1
905fdcb5
BS
1087 .nvram_machine_id = 0x72,
1088 .machine_id = ss10_id,
7fbfb139 1089 .iommu_version = 0x03000000,
6ef05b95 1090 .max_mem = 0xf00000000ULL,
3ebf5aaf 1091 .default_cpu_model = "TI SuperSparc II",
36cd9210 1092 },
6a3b9cc9
BS
1093 /* SS-600MP */
1094 {
1095 .iommu_base = 0xfe0000000ULL,
1096 .tcx_base = 0xe20000000ULL,
6a3b9cc9
BS
1097 .slavio_base = 0xff0000000ULL,
1098 .ms_kb_base = 0xff1000000ULL,
1099 .serial_base = 0xff1100000ULL,
1100 .nvram_base = 0xff1200000ULL,
6a3b9cc9
BS
1101 .counter_base = 0xff1300000ULL,
1102 .intctl_base = 0xff1400000ULL,
1103 .dma_base = 0xef0081000ULL,
1104 .esp_base = 0xef0080000ULL,
1105 .le_base = 0xef0060000ULL,
0019ad53 1106 .apc_base = 0xefa000000ULL, // XXX should not exist
127fc407
BS
1107 .aux1_base = 0xff1800000ULL,
1108 .aux2_base = 0xff1a01000ULL, // XXX should not exist
7eb0c8e8
BS
1109 .ecc_base = 0xf00000000ULL,
1110 .ecc_version = 0x00000000, // version 0, implementation 0
905fdcb5
BS
1111 .nvram_machine_id = 0x71,
1112 .machine_id = ss600mp_id,
7fbfb139 1113 .iommu_version = 0x01000000,
6ef05b95 1114 .max_mem = 0xf00000000ULL,
3ebf5aaf 1115 .default_cpu_model = "TI SuperSparc II",
6a3b9cc9 1116 },
ae40972f
BS
1117 /* SS-20 */
1118 {
1119 .iommu_base = 0xfe0000000ULL,
1120 .tcx_base = 0xe20000000ULL,
ae40972f
BS
1121 .slavio_base = 0xff0000000ULL,
1122 .ms_kb_base = 0xff1000000ULL,
1123 .serial_base = 0xff1100000ULL,
1124 .nvram_base = 0xff1200000ULL,
1125 .fd_base = 0xff1700000ULL,
1126 .counter_base = 0xff1300000ULL,
1127 .intctl_base = 0xff1400000ULL,
4c2485de 1128 .idreg_base = 0xef0000000ULL,
ae40972f
BS
1129 .dma_base = 0xef0400000ULL,
1130 .esp_base = 0xef0800000ULL,
1131 .le_base = 0xef0c00000ULL,
9a62fb24 1132 .bpp_base = 0xef4800000ULL,
0019ad53 1133 .apc_base = 0xefa000000ULL, // XXX should not exist
577d8dd4
BS
1134 .aux1_base = 0xff1800000ULL,
1135 .aux2_base = 0xff1a01000ULL,
9a62fb24
BB
1136 .dbri_base = 0xee0000000ULL,
1137 .sx_base = 0xf80000000ULL,
1138 .vsimm = {
1139 {
1140 .reg_base = 0x9c000000ULL,
1141 .vram_base = 0xfc000000ULL
1142 }, {
1143 .reg_base = 0x90000000ULL,
1144 .vram_base = 0xf0000000ULL
1145 }, {
1146 .reg_base = 0x94000000ULL
1147 }, {
1148 .reg_base = 0x98000000ULL
1149 }
1150 },
ae40972f
BS
1151 .ecc_base = 0xf00000000ULL,
1152 .ecc_version = 0x20000000, // version 0, implementation 2
905fdcb5
BS
1153 .nvram_machine_id = 0x72,
1154 .machine_id = ss20_id,
ae40972f 1155 .iommu_version = 0x13000000,
6ef05b95 1156 .max_mem = 0xf00000000ULL,
ae40972f
BS
1157 .default_cpu_model = "TI SuperSparc II",
1158 },
a526a31c
BS
1159 /* Voyager */
1160 {
1161 .iommu_base = 0x10000000,
1162 .tcx_base = 0x50000000,
a526a31c
BS
1163 .slavio_base = 0x70000000,
1164 .ms_kb_base = 0x71000000,
1165 .serial_base = 0x71100000,
1166 .nvram_base = 0x71200000,
1167 .fd_base = 0x71400000,
1168 .counter_base = 0x71d00000,
1169 .intctl_base = 0x71e00000,
1170 .idreg_base = 0x78000000,
1171 .dma_base = 0x78400000,
1172 .esp_base = 0x78800000,
1173 .le_base = 0x78c00000,
1174 .apc_base = 0x71300000, // pmc
1175 .aux1_base = 0x71900000,
1176 .aux2_base = 0x71910000,
905fdcb5
BS
1177 .nvram_machine_id = 0x80,
1178 .machine_id = vger_id,
a526a31c 1179 .iommu_version = 0x05000000,
a526a31c
BS
1180 .max_mem = 0x10000000,
1181 .default_cpu_model = "Fujitsu MB86904",
1182 },
1183 /* LX */
1184 {
1185 .iommu_base = 0x10000000,
3386376c
AT
1186 .iommu_pad_base = 0x10004000,
1187 .iommu_pad_len = 0x0fffb000,
a526a31c 1188 .tcx_base = 0x50000000,
a526a31c
BS
1189 .slavio_base = 0x70000000,
1190 .ms_kb_base = 0x71000000,
1191 .serial_base = 0x71100000,
1192 .nvram_base = 0x71200000,
1193 .fd_base = 0x71400000,
1194 .counter_base = 0x71d00000,
1195 .intctl_base = 0x71e00000,
1196 .idreg_base = 0x78000000,
1197 .dma_base = 0x78400000,
1198 .esp_base = 0x78800000,
1199 .le_base = 0x78c00000,
a526a31c
BS
1200 .aux1_base = 0x71900000,
1201 .aux2_base = 0x71910000,
905fdcb5
BS
1202 .nvram_machine_id = 0x80,
1203 .machine_id = lx_id,
a526a31c 1204 .iommu_version = 0x04000000,
a526a31c
BS
1205 .max_mem = 0x10000000,
1206 .default_cpu_model = "TI MicroSparc I",
1207 },
1208 /* SS-4 */
1209 {
1210 .iommu_base = 0x10000000,
1211 .tcx_base = 0x50000000,
1212 .cs_base = 0x6c000000,
1213 .slavio_base = 0x70000000,
1214 .ms_kb_base = 0x71000000,
1215 .serial_base = 0x71100000,
1216 .nvram_base = 0x71200000,
1217 .fd_base = 0x71400000,
1218 .counter_base = 0x71d00000,
1219 .intctl_base = 0x71e00000,
1220 .idreg_base = 0x78000000,
1221 .dma_base = 0x78400000,
1222 .esp_base = 0x78800000,
1223 .le_base = 0x78c00000,
1224 .apc_base = 0x6a000000,
1225 .aux1_base = 0x71900000,
1226 .aux2_base = 0x71910000,
905fdcb5
BS
1227 .nvram_machine_id = 0x80,
1228 .machine_id = ss4_id,
a526a31c 1229 .iommu_version = 0x05000000,
a526a31c
BS
1230 .max_mem = 0x10000000,
1231 .default_cpu_model = "Fujitsu MB86904",
1232 },
1233 /* SPARCClassic */
1234 {
1235 .iommu_base = 0x10000000,
1236 .tcx_base = 0x50000000,
a526a31c
BS
1237 .slavio_base = 0x70000000,
1238 .ms_kb_base = 0x71000000,
1239 .serial_base = 0x71100000,
1240 .nvram_base = 0x71200000,
1241 .fd_base = 0x71400000,
1242 .counter_base = 0x71d00000,
1243 .intctl_base = 0x71e00000,
1244 .idreg_base = 0x78000000,
1245 .dma_base = 0x78400000,
1246 .esp_base = 0x78800000,
1247 .le_base = 0x78c00000,
1248 .apc_base = 0x6a000000,
1249 .aux1_base = 0x71900000,
1250 .aux2_base = 0x71910000,
905fdcb5
BS
1251 .nvram_machine_id = 0x80,
1252 .machine_id = scls_id,
a526a31c 1253 .iommu_version = 0x05000000,
a526a31c
BS
1254 .max_mem = 0x10000000,
1255 .default_cpu_model = "TI MicroSparc I",
1256 },
1257 /* SPARCbook */
1258 {
1259 .iommu_base = 0x10000000,
1260 .tcx_base = 0x50000000, // XXX
a526a31c
BS
1261 .slavio_base = 0x70000000,
1262 .ms_kb_base = 0x71000000,
1263 .serial_base = 0x71100000,
1264 .nvram_base = 0x71200000,
1265 .fd_base = 0x71400000,
1266 .counter_base = 0x71d00000,
1267 .intctl_base = 0x71e00000,
1268 .idreg_base = 0x78000000,
1269 .dma_base = 0x78400000,
1270 .esp_base = 0x78800000,
1271 .le_base = 0x78c00000,
1272 .apc_base = 0x6a000000,
1273 .aux1_base = 0x71900000,
1274 .aux2_base = 0x71910000,
905fdcb5
BS
1275 .nvram_machine_id = 0x80,
1276 .machine_id = sbook_id,
a526a31c 1277 .iommu_version = 0x05000000,
a526a31c
BS
1278 .max_mem = 0x10000000,
1279 .default_cpu_model = "TI MicroSparc I",
1280 },
36cd9210
BS
1281};
1282
36cd9210 1283/* SPARCstation 5 hardware initialisation */
c227f099 1284static void ss5_init(ram_addr_t RAM_size,
3023f332 1285 const char *boot_device,
b881c2c6
BS
1286 const char *kernel_filename, const char *kernel_cmdline,
1287 const char *initrd_filename, const char *cpu_model)
36cd9210 1288{
3023f332 1289 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
3ebf5aaf 1290 kernel_cmdline, initrd_filename, cpu_model);
420557e8 1291}
c0e564d5 1292
e0353fe2 1293/* SPARCstation 10 hardware initialisation */
c227f099 1294static void ss10_init(ram_addr_t RAM_size,
3023f332 1295 const char *boot_device,
b881c2c6
BS
1296 const char *kernel_filename, const char *kernel_cmdline,
1297 const char *initrd_filename, const char *cpu_model)
e0353fe2 1298{
3023f332 1299 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
3ebf5aaf 1300 kernel_cmdline, initrd_filename, cpu_model);
e0353fe2
BS
1301}
1302
6a3b9cc9 1303/* SPARCserver 600MP hardware initialisation */
c227f099 1304static void ss600mp_init(ram_addr_t RAM_size,
3023f332 1305 const char *boot_device,
77f193da
BS
1306 const char *kernel_filename,
1307 const char *kernel_cmdline,
6a3b9cc9
BS
1308 const char *initrd_filename, const char *cpu_model)
1309{
3023f332 1310 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
3ebf5aaf 1311 kernel_cmdline, initrd_filename, cpu_model);
6a3b9cc9
BS
1312}
1313
ae40972f 1314/* SPARCstation 20 hardware initialisation */
c227f099 1315static void ss20_init(ram_addr_t RAM_size,
3023f332 1316 const char *boot_device,
ae40972f
BS
1317 const char *kernel_filename, const char *kernel_cmdline,
1318 const char *initrd_filename, const char *cpu_model)
1319{
3023f332 1320 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
ee76f82e
BS
1321 kernel_cmdline, initrd_filename, cpu_model);
1322}
1323
a526a31c 1324/* SPARCstation Voyager hardware initialisation */
c227f099 1325static void vger_init(ram_addr_t RAM_size,
3023f332 1326 const char *boot_device,
a526a31c
BS
1327 const char *kernel_filename, const char *kernel_cmdline,
1328 const char *initrd_filename, const char *cpu_model)
1329{
3023f332 1330 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
a526a31c
BS
1331 kernel_cmdline, initrd_filename, cpu_model);
1332}
1333
1334/* SPARCstation LX hardware initialisation */
c227f099 1335static void ss_lx_init(ram_addr_t RAM_size,
3023f332 1336 const char *boot_device,
a526a31c
BS
1337 const char *kernel_filename, const char *kernel_cmdline,
1338 const char *initrd_filename, const char *cpu_model)
1339{
3023f332 1340 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
a526a31c
BS
1341 kernel_cmdline, initrd_filename, cpu_model);
1342}
1343
1344/* SPARCstation 4 hardware initialisation */
c227f099 1345static void ss4_init(ram_addr_t RAM_size,
3023f332 1346 const char *boot_device,
a526a31c
BS
1347 const char *kernel_filename, const char *kernel_cmdline,
1348 const char *initrd_filename, const char *cpu_model)
1349{
3023f332 1350 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
a526a31c
BS
1351 kernel_cmdline, initrd_filename, cpu_model);
1352}
1353
1354/* SPARCClassic hardware initialisation */
c227f099 1355static void scls_init(ram_addr_t RAM_size,
3023f332 1356 const char *boot_device,
a526a31c
BS
1357 const char *kernel_filename, const char *kernel_cmdline,
1358 const char *initrd_filename, const char *cpu_model)
1359{
3023f332 1360 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
a526a31c
BS
1361 kernel_cmdline, initrd_filename, cpu_model);
1362}
1363
1364/* SPARCbook hardware initialisation */
c227f099 1365static void sbook_init(ram_addr_t RAM_size,
3023f332 1366 const char *boot_device,
a526a31c
BS
1367 const char *kernel_filename, const char *kernel_cmdline,
1368 const char *initrd_filename, const char *cpu_model)
1369{
3023f332 1370 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
a526a31c
BS
1371 kernel_cmdline, initrd_filename, cpu_model);
1372}
1373
f80f9ec9 1374static QEMUMachine ss5_machine = {
66de733b
BS
1375 .name = "SS-5",
1376 .desc = "Sun4m platform, SPARCstation 5",
1377 .init = ss5_init,
c9b1ae2c 1378 .use_scsi = 1,
0c257437 1379 .is_default = 1,
c0e564d5 1380};
e0353fe2 1381
f80f9ec9 1382static QEMUMachine ss10_machine = {
66de733b
BS
1383 .name = "SS-10",
1384 .desc = "Sun4m platform, SPARCstation 10",
1385 .init = ss10_init,
c9b1ae2c 1386 .use_scsi = 1,
1bcee014 1387 .max_cpus = 4,
e0353fe2 1388};
6a3b9cc9 1389
f80f9ec9 1390static QEMUMachine ss600mp_machine = {
66de733b
BS
1391 .name = "SS-600MP",
1392 .desc = "Sun4m platform, SPARCserver 600MP",
1393 .init = ss600mp_init,
c9b1ae2c 1394 .use_scsi = 1,
1bcee014 1395 .max_cpus = 4,
6a3b9cc9 1396};
ae40972f 1397
f80f9ec9 1398static QEMUMachine ss20_machine = {
66de733b
BS
1399 .name = "SS-20",
1400 .desc = "Sun4m platform, SPARCstation 20",
1401 .init = ss20_init,
c9b1ae2c 1402 .use_scsi = 1,
1bcee014 1403 .max_cpus = 4,
ae40972f
BS
1404};
1405
f80f9ec9 1406static QEMUMachine voyager_machine = {
66de733b
BS
1407 .name = "Voyager",
1408 .desc = "Sun4m platform, SPARCstation Voyager",
1409 .init = vger_init,
c9b1ae2c 1410 .use_scsi = 1,
a526a31c
BS
1411};
1412
f80f9ec9 1413static QEMUMachine ss_lx_machine = {
66de733b
BS
1414 .name = "LX",
1415 .desc = "Sun4m platform, SPARCstation LX",
1416 .init = ss_lx_init,
c9b1ae2c 1417 .use_scsi = 1,
a526a31c
BS
1418};
1419
f80f9ec9 1420static QEMUMachine ss4_machine = {
66de733b
BS
1421 .name = "SS-4",
1422 .desc = "Sun4m platform, SPARCstation 4",
1423 .init = ss4_init,
c9b1ae2c 1424 .use_scsi = 1,
a526a31c
BS
1425};
1426
f80f9ec9 1427static QEMUMachine scls_machine = {
66de733b
BS
1428 .name = "SPARCClassic",
1429 .desc = "Sun4m platform, SPARCClassic",
1430 .init = scls_init,
c9b1ae2c 1431 .use_scsi = 1,
a526a31c
BS
1432};
1433
f80f9ec9 1434static QEMUMachine sbook_machine = {
66de733b
BS
1435 .name = "SPARCbook",
1436 .desc = "Sun4m platform, SPARCbook",
1437 .init = sbook_init,
c9b1ae2c 1438 .use_scsi = 1,
a526a31c
BS
1439};
1440
7d85892b
BS
1441static const struct sun4d_hwdef sun4d_hwdefs[] = {
1442 /* SS-1000 */
1443 {
1444 .iounit_bases = {
1445 0xfe0200000ULL,
1446 0xfe1200000ULL,
1447 0xfe2200000ULL,
1448 0xfe3200000ULL,
1449 -1,
1450 },
1451 .tcx_base = 0x820000000ULL,
1452 .slavio_base = 0xf00000000ULL,
1453 .ms_kb_base = 0xf00240000ULL,
1454 .serial_base = 0xf00200000ULL,
1455 .nvram_base = 0xf00280000ULL,
1456 .counter_base = 0xf00300000ULL,
1457 .espdma_base = 0x800081000ULL,
1458 .esp_base = 0x800080000ULL,
1459 .ledma_base = 0x800040000ULL,
1460 .le_base = 0x800060000ULL,
1461 .sbi_base = 0xf02800000ULL,
905fdcb5
BS
1462 .nvram_machine_id = 0x80,
1463 .machine_id = ss1000_id,
7d85892b 1464 .iounit_version = 0x03000000,
6ef05b95 1465 .max_mem = 0xf00000000ULL,
7d85892b
BS
1466 .default_cpu_model = "TI SuperSparc II",
1467 },
1468 /* SS-2000 */
1469 {
1470 .iounit_bases = {
1471 0xfe0200000ULL,
1472 0xfe1200000ULL,
1473 0xfe2200000ULL,
1474 0xfe3200000ULL,
1475 0xfe4200000ULL,
1476 },
1477 .tcx_base = 0x820000000ULL,
1478 .slavio_base = 0xf00000000ULL,
1479 .ms_kb_base = 0xf00240000ULL,
1480 .serial_base = 0xf00200000ULL,
1481 .nvram_base = 0xf00280000ULL,
1482 .counter_base = 0xf00300000ULL,
1483 .espdma_base = 0x800081000ULL,
1484 .esp_base = 0x800080000ULL,
1485 .ledma_base = 0x800040000ULL,
1486 .le_base = 0x800060000ULL,
1487 .sbi_base = 0xf02800000ULL,
905fdcb5
BS
1488 .nvram_machine_id = 0x80,
1489 .machine_id = ss2000_id,
7d85892b 1490 .iounit_version = 0x03000000,
6ef05b95 1491 .max_mem = 0xf00000000ULL,
7d85892b
BS
1492 .default_cpu_model = "TI SuperSparc II",
1493 },
1494};
1495
c227f099 1496static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
4b48bf05
BS
1497{
1498 DeviceState *dev;
1499 SysBusDevice *s;
1500 unsigned int i;
1501
1502 dev = qdev_create(NULL, "sbi");
e23a1b33 1503 qdev_init_nofail(dev);
4b48bf05
BS
1504
1505 s = sysbus_from_qdev(dev);
1506
1507 for (i = 0; i < MAX_CPUS; i++) {
1508 sysbus_connect_irq(s, i, *parent_irq[i]);
1509 }
1510
1511 sysbus_mmio_map(s, 0, addr);
1512
1513 return dev;
1514}
1515
c227f099 1516static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
7d85892b 1517 const char *boot_device,
3023f332 1518 const char *kernel_filename,
7d85892b
BS
1519 const char *kernel_cmdline,
1520 const char *initrd_filename, const char *cpu_model)
1521{
7d85892b 1522 unsigned int i;
7fc06735
BS
1523 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1524 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
6f6260c7 1525 espdma_irq, ledma_irq;
73d74342 1526 qemu_irq esp_reset, dma_enable;
5c6602c5 1527 unsigned long kernel_size;
3cce6243 1528 void *fw_cfg;
7fc06735 1529 DeviceState *dev;
7d85892b
BS
1530
1531 /* init CPUs */
1532 if (!cpu_model)
1533 cpu_model = hwdef->default_cpu_model;
1534
666713c0 1535 for(i = 0; i < smp_cpus; i++) {
89835363 1536 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
7d85892b
BS
1537 }
1538
1539 for (i = smp_cpus; i < MAX_CPUS; i++)
1540 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1541
7d85892b 1542 /* set up devices */
a350db85
BS
1543 ram_init(0, RAM_size, hwdef->max_mem);
1544
f48f6569
BS
1545 prom_init(hwdef->slavio_base, bios_name);
1546
7fc06735
BS
1547 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1548
1549 for (i = 0; i < 32; i++) {
1550 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1551 }
1552 for (i = 0; i < MAX_CPUS; i++) {
1553 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1554 }
7d85892b
BS
1555
1556 for (i = 0; i < MAX_IOUNITS; i++)
c227f099 1557 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
ff403da6
BS
1558 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1559 hwdef->iounit_version,
c533e0b3 1560 sbi_irq[0]);
7d85892b 1561
c533e0b3 1562 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
86d1c388 1563 iounits[0], &espdma_irq, 0);
7d85892b 1564
86d1c388 1565 /* should be lebuffer instead */
c533e0b3 1566 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
86d1c388 1567 iounits[0], &ledma_irq, 0);
7d85892b
BS
1568
1569 if (graphic_depth != 8 && graphic_depth != 24) {
1570 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1571 exit (1);
1572 }
d95d8f1c 1573 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
dc828ca1 1574 graphic_depth);
7d85892b 1575
74ff8d90 1576 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
7d85892b 1577
d95d8f1c 1578 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
7d85892b 1579
c533e0b3 1580 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
7d85892b 1581
c533e0b3 1582 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
993fbfdb 1583 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
7d85892b
BS
1584 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1585 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
c533e0b3 1586 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
aeeb69c7 1587 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
7d85892b
BS
1588
1589 if (drive_get_max_bus(IF_SCSI) > 0) {
1590 fprintf(stderr, "qemu: too many SCSI bus\n");
1591 exit(1);
1592 }
1593
cfb9de9c
PB
1594 esp_init(hwdef->esp_base, 2,
1595 espdma_memory_read, espdma_memory_write,
73d74342
BS
1596 espdma, espdma_irq, &esp_reset, &dma_enable);
1597
1598 qdev_connect_gpio_out(espdma, 0, esp_reset);
1599 qdev_connect_gpio_out(espdma, 1, dma_enable);
7d85892b 1600
293f78bc
BS
1601 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1602 RAM_size);
7d85892b
BS
1603
1604 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1605 boot_device, RAM_size, kernel_size, graphic_width,
905fdcb5
BS
1606 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1607 "Sun4d");
3cce6243
BS
1608
1609 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1610 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
905fdcb5
BS
1611 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1612 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
513f789f
BS
1613 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1614 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1615 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1616 if (kernel_cmdline) {
1617 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
3c178e72 1618 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
6bb4ca57
BS
1619 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1620 (uint8_t*)strdup(kernel_cmdline),
1621 strlen(kernel_cmdline) + 1);
513f789f
BS
1622 } else {
1623 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1624 }
1625 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1626 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1627 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1628 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
7d85892b
BS
1629}
1630
1631/* SPARCserver 1000 hardware initialisation */
c227f099 1632static void ss1000_init(ram_addr_t RAM_size,
3023f332 1633 const char *boot_device,
7d85892b
BS
1634 const char *kernel_filename, const char *kernel_cmdline,
1635 const char *initrd_filename, const char *cpu_model)
1636{
3023f332 1637 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
7d85892b
BS
1638 kernel_cmdline, initrd_filename, cpu_model);
1639}
1640
1641/* SPARCcenter 2000 hardware initialisation */
c227f099 1642static void ss2000_init(ram_addr_t RAM_size,
3023f332 1643 const char *boot_device,
7d85892b
BS
1644 const char *kernel_filename, const char *kernel_cmdline,
1645 const char *initrd_filename, const char *cpu_model)
1646{
3023f332 1647 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
7d85892b
BS
1648 kernel_cmdline, initrd_filename, cpu_model);
1649}
1650
f80f9ec9 1651static QEMUMachine ss1000_machine = {
66de733b
BS
1652 .name = "SS-1000",
1653 .desc = "Sun4d platform, SPARCserver 1000",
1654 .init = ss1000_init,
c9b1ae2c 1655 .use_scsi = 1,
1bcee014 1656 .max_cpus = 8,
7d85892b
BS
1657};
1658
f80f9ec9 1659static QEMUMachine ss2000_machine = {
66de733b
BS
1660 .name = "SS-2000",
1661 .desc = "Sun4d platform, SPARCcenter 2000",
1662 .init = ss2000_init,
c9b1ae2c 1663 .use_scsi = 1,
1bcee014 1664 .max_cpus = 20,
7d85892b 1665};
8137cde8
BS
1666
1667static const struct sun4c_hwdef sun4c_hwdefs[] = {
1668 /* SS-2 */
1669 {
1670 .iommu_base = 0xf8000000,
1671 .tcx_base = 0xfe000000,
8137cde8
BS
1672 .slavio_base = 0xf6000000,
1673 .intctl_base = 0xf5000000,
1674 .counter_base = 0xf3000000,
1675 .ms_kb_base = 0xf0000000,
1676 .serial_base = 0xf1000000,
1677 .nvram_base = 0xf2000000,
1678 .fd_base = 0xf7200000,
1679 .dma_base = 0xf8400000,
1680 .esp_base = 0xf8800000,
1681 .le_base = 0xf8c00000,
8137cde8 1682 .aux1_base = 0xf7400003,
8137cde8
BS
1683 .nvram_machine_id = 0x55,
1684 .machine_id = ss2_id,
1685 .max_mem = 0x10000000,
1686 .default_cpu_model = "Cypress CY7C601",
1687 },
1688};
1689
c227f099 1690static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
4b48bf05
BS
1691 qemu_irq *parent_irq)
1692{
1693 DeviceState *dev;
1694 SysBusDevice *s;
1695 unsigned int i;
1696
1697 dev = qdev_create(NULL, "sun4c_intctl");
e23a1b33 1698 qdev_init_nofail(dev);
4b48bf05
BS
1699
1700 s = sysbus_from_qdev(dev);
1701
1702 for (i = 0; i < MAX_PILS; i++) {
1703 sysbus_connect_irq(s, i, parent_irq[i]);
1704 }
1705 sysbus_mmio_map(s, 0, addr);
1706
1707 return dev;
1708}
1709
c227f099 1710static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
8137cde8 1711 const char *boot_device,
3023f332 1712 const char *kernel_filename,
8137cde8
BS
1713 const char *kernel_cmdline,
1714 const char *initrd_filename, const char *cpu_model)
1715{
cfb9de9c 1716 void *iommu, *espdma, *ledma, *nvram;
e32cba29 1717 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
73d74342 1718 qemu_irq esp_reset, dma_enable;
2582cfa0 1719 qemu_irq fdc_tc;
5c6602c5 1720 unsigned long kernel_size;
fd8014e1 1721 DriveInfo *fd[MAX_FD];
8137cde8 1722 void *fw_cfg;
e32cba29
BS
1723 DeviceState *dev;
1724 unsigned int i;
8137cde8
BS
1725
1726 /* init CPU */
1727 if (!cpu_model)
1728 cpu_model = hwdef->default_cpu_model;
1729
89835363 1730 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
8137cde8 1731
8137cde8 1732 /* set up devices */
a350db85
BS
1733 ram_init(0, RAM_size, hwdef->max_mem);
1734
f48f6569
BS
1735 prom_init(hwdef->slavio_base, bios_name);
1736
e32cba29
BS
1737 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1738
1739 for (i = 0; i < 8; i++) {
1740 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1741 }
8137cde8
BS
1742
1743 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
c533e0b3 1744 slavio_irq[1]);
8137cde8 1745
c533e0b3 1746 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
86d1c388 1747 iommu, &espdma_irq, 0);
8137cde8
BS
1748
1749 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
86d1c388 1750 slavio_irq[3], iommu, &ledma_irq, 1);
8137cde8
BS
1751
1752 if (graphic_depth != 8 && graphic_depth != 24) {
1753 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1754 exit (1);
1755 }
d95d8f1c 1756 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
dc828ca1 1757 graphic_depth);
8137cde8 1758
74ff8d90 1759 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
8137cde8 1760
d95d8f1c 1761 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
8137cde8 1762
c533e0b3 1763 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
993fbfdb 1764 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
8137cde8
BS
1765 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1766 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
c533e0b3
BS
1767 escc_init(hwdef->serial_base, slavio_irq[1],
1768 slavio_irq[1], serial_hds[0], serial_hds[1],
aeeb69c7 1769 ESCC_CLOCK, 1);
8137cde8 1770
b2b6f6ec 1771 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
8137cde8 1772
c227f099 1773 if (hwdef->fd_base != (target_phys_addr_t)-1) {
8137cde8 1774 /* there is zero or one floppy drive */
ce802585 1775 memset(fd, 0, sizeof(fd));
fd8014e1 1776 fd[0] = drive_get(IF_FLOPPY, 0, 0);
c533e0b3 1777 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
2582cfa0 1778 &fdc_tc);
8137cde8
BS
1779 }
1780
1781 if (drive_get_max_bus(IF_SCSI) > 0) {
1782 fprintf(stderr, "qemu: too many SCSI bus\n");
1783 exit(1);
1784 }
1785
cfb9de9c
PB
1786 esp_init(hwdef->esp_base, 2,
1787 espdma_memory_read, espdma_memory_write,
73d74342
BS
1788 espdma, espdma_irq, &esp_reset, &dma_enable);
1789
1790 qdev_connect_gpio_out(espdma, 0, esp_reset);
1791 qdev_connect_gpio_out(espdma, 1, dma_enable);
8137cde8
BS
1792
1793 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1794 RAM_size);
1795
1796 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1797 boot_device, RAM_size, kernel_size, graphic_width,
1798 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1799 "Sun4c");
1800
1801 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1802 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1803 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1804 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
513f789f
BS
1805 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1806 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1807 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1808 if (kernel_cmdline) {
1809 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
3c178e72 1810 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
6bb4ca57
BS
1811 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1812 (uint8_t*)strdup(kernel_cmdline),
1813 strlen(kernel_cmdline) + 1);
513f789f
BS
1814 } else {
1815 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1816 }
1817 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1818 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1819 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1820 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
8137cde8
BS
1821}
1822
1823/* SPARCstation 2 hardware initialisation */
c227f099 1824static void ss2_init(ram_addr_t RAM_size,
3023f332 1825 const char *boot_device,
8137cde8
BS
1826 const char *kernel_filename, const char *kernel_cmdline,
1827 const char *initrd_filename, const char *cpu_model)
1828{
3023f332 1829 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
8137cde8
BS
1830 kernel_cmdline, initrd_filename, cpu_model);
1831}
1832
f80f9ec9 1833static QEMUMachine ss2_machine = {
8137cde8
BS
1834 .name = "SS-2",
1835 .desc = "Sun4c platform, SPARCstation 2",
1836 .init = ss2_init,
8137cde8 1837 .use_scsi = 1,
8137cde8 1838};
f80f9ec9 1839
83f7d43a
AF
1840static void sun4m_register_types(void)
1841{
1842 type_register_static(&idreg_info);
1843 type_register_static(&afx_info);
1844 type_register_static(&prom_info);
1845 type_register_static(&ram_info);
1846}
1847
f80f9ec9
AL
1848static void ss2_machine_init(void)
1849{
1850 qemu_register_machine(&ss5_machine);
1851 qemu_register_machine(&ss10_machine);
1852 qemu_register_machine(&ss600mp_machine);
1853 qemu_register_machine(&ss20_machine);
1854 qemu_register_machine(&voyager_machine);
1855 qemu_register_machine(&ss_lx_machine);
1856 qemu_register_machine(&ss4_machine);
1857 qemu_register_machine(&scls_machine);
1858 qemu_register_machine(&sbook_machine);
1859 qemu_register_machine(&ss1000_machine);
1860 qemu_register_machine(&ss2000_machine);
1861 qemu_register_machine(&ss2_machine);
1862}
1863
83f7d43a 1864type_init(sun4m_register_types)
f80f9ec9 1865machine_init(ss2_machine_init);