[mirror_qemu.git] / hw / tcx.c

/*
 * QEMU TCX Frame buffer
 *
 * Copyright (c) 2003-2005 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "console.h"
#include "pixel_ops.h"
#include "sysbus.h"
#include "qdev-addr.h"

#define MAXX 1024
#define MAXY 768
#define TCX_DAC_NREGS 16
#define TCX_THC_NREGS_8  0x081c
#define TCX_THC_NREGS_24 0x1000
#define TCX_TEC_NREGS    0x1000

typedef struct TCXState {
    SysBusDevice busdev;
    target_phys_addr_t addr;
    DisplayState *ds;
    uint8_t *vram;
    uint32_t *vram24, *cplane;
    MemoryRegion vram_mem;
    MemoryRegion vram_8bit;
    MemoryRegion vram_24bit;
    MemoryRegion vram_cplane;
    MemoryRegion dac;
    MemoryRegion tec;
    MemoryRegion thc24;
    MemoryRegion thc8;
    ram_addr_t vram24_offset, cplane_offset;
    uint32_t vram_size;
    uint32_t palette[256];
    uint8_t r[256], g[256], b[256];
    uint16_t width, height, depth;
    uint8_t dac_index, dac_state;
} TCXState;

static void tcx_screen_dump(void *opaque, const char *filename);
static void tcx24_screen_dump(void *opaque, const char *filename);

static void tcx_set_dirty(TCXState *s)
{
    memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
}

static void tcx24_set_dirty(TCXState *s)
{
    memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
    memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
}

static void update_palette_entries(TCXState *s, int start, int end)
{
    int i;
    for(i = start; i < end; i++) {
        switch(ds_get_bits_per_pixel(s->ds)) {
        default:
        case 8:
            s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
            break;
        case 15:
            s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
            break;
        case 16:
            s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
            break;
        case 32:
            if (is_surface_bgr(s->ds->surface))
                s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
            else
                s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
            break;
        }
    }
    if (s->depth == 24) {
        tcx24_set_dirty(s);
    } else {
        tcx_set_dirty(s);
    }
}

static void tcx_draw_line32(TCXState *s1, uint8_t *d,
                            const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint32_t *p = (uint32_t *)d;

    for(x = 0; x < width; x++) {
        val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line16(TCXState *s1, uint8_t *d,
                            const uint8_t *s, int width)
{
    int x;
    uint8_t val;
    uint16_t *p = (uint16_t *)d;

    for(x = 0; x < width; x++) {
        val = *s++;
        *p++ = s1->palette[val];
    }
}

static void tcx_draw_line8(TCXState *s1, uint8_t *d,
                           const uint8_t *s, int width)
{
    int x;
    uint8_t val;

    for(x = 0; x < width; x++) {
        val = *s++;
        *d++ = s1->palette[val];
    }
}

/*
  XXX Could be much more optimal:
  * detect if line/page/whole screen is in 24 bit mode
  * if destination is also BGR, use memcpy
  */
static inline void tcx24_draw_line32(TCXState *s1, uint8_t *d,
                                     const uint8_t *s, int width,
                                     const uint32_t *cplane,
                                     const uint32_t *s24)
{
    int x, bgr, r, g, b;
    uint8_t val, *p8;
    uint32_t *p = (uint32_t *)d;
    uint32_t dval;

    bgr = is_surface_bgr(s1->ds->surface);
    for(x = 0; x < width; x++, s++, s24++) {
        if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
            // 24-bit direct, BGR order
            p8 = (uint8_t *)s24;
            p8++;
            b = *p8++;
            g = *p8++;
            r = *p8;
            if (bgr)
                dval = rgb_to_pixel32bgr(r, g, b);
            else
                dval = rgb_to_pixel32(r, g, b);
        } else {
            val = *s;
            dval = s1->palette[val];
        }
        *p++ = dval;
    }
}

static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
                              ram_addr_t cpage)
{
    int ret;
    unsigned int off;

    ret = memory_region_get_dirty(&s->vram_mem, page, DIRTY_MEMORY_VGA);
    for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
        ret |= memory_region_get_dirty(&s->vram_mem, page24 + off,
                                       DIRTY_MEMORY_VGA);
        ret |= memory_region_get_dirty(&s->vram_mem, cpage + off,
                                       DIRTY_MEMORY_VGA);
    }
    return ret;
}

static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
                               ram_addr_t page_max, ram_addr_t page24,
                              ram_addr_t cpage)
{
    memory_region_reset_dirty(&ts->vram_mem,
                              page_min, page_max + TARGET_PAGE_SIZE,
                              DIRTY_MEMORY_VGA);
    memory_region_reset_dirty(&ts->vram_mem,
                              page24 + page_min * 4,
                              page24 + page_max * 4 + TARGET_PAGE_SIZE,
                              DIRTY_MEMORY_VGA);
    memory_region_reset_dirty(&ts->vram_mem,
                              cpage + page_min * 4,
                              cpage + page_max * 4 + TARGET_PAGE_SIZE,
                              DIRTY_MEMORY_VGA);
}

/* Fixed line length 1024 allows us to do nice tricks not possible on
   VGA... */
static void tcx_update_display(void *opaque)
{
    TCXState *ts = opaque;
    ram_addr_t page, page_min, page_max;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    void (*f)(TCXState *s1, uint8_t *dst, const uint8_t *src, int width);

    if (ds_get_bits_per_pixel(ts->ds) == 0)
        return;
    page = 0;
    y_start = -1;
    page_min = -1;
    page_max = 0;
    d = ds_get_data(ts->ds);
    s = ts->vram;
    dd = ds_get_linesize(ts->ds);
    ds = 1024;

    switch (ds_get_bits_per_pixel(ts->ds)) {
    case 32:
        f = tcx_draw_line32;
        break;
    case 15:
    case 16:
        f = tcx_draw_line16;
        break;
    default:
    case 8:
        f = tcx_draw_line8;
        break;
    case 0:
        return;
    }

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
        if (memory_region_get_dirty(&ts->vram_mem, page, DIRTY_MEMORY_VGA)) {
            if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
            f(ts, d, s, ts->width);
            d += dd;
            s += ds;
        } else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_update(ts->ds, 0, y_start,
                           ts->width, y - y_start);
                y_start = -1;
            }
            d += dd * 4;
            s += ds * 4;
        }
    }
    if (y_start >= 0) {
        /* flush to display */
        dpy_update(ts->ds, 0, y_start,
                   ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_max >= page_min) {
        memory_region_reset_dirty(&ts->vram_mem,
                                  page_min, page_max + TARGET_PAGE_SIZE,
                                  DIRTY_MEMORY_VGA);
    }
}

static void tcx24_update_display(void *opaque)
{
    TCXState *ts = opaque;
    ram_addr_t page, page_min, page_max, cpage, page24;
    int y, y_start, dd, ds;
    uint8_t *d, *s;
    uint32_t *cptr, *s24;

    if (ds_get_bits_per_pixel(ts->ds) != 32)
            return;
    page = 0;
    page24 = ts->vram24_offset;
    cpage = ts->cplane_offset;
    y_start = -1;
    page_min = -1;
    page_max = 0;
    d = ds_get_data(ts->ds);
    s = ts->vram;
    s24 = ts->vram24;
    cptr = ts->cplane;
    dd = ds_get_linesize(ts->ds);
    ds = 1024;

    for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
            page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
        if (check_dirty(ts, page, page24, cpage)) {
            if (y_start < 0)
                y_start = y;
            if (page < page_min)
                page_min = page;
            if (page > page_max)
                page_max = page;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
            tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
            d += dd;
            s += ds;
            cptr += ds;
            s24 += ds;
        } else {
            if (y_start >= 0) {
                /* flush to display */
                dpy_update(ts->ds, 0, y_start,
                           ts->width, y - y_start);
                y_start = -1;
            }
            d += dd * 4;
            s += ds * 4;
            cptr += ds * 4;
            s24 += ds * 4;
        }
    }
    if (y_start >= 0) {
        /* flush to display */
        dpy_update(ts->ds, 0, y_start,
                   ts->width, y - y_start);
    }
    /* reset modified pages */
    if (page_max >= page_min) {
        reset_dirty(ts, page_min, page_max, page24, cpage);
    }
}

static void tcx_invalidate_display(void *opaque)
{
    TCXState *s = opaque;

    tcx_set_dirty(s);
    qemu_console_resize(s->ds, s->width, s->height);
}

static void tcx24_invalidate_display(void *opaque)
{
    TCXState *s = opaque;

    tcx_set_dirty(s);
    tcx24_set_dirty(s);
    qemu_console_resize(s->ds, s->width, s->height);
}

static int vmstate_tcx_post_load(void *opaque, int version_id)
{
    TCXState *s = opaque;

    update_palette_entries(s, 0, 256);
    if (s->depth == 24) {
        tcx24_set_dirty(s);
    } else {
        tcx_set_dirty(s);
    }

    return 0;
}

static const VMStateDescription vmstate_tcx = {
    .name ="tcx",
    .version_id = 4,
    .minimum_version_id = 4,
    .minimum_version_id_old = 4,
    .post_load = vmstate_tcx_post_load,
    .fields      = (VMStateField []) {
        VMSTATE_UINT16(height, TCXState),
        VMSTATE_UINT16(width, TCXState),
        VMSTATE_UINT16(depth, TCXState),
        VMSTATE_BUFFER(r, TCXState),
        VMSTATE_BUFFER(g, TCXState),
        VMSTATE_BUFFER(b, TCXState),
        VMSTATE_UINT8(dac_index, TCXState),
        VMSTATE_UINT8(dac_state, TCXState),
        VMSTATE_END_OF_LIST()
    }
};

static void tcx_reset(DeviceState *d)
{
    TCXState *s = container_of(d, TCXState, busdev.qdev);

    /* Initialize palette */
    memset(s->r, 0, 256);
    memset(s->g, 0, 256);
    memset(s->b, 0, 256);
    s->r[255] = s->g[255] = s->b[255] = 255;
    update_palette_entries(s, 0, 256);
    memset(s->vram, 0, MAXX*MAXY);
    memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
                              DIRTY_MEMORY_VGA);
    s->dac_index = 0;
    s->dac_state = 0;
}

static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
                              unsigned size)
{
    return 0;
}

static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
                           unsigned size)
{
    TCXState *s = opaque;

    switch (addr) {
    case 0:
        s->dac_index = val >> 24;
        s->dac_state = 0;
        break;
    case 4:
        switch (s->dac_state) {
        case 0:
            s->r[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_state++;
            break;
        case 1:
            s->g[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_state++;
            break;
        case 2:
            s->b[s->dac_index] = val >> 24;
            update_palette_entries(s, s->dac_index, s->dac_index + 1);
            s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
        default:
            s->dac_state = 0;
            break;
        }
        break;
    default:
        break;
    }
    return;
}

static const MemoryRegionOps tcx_dac_ops = {
    .read = tcx_dac_readl,
    .write = tcx_dac_writel,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
                            unsigned size)
{
    return 0;
}

static void dummy_writel(void *opaque, target_phys_addr_t addr,
                         uint64_t val, unsigned size)
{
}

static const MemoryRegionOps dummy_ops = {
    .read = dummy_readl,
    .write = dummy_writel,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static int tcx_init1(SysBusDevice *dev)
{
    TCXState *s = FROM_SYSBUS(TCXState, dev);
    ram_addr_t vram_offset = 0;
    int size;
    uint8_t *vram_base;

    memory_region_init_ram(&s->vram_mem, "tcx.vram",
                           s->vram_size * (1 + 4 + 4));
    vmstate_register_ram_global(&s->vram_mem);
    vram_base = memory_region_get_ram_ptr(&s->vram_mem);

    /* 8-bit plane */
    s->vram = vram_base;
    size = s->vram_size;
    memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
                             &s->vram_mem, vram_offset, size);
    sysbus_init_mmio(dev, &s->vram_8bit);
    vram_offset += size;
    vram_base += size;

    /* DAC */
    memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
    sysbus_init_mmio(dev, &s->dac);

    /* TEC (dummy) */
    memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
    sysbus_init_mmio(dev, &s->tec);
    /* THC: NetBSD writes here even with 8-bit display: dummy */
    memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
                          TCX_THC_NREGS_24);
    sysbus_init_mmio(dev, &s->thc24);

    if (s->depth == 24) {
        /* 24-bit plane */
        size = s->vram_size * 4;
        s->vram24 = (uint32_t *)vram_base;
        s->vram24_offset = vram_offset;
        memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
                                 &s->vram_mem, vram_offset, size);
        sysbus_init_mmio(dev, &s->vram_24bit);
        vram_offset += size;
        vram_base += size;

        /* Control plane */
        size = s->vram_size * 4;
        s->cplane = (uint32_t *)vram_base;
        s->cplane_offset = vram_offset;
        memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
                                 &s->vram_mem, vram_offset, size);
        sysbus_init_mmio(dev, &s->vram_cplane);

        s->ds = graphic_console_init(tcx24_update_display,
                                     tcx24_invalidate_display,
                                     tcx24_screen_dump, NULL, s);
    } else {
        /* THC 8 bit (dummy) */
        memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
                              TCX_THC_NREGS_8);
        sysbus_init_mmio(dev, &s->thc8);

        s->ds = graphic_console_init(tcx_update_display,
                                     tcx_invalidate_display,
                                     tcx_screen_dump, NULL, s);
    }

    qemu_console_resize(s->ds, s->width, s->height);
    return 0;
}

static void tcx_screen_dump(void *opaque, const char *filename)
{
    TCXState *s = opaque;
    FILE *f;
    uint8_t *d, *d1, v;
    int y, x;

    f = fopen(filename, "wb");
    if (!f)
        return;
    fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
    d1 = s->vram;
    for(y = 0; y < s->height; y++) {
        d = d1;
        for(x = 0; x < s->width; x++) {
            v = *d;
            fputc(s->r[v], f);
            fputc(s->g[v], f);
            fputc(s->b[v], f);
            d++;
        }
        d1 += MAXX;
    }
    fclose(f);
    return;
}

static void tcx24_screen_dump(void *opaque, const char *filename)
{
    TCXState *s = opaque;
    FILE *f;
    uint8_t *d, *d1, v;
    uint32_t *s24, *cptr, dval;
    int y, x;

    f = fopen(filename, "wb");
    if (!f)
        return;
    fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
    d1 = s->vram;
    s24 = s->vram24;
    cptr = s->cplane;
    for(y = 0; y < s->height; y++) {
        d = d1;
        for(x = 0; x < s->width; x++, d++, s24++) {
            if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
                dval = *s24 & 0x00ffffff;
                fputc((dval >> 16) & 0xff, f);
                fputc((dval >> 8) & 0xff, f);
                fputc(dval & 0xff, f);
            } else {
                v = *d;
                fputc(s->r[v], f);
                fputc(s->g[v], f);
                fputc(s->b[v], f);
            }
        }
        d1 += MAXX;
    }
    fclose(f);
    return;
}

static Property tcx_properties[] = {
    DEFINE_PROP_TADDR("addr",      TCXState, addr,      -1),
    DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
    DEFINE_PROP_UINT16("width",    TCXState, width,     -1),
    DEFINE_PROP_UINT16("height",   TCXState, height,    -1),
    DEFINE_PROP_UINT16("depth",    TCXState, depth,     -1),
    DEFINE_PROP_END_OF_LIST(),
};

static void tcx_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = tcx_init1;
}

static DeviceInfo tcx_info = {
    .name = "SUNW,tcx",
    .size = sizeof(TCXState),
    .reset = tcx_reset,
    .vmsd = &vmstate_tcx,
    .props = tcx_properties,
    .class_init = tcx_class_init,
};

static void tcx_register_devices(void)
{
    sysbus_register_withprop(&tcx_info);
}

device_init(tcx_register_devices)
Commit	Line	Data
420557e8	1	/*
6f7e9aec	2	* QEMU TCX Frame buffer
5fafdf24	3	*
6f7e9aec	4	* Copyright (c) 2003-2005 Fabrice Bellard
5fafdf24	5	*
420557e8 FB	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
f40070c3	24
87ecb68b	25	#include "console.h"
94470844	26	#include "pixel_ops.h"
f40070c3	27	#include "sysbus.h"
ee6847d1	28	#include "qdev-addr.h"
420557e8	29
420557e8 FB	30	#define MAXX 1024
420557e8 FB	31	#define MAXY 768
6f7e9aec	32	#define TCX_DAC_NREGS 16
8508b89e BS	33	#define TCX_THC_NREGS_8 0x081c
	34	#define TCX_THC_NREGS_24 0x1000
	35	#define TCX_TEC_NREGS 0x1000
420557e8	36
420557e8	37	typedef struct TCXState {
f40070c3	38	SysBusDevice busdev;
c227f099	39	target_phys_addr_t addr;
420557e8	40	DisplayState *ds;
8d5f07fa	41	uint8_t *vram;
eee0b836	42	uint32_t vram24, cplane;
d08151bf AK	43	MemoryRegion vram_mem;
	44	MemoryRegion vram_8bit;
	45	MemoryRegion vram_24bit;
	46	MemoryRegion vram_cplane;
	47	MemoryRegion dac;
	48	MemoryRegion tec;
	49	MemoryRegion thc24;
	50	MemoryRegion thc8;
	51	ram_addr_t vram24_offset, cplane_offset;
ee6847d1	52	uint32_t vram_size;
21206a10	53	uint32_t palette[256];
427a66c3 BS	54	uint8_t r[256], g[256], b[256];
427a66c3 BS	55	uint16_t width, height, depth;
6f7e9aec	56	uint8_t dac_index, dac_state;
420557e8 FB	57	} TCXState;
420557e8 FB	58
95219897	59	static void tcx_screen_dump(void opaque, const char filename);
eee0b836	60	static void tcx24_screen_dump(void opaque, const char filename);
d3ffcafe BS	61
	62	static void tcx_set_dirty(TCXState *s)
	63	{
fd4aa979	64	memory_region_set_dirty(&s->vram_mem, 0, MAXX * MAXY);
d3ffcafe BS	65	}
	66
	67	static void tcx24_set_dirty(TCXState *s)
	68	{
fd4aa979 BS	69	memory_region_set_dirty(&s->vram_mem, s->vram24_offset, MAXX * MAXY * 4);
fd4aa979 BS	70	memory_region_set_dirty(&s->vram_mem, s->cplane_offset, MAXX * MAXY * 4);
d3ffcafe	71	}
95219897	72
21206a10 FB	73	static void update_palette_entries(TCXState *s, int start, int end)
	74	{
	75	int i;
	76	for(i = start; i < end; i++) {
0e1f5a0c	77	switch(ds_get_bits_per_pixel(s->ds)) {
21206a10 FB	78	default:
	79	case 8:
	80	s->palette[i] = rgb_to_pixel8(s->r[i], s->g[i], s->b[i]);
	81	break;
	82	case 15:
8927bcfd	83	s->palette[i] = rgb_to_pixel15(s->r[i], s->g[i], s->b[i]);
21206a10 FB	84	break;
21206a10 FB	85	case 16:
8927bcfd	86	s->palette[i] = rgb_to_pixel16(s->r[i], s->g[i], s->b[i]);
21206a10 FB	87	break;
21206a10 FB	88	case 32:
7b5d76da AL	89	if (is_surface_bgr(s->ds->surface))
	90	s->palette[i] = rgb_to_pixel32bgr(s->r[i], s->g[i], s->b[i]);
	91	else
	92	s->palette[i] = rgb_to_pixel32(s->r[i], s->g[i], s->b[i]);
21206a10 FB	93	break;
	94	}
	95	}
d3ffcafe BS	96	if (s->depth == 24) {
	97	tcx24_set_dirty(s);
	98	} else {
	99	tcx_set_dirty(s);
	100	}
21206a10 FB	101	}
21206a10 FB	102
5fafdf24	103	static void tcx_draw_line32(TCXState s1, uint8_t d,
f930d07e	104	const uint8_t *s, int width)
420557e8	105	{
e80cfcfc FB	106	int x;
e80cfcfc FB	107	uint8_t val;
8bdc2159	108	uint32_t p = (uint32_t )d;
e80cfcfc FB	109
e80cfcfc FB	110	for(x = 0; x < width; x++) {
f930d07e	111	val = *s++;
8bdc2159	112	*p++ = s1->palette[val];
e80cfcfc	113	}
420557e8 FB	114	}
420557e8 FB	115
5fafdf24	116	static void tcx_draw_line16(TCXState s1, uint8_t d,
f930d07e	117	const uint8_t *s, int width)
e80cfcfc FB	118	{
	119	int x;
	120	uint8_t val;
8bdc2159	121	uint16_t p = (uint16_t )d;
8d5f07fa	122
e80cfcfc	123	for(x = 0; x < width; x++) {
f930d07e	124	val = *s++;
8bdc2159	125	*p++ = s1->palette[val];
e80cfcfc FB	126	}
	127	}
	128
5fafdf24	129	static void tcx_draw_line8(TCXState s1, uint8_t d,
f930d07e	130	const uint8_t *s, int width)
420557e8	131	{
e80cfcfc FB	132	int x;
	133	uint8_t val;
	134
	135	for(x = 0; x < width; x++) {
f930d07e	136	val = *s++;
21206a10	137	*d++ = s1->palette[val];
420557e8	138	}
420557e8 FB	139	}
420557e8 FB	140
688ea2eb BS	141	/*
	142	XXX Could be much more optimal:
	143	* detect if line/page/whole screen is in 24 bit mode
	144	* if destination is also BGR, use memcpy
	145	*/
eee0b836 BS	146	static inline void tcx24_draw_line32(TCXState s1, uint8_t d,
	147	const uint8_t *s, int width,
	148	const uint32_t *cplane,
	149	const uint32_t *s24)
	150	{
7b5d76da	151	int x, bgr, r, g, b;
688ea2eb	152	uint8_t val, *p8;
eee0b836 BS	153	uint32_t p = (uint32_t )d;
	154	uint32_t dval;
	155
7b5d76da	156	bgr = is_surface_bgr(s1->ds->surface);
eee0b836	157	for(x = 0; x < width; x++, s++, s24++) {
688ea2eb BS	158	if ((be32_to_cpu(*cplane++) & 0xff000000) == 0x03000000) {
	159	// 24-bit direct, BGR order
	160	p8 = (uint8_t *)s24;
	161	p8++;
	162	b = *p8++;
	163	g = *p8++;
f7e683b8	164	r = *p8;
7b5d76da AL	165	if (bgr)
	166	dval = rgb_to_pixel32bgr(r, g, b);
	167	else
	168	dval = rgb_to_pixel32(r, g, b);
eee0b836 BS	169	} else {
	170	val = *s;
	171	dval = s1->palette[val];
	172	}
	173	*p++ = dval;
	174	}
	175	}
	176
d08151bf	177	static inline int check_dirty(TCXState *s, ram_addr_t page, ram_addr_t page24,
c227f099	178	ram_addr_t cpage)
eee0b836 BS	179	{
	180	int ret;
	181	unsigned int off;
	182
d08151bf	183	ret = memory_region_get_dirty(&s->vram_mem, page, DIRTY_MEMORY_VGA);
eee0b836	184	for (off = 0; off < TARGET_PAGE_SIZE * 4; off += TARGET_PAGE_SIZE) {
d08151bf AK	185	ret \|= memory_region_get_dirty(&s->vram_mem, page24 + off,
	186	DIRTY_MEMORY_VGA);
	187	ret \|= memory_region_get_dirty(&s->vram_mem, cpage + off,
	188	DIRTY_MEMORY_VGA);
eee0b836 BS	189	}
	190	return ret;
	191	}
	192
c227f099 AL	193	static inline void reset_dirty(TCXState *ts, ram_addr_t page_min,
	194	ram_addr_t page_max, ram_addr_t page24,
	195	ram_addr_t cpage)
eee0b836	196	{
d08151bf AK	197	memory_region_reset_dirty(&ts->vram_mem,
	198	page_min, page_max + TARGET_PAGE_SIZE,
	199	DIRTY_MEMORY_VGA);
	200	memory_region_reset_dirty(&ts->vram_mem,
	201	page24 + page_min * 4,
	202	page24 + page_max * 4 + TARGET_PAGE_SIZE,
	203	DIRTY_MEMORY_VGA);
	204	memory_region_reset_dirty(&ts->vram_mem,
	205	cpage + page_min * 4,
	206	cpage + page_max * 4 + TARGET_PAGE_SIZE,
	207	DIRTY_MEMORY_VGA);
eee0b836 BS	208	}
eee0b836 BS	209
e80cfcfc FB	210	/* Fixed line length 1024 allows us to do nice tricks not possible on
e80cfcfc FB	211	VGA... */
95219897	212	static void tcx_update_display(void *opaque)
420557e8	213	{
e80cfcfc	214	TCXState *ts = opaque;
c227f099	215	ram_addr_t page, page_min, page_max;
550be127	216	int y, y_start, dd, ds;
e80cfcfc	217	uint8_t d, s;
b3ceef24	218	void (f)(TCXState s1, uint8_t dst, const uint8_t src, int width);
e80cfcfc	219
0e1f5a0c	220	if (ds_get_bits_per_pixel(ts->ds) == 0)
f930d07e	221	return;
d08151bf	222	page = 0;
e80cfcfc	223	y_start = -1;
c0c440f3	224	page_min = -1;
550be127	225	page_max = 0;
0e1f5a0c	226	d = ds_get_data(ts->ds);
6f7e9aec	227	s = ts->vram;
0e1f5a0c	228	dd = ds_get_linesize(ts->ds);
e80cfcfc FB	229	ds = 1024;
e80cfcfc FB	230
0e1f5a0c	231	switch (ds_get_bits_per_pixel(ts->ds)) {
e80cfcfc	232	case 32:
f930d07e BS	233	f = tcx_draw_line32;
f930d07e BS	234	break;
21206a10 FB	235	case 15:
21206a10 FB	236	case 16:
f930d07e BS	237	f = tcx_draw_line16;
f930d07e BS	238	break;
e80cfcfc FB	239	default:
e80cfcfc FB	240	case 8:
f930d07e BS	241	f = tcx_draw_line8;
f930d07e BS	242	break;
e80cfcfc	243	case 0:
f930d07e	244	return;
e80cfcfc	245	}
3b46e624	246
6f7e9aec	247	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE) {
d08151bf	248	if (memory_region_get_dirty(&ts->vram_mem, page, DIRTY_MEMORY_VGA)) {
f930d07e	249	if (y_start < 0)
e80cfcfc FB	250	y_start = y;
	251	if (page < page_min)
	252	page_min = page;
	253	if (page > page_max)
	254	page_max = page;
f930d07e BS	255	f(ts, d, s, ts->width);
	256	d += dd;
	257	s += ds;
	258	f(ts, d, s, ts->width);
	259	d += dd;
	260	s += ds;
	261	f(ts, d, s, ts->width);
	262	d += dd;
	263	s += ds;
	264	f(ts, d, s, ts->width);
	265	d += dd;
	266	s += ds;
	267	} else {
e80cfcfc FB	268	if (y_start >= 0) {
e80cfcfc FB	269	/* flush to display */
5fafdf24	270	dpy_update(ts->ds, 0, y_start,
6f7e9aec	271	ts->width, y - y_start);
e80cfcfc FB	272	y_start = -1;
e80cfcfc FB	273	}
f930d07e BS	274	d += dd * 4;
	275	s += ds * 4;
	276	}
e80cfcfc FB	277	}
e80cfcfc FB	278	if (y_start >= 0) {
f930d07e BS	279	/* flush to display */
	280	dpy_update(ts->ds, 0, y_start,
	281	ts->width, y - y_start);
e80cfcfc FB	282	}
e80cfcfc FB	283	/* reset modified pages */
c0c440f3	284	if (page_max >= page_min) {
d08151bf AK	285	memory_region_reset_dirty(&ts->vram_mem,
	286	page_min, page_max + TARGET_PAGE_SIZE,
	287	DIRTY_MEMORY_VGA);
e80cfcfc	288	}
420557e8 FB	289	}
420557e8 FB	290
eee0b836 BS	291	static void tcx24_update_display(void *opaque)
	292	{
	293	TCXState *ts = opaque;
c227f099	294	ram_addr_t page, page_min, page_max, cpage, page24;
eee0b836 BS	295	int y, y_start, dd, ds;
	296	uint8_t d, s;
	297	uint32_t cptr, s24;
	298
0e1f5a0c	299	if (ds_get_bits_per_pixel(ts->ds) != 32)
eee0b836	300	return;
d08151bf	301	page = 0;
eee0b836 BS	302	page24 = ts->vram24_offset;
	303	cpage = ts->cplane_offset;
	304	y_start = -1;
c0c440f3	305	page_min = -1;
eee0b836	306	page_max = 0;
0e1f5a0c	307	d = ds_get_data(ts->ds);
eee0b836 BS	308	s = ts->vram;
	309	s24 = ts->vram24;
	310	cptr = ts->cplane;
0e1f5a0c	311	dd = ds_get_linesize(ts->ds);
eee0b836 BS	312	ds = 1024;
	313
	314	for(y = 0; y < ts->height; y += 4, page += TARGET_PAGE_SIZE,
	315	page24 += TARGET_PAGE_SIZE, cpage += TARGET_PAGE_SIZE) {
d08151bf	316	if (check_dirty(ts, page, page24, cpage)) {
eee0b836 BS	317	if (y_start < 0)
	318	y_start = y;
	319	if (page < page_min)
	320	page_min = page;
	321	if (page > page_max)
	322	page_max = page;
	323	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	324	d += dd;
	325	s += ds;
	326	cptr += ds;
	327	s24 += ds;
	328	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	329	d += dd;
	330	s += ds;
	331	cptr += ds;
	332	s24 += ds;
	333	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	334	d += dd;
	335	s += ds;
	336	cptr += ds;
	337	s24 += ds;
	338	tcx24_draw_line32(ts, d, s, ts->width, cptr, s24);
	339	d += dd;
	340	s += ds;
	341	cptr += ds;
	342	s24 += ds;
	343	} else {
	344	if (y_start >= 0) {
	345	/* flush to display */
	346	dpy_update(ts->ds, 0, y_start,
	347	ts->width, y - y_start);
	348	y_start = -1;
	349	}
	350	d += dd * 4;
	351	s += ds * 4;
	352	cptr += ds * 4;
	353	s24 += ds * 4;
	354	}
	355	}
	356	if (y_start >= 0) {
	357	/* flush to display */
	358	dpy_update(ts->ds, 0, y_start,
	359	ts->width, y - y_start);
	360	}
	361	/* reset modified pages */
c0c440f3	362	if (page_max >= page_min) {
eee0b836 BS	363	reset_dirty(ts, page_min, page_max, page24, cpage);
	364	}
	365	}
	366
95219897	367	static void tcx_invalidate_display(void *opaque)
420557e8	368	{
e80cfcfc	369	TCXState *s = opaque;
e80cfcfc	370
d3ffcafe BS	371	tcx_set_dirty(s);
d3ffcafe BS	372	qemu_console_resize(s->ds, s->width, s->height);
420557e8 FB	373	}
420557e8 FB	374
eee0b836 BS	375	static void tcx24_invalidate_display(void *opaque)
	376	{
	377	TCXState *s = opaque;
eee0b836	378
d3ffcafe BS	379	tcx_set_dirty(s);
	380	tcx24_set_dirty(s);
	381	qemu_console_resize(s->ds, s->width, s->height);
eee0b836 BS	382	}
eee0b836 BS	383
e59fb374	384	static int vmstate_tcx_post_load(void *opaque, int version_id)
420557e8 FB	385	{
420557e8 FB	386	TCXState *s = opaque;
3b46e624	387
21206a10	388	update_palette_entries(s, 0, 256);
d3ffcafe BS	389	if (s->depth == 24) {
	390	tcx24_set_dirty(s);
	391	} else {
	392	tcx_set_dirty(s);
	393	}
5425a216	394
e80cfcfc	395	return 0;
420557e8 FB	396	}
420557e8 FB	397
c0c41a4b BS	398	static const VMStateDescription vmstate_tcx = {
	399	.name ="tcx",
	400	.version_id = 4,
	401	.minimum_version_id = 4,
	402	.minimum_version_id_old = 4,
752ff2fa	403	.post_load = vmstate_tcx_post_load,
c0c41a4b BS	404	.fields = (VMStateField []) {
	405	VMSTATE_UINT16(height, TCXState),
	406	VMSTATE_UINT16(width, TCXState),
	407	VMSTATE_UINT16(depth, TCXState),
	408	VMSTATE_BUFFER(r, TCXState),
	409	VMSTATE_BUFFER(g, TCXState),
	410	VMSTATE_BUFFER(b, TCXState),
	411	VMSTATE_UINT8(dac_index, TCXState),
	412	VMSTATE_UINT8(dac_state, TCXState),
	413	VMSTATE_END_OF_LIST()
	414	}
	415	};
	416
7f23f812	417	static void tcx_reset(DeviceState *d)
420557e8	418	{
7f23f812	419	TCXState *s = container_of(d, TCXState, busdev.qdev);
e80cfcfc FB	420
	421	/* Initialize palette */
	422	memset(s->r, 0, 256);
	423	memset(s->g, 0, 256);
	424	memset(s->b, 0, 256);
	425	s->r[255] = s->g[255] = s->b[255] = 255;
21206a10	426	update_palette_entries(s, 0, 256);
e80cfcfc	427	memset(s->vram, 0, MAXX*MAXY);
d08151bf AK	428	memory_region_reset_dirty(&s->vram_mem, 0, MAXX * MAXY * (1 + 4 + 4),
d08151bf AK	429	DIRTY_MEMORY_VGA);
6f7e9aec FB	430	s->dac_index = 0;
	431	s->dac_state = 0;
	432	}
	433
d08151bf AK	434	static uint64_t tcx_dac_readl(void *opaque, target_phys_addr_t addr,
d08151bf AK	435	unsigned size)
6f7e9aec FB	436	{
	437	return 0;
	438	}
	439
d08151bf AK	440	static void tcx_dac_writel(void *opaque, target_phys_addr_t addr, uint64_t val,
d08151bf AK	441	unsigned size)
6f7e9aec FB	442	{
6f7e9aec FB	443	TCXState *s = opaque;
6f7e9aec	444
e64d7d59	445	switch (addr) {
6f7e9aec	446	case 0:
f930d07e BS	447	s->dac_index = val >> 24;
	448	s->dac_state = 0;
	449	break;
e64d7d59	450	case 4:
f930d07e BS	451	switch (s->dac_state) {
	452	case 0:
	453	s->r[s->dac_index] = val >> 24;
21206a10	454	update_palette_entries(s, s->dac_index, s->dac_index + 1);
f930d07e BS	455	s->dac_state++;
	456	break;
	457	case 1:
	458	s->g[s->dac_index] = val >> 24;
21206a10	459	update_palette_entries(s, s->dac_index, s->dac_index + 1);
f930d07e BS	460	s->dac_state++;
	461	break;
	462	case 2:
	463	s->b[s->dac_index] = val >> 24;
21206a10	464	update_palette_entries(s, s->dac_index, s->dac_index + 1);
5c8cdbf8	465	s->dac_index = (s->dac_index + 1) & 255; // Index autoincrement
f930d07e BS	466	default:
	467	s->dac_state = 0;
	468	break;
	469	}
	470	break;
6f7e9aec	471	default:
f930d07e	472	break;
6f7e9aec FB	473	}
6f7e9aec FB	474	return;
420557e8 FB	475	}
420557e8 FB	476
d08151bf AK	477	static const MemoryRegionOps tcx_dac_ops = {
	478	.read = tcx_dac_readl,
	479	.write = tcx_dac_writel,
	480	.endianness = DEVICE_NATIVE_ENDIAN,
	481	.valid = {
	482	.min_access_size = 4,
	483	.max_access_size = 4,
	484	},
6f7e9aec FB	485	};
6f7e9aec FB	486
d08151bf AK	487	static uint64_t dummy_readl(void *opaque, target_phys_addr_t addr,
d08151bf AK	488	unsigned size)
8508b89e BS	489	{
	490	return 0;
	491	}
	492
d08151bf AK	493	static void dummy_writel(void *opaque, target_phys_addr_t addr,
d08151bf AK	494	uint64_t val, unsigned size)
8508b89e BS	495	{
	496	}
	497
d08151bf AK	498	static const MemoryRegionOps dummy_ops = {
	499	.read = dummy_readl,
	500	.write = dummy_writel,
	501	.endianness = DEVICE_NATIVE_ENDIAN,
	502	.valid = {
	503	.min_access_size = 4,
	504	.max_access_size = 4,
	505	},
8508b89e BS	506	};
8508b89e BS	507
81a322d4	508	static int tcx_init1(SysBusDevice *dev)
f40070c3 BS	509	{
f40070c3 BS	510	TCXState *s = FROM_SYSBUS(TCXState, dev);
d08151bf	511	ram_addr_t vram_offset = 0;
ee6847d1	512	int size;
dc828ca1 PB	513	uint8_t *vram_base;
dc828ca1 PB	514
c5705a77	515	memory_region_init_ram(&s->vram_mem, "tcx.vram",
d08151bf	516	s->vram_size * (1 + 4 + 4));
c5705a77	517	vmstate_register_ram_global(&s->vram_mem);
d08151bf	518	vram_base = memory_region_get_ram_ptr(&s->vram_mem);
eee0b836	519
f40070c3	520	/* 8-bit plane */
eee0b836	521	s->vram = vram_base;
ee6847d1	522	size = s->vram_size;
d08151bf AK	523	memory_region_init_alias(&s->vram_8bit, "tcx.vram.8bit",
d08151bf AK	524	&s->vram_mem, vram_offset, size);
750ecd44	525	sysbus_init_mmio(dev, &s->vram_8bit);
eee0b836 BS	526	vram_offset += size;
eee0b836 BS	527	vram_base += size;
e80cfcfc	528
f40070c3	529	/* DAC */
d08151bf	530	memory_region_init_io(&s->dac, &tcx_dac_ops, s, "tcx.dac", TCX_DAC_NREGS);
750ecd44	531	sysbus_init_mmio(dev, &s->dac);
eee0b836	532
f40070c3	533	/* TEC (dummy) */
d08151bf	534	memory_region_init_io(&s->tec, &dummy_ops, s, "tcx.tec", TCX_TEC_NREGS);
750ecd44	535	sysbus_init_mmio(dev, &s->tec);
f40070c3	536	/* THC: NetBSD writes here even with 8-bit display: dummy */
d08151bf AK	537	memory_region_init_io(&s->thc24, &dummy_ops, s, "tcx.thc24",
d08151bf AK	538	TCX_THC_NREGS_24);
750ecd44	539	sysbus_init_mmio(dev, &s->thc24);
f40070c3 BS	540
	541	if (s->depth == 24) {
	542	/* 24-bit plane */
ee6847d1	543	size = s->vram_size * 4;
eee0b836 BS	544	s->vram24 = (uint32_t *)vram_base;
eee0b836 BS	545	s->vram24_offset = vram_offset;
d08151bf AK	546	memory_region_init_alias(&s->vram_24bit, "tcx.vram.24bit",
d08151bf AK	547	&s->vram_mem, vram_offset, size);
750ecd44	548	sysbus_init_mmio(dev, &s->vram_24bit);
eee0b836 BS	549	vram_offset += size;
	550	vram_base += size;
	551
f40070c3	552	/* Control plane */
ee6847d1	553	size = s->vram_size * 4;
eee0b836 BS	554	s->cplane = (uint32_t *)vram_base;
eee0b836 BS	555	s->cplane_offset = vram_offset;
d08151bf AK	556	memory_region_init_alias(&s->vram_cplane, "tcx.vram.cplane",
d08151bf AK	557	&s->vram_mem, vram_offset, size);
750ecd44	558	sysbus_init_mmio(dev, &s->vram_cplane);
f40070c3	559
3023f332 AL	560	s->ds = graphic_console_init(tcx24_update_display,
	561	tcx24_invalidate_display,
	562	tcx24_screen_dump, NULL, s);
eee0b836	563	} else {
f40070c3	564	/* THC 8 bit (dummy) */
d08151bf AK	565	memory_region_init_io(&s->thc8, &dummy_ops, s, "tcx.thc8",
d08151bf AK	566	TCX_THC_NREGS_8);
750ecd44	567	sysbus_init_mmio(dev, &s->thc8);
f40070c3	568
3023f332 AL	569	s->ds = graphic_console_init(tcx_update_display,
	570	tcx_invalidate_display,
	571	tcx_screen_dump, NULL, s);
eee0b836	572	}
e80cfcfc	573
f40070c3	574	qemu_console_resize(s->ds, s->width, s->height);
81a322d4	575	return 0;
420557e8 FB	576	}
420557e8 FB	577
95219897	578	static void tcx_screen_dump(void opaque, const char filename)
8d5f07fa	579	{
e80cfcfc	580	TCXState *s = opaque;
8d5f07fa	581	FILE *f;
e80cfcfc	582	uint8_t d, d1, v;
8d5f07fa FB	583	int y, x;
	584
	585	f = fopen(filename, "wb");
	586	if (!f)
e80cfcfc	587	return;
6f7e9aec FB	588	fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	589	d1 = s->vram;
	590	for(y = 0; y < s->height; y++) {
8d5f07fa	591	d = d1;
6f7e9aec	592	for(x = 0; x < s->width; x++) {
8d5f07fa	593	v = *d;
e80cfcfc FB	594	fputc(s->r[v], f);
	595	fputc(s->g[v], f);
	596	fputc(s->b[v], f);
8d5f07fa FB	597	d++;
8d5f07fa FB	598	}
e80cfcfc	599	d1 += MAXX;
8d5f07fa FB	600	}
	601	fclose(f);
	602	return;
	603	}
	604
eee0b836 BS	605	static void tcx24_screen_dump(void opaque, const char filename)
	606	{
	607	TCXState *s = opaque;
	608	FILE *f;
	609	uint8_t d, d1, v;
	610	uint32_t s24, cptr, dval;
	611	int y, x;
8d5f07fa	612
eee0b836 BS	613	f = fopen(filename, "wb");
	614	if (!f)
	615	return;
	616	fprintf(f, "P6\n%d %d\n%d\n", s->width, s->height, 255);
	617	d1 = s->vram;
	618	s24 = s->vram24;
	619	cptr = s->cplane;
	620	for(y = 0; y < s->height; y++) {
	621	d = d1;
	622	for(x = 0; x < s->width; x++, d++, s24++) {
	623	if ((*cptr++ & 0xff000000) == 0x03000000) { // 24-bit direct
	624	dval = *s24 & 0x00ffffff;
	625	fputc((dval >> 16) & 0xff, f);
	626	fputc((dval >> 8) & 0xff, f);
	627	fputc(dval & 0xff, f);
	628	} else {
	629	v = *d;
	630	fputc(s->r[v], f);
	631	fputc(s->g[v], f);
	632	fputc(s->b[v], f);
	633	}
	634	}
	635	d1 += MAXX;
	636	}
	637	fclose(f);
	638	return;
	639	}
f40070c3	640
999e12bb AL	641	static Property tcx_properties[] = {
	642	DEFINE_PROP_TADDR("addr", TCXState, addr, -1),
	643	DEFINE_PROP_HEX32("vram_size", TCXState, vram_size, -1),
	644	DEFINE_PROP_UINT16("width", TCXState, width, -1),
	645	DEFINE_PROP_UINT16("height", TCXState, height, -1),
	646	DEFINE_PROP_UINT16("depth", TCXState, depth, -1),
	647	DEFINE_PROP_END_OF_LIST(),
	648	};
	649
	650	static void tcx_class_init(ObjectClass klass, void data)
	651	{
	652	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	653
	654	k->init = tcx_init1;
	655	}
	656
	657	static DeviceInfo tcx_info = {
	658	.name = "SUNW,tcx",
	659	.size = sizeof(TCXState),
	660	.reset = tcx_reset,
	661	.vmsd = &vmstate_tcx,
	662	.props = tcx_properties,
	663	.class_init = tcx_class_init,
ee6847d1 GH	664	};
ee6847d1 GH	665
f40070c3 BS	666	static void tcx_register_devices(void)
f40070c3 BS	667	{
ee6847d1	668	sysbus_register_withprop(&tcx_info);
f40070c3 BS	669	}
	670
	671	device_init(tcx_register_devices)