[mirror_qemu.git] / hw / timer / allwinner-a10-pit.c

/*
 * Allwinner A10 timer device emulation
 *
 * Copyright (C) 2013 Li Guang
 * Written by Li Guang <lig.fnst@cn.fujitsu.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
 * for more details.
 */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "hw/timer/allwinner-a10-pit.h"
#include "migration/vmstate.h"
#include "qemu/log.h"
#include "qemu/module.h"

static void a10_pit_update_irq(AwA10PITState *s)
{
    int i;

    for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
        qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i)));
    }
}

static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
{
    AwA10PITState *s = AW_A10_PIT(opaque);
    uint8_t index;

    switch (offset) {
    case AW_A10_PIT_TIMER_IRQ_EN:
        return s->irq_enable;
    case AW_A10_PIT_TIMER_IRQ_ST:
        return s->irq_status;
    case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
        index = offset & 0xf0;
        index >>= 4;
        index -= 1;
        switch (offset & 0x0f) {
        case AW_A10_PIT_TIMER_CONTROL:
            return s->control[index];
        case AW_A10_PIT_TIMER_INTERVAL:
            return s->interval[index];
        case AW_A10_PIT_TIMER_COUNT:
            s->count[index] = ptimer_get_count(s->timer[index]);
            return s->count[index];
        default:
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: Bad offset 0x%x\n",  __func__, (int)offset);
            break;
        }
    case AW_A10_PIT_WDOG_CONTROL:
        break;
    case AW_A10_PIT_WDOG_MODE:
        break;
    case AW_A10_PIT_COUNT_LO:
        return s->count_lo;
    case AW_A10_PIT_COUNT_HI:
        return s->count_hi;
    case AW_A10_PIT_COUNT_CTL:
        return s->count_ctl;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
        break;
    }

    return 0;
}

/* Must be called inside a ptimer transaction block for s->timer[index] */
static void a10_pit_set_freq(AwA10PITState *s, int index)
{
    uint32_t prescaler, source, source_freq;

    prescaler = 1 << extract32(s->control[index], 4, 3);
    source = extract32(s->control[index], 2, 2);
    source_freq = s->clk_freq[source];

    if (source_freq) {
        ptimer_set_freq(s->timer[index], source_freq / prescaler);
    } else {
        qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n",
                      __func__, source);
    }
}

static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
                            unsigned size)
{
     AwA10PITState *s = AW_A10_PIT(opaque);
     uint8_t index;

    switch (offset) {
    case AW_A10_PIT_TIMER_IRQ_EN:
        s->irq_enable = value;
        a10_pit_update_irq(s);
        break;
    case AW_A10_PIT_TIMER_IRQ_ST:
        s->irq_status &= ~value;
        a10_pit_update_irq(s);
        break;
    case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
        index = offset & 0xf0;
        index >>= 4;
        index -= 1;
        switch (offset & 0x0f) {
        case AW_A10_PIT_TIMER_CONTROL:
            s->control[index] = value;
            ptimer_transaction_begin(s->timer[index]);
            a10_pit_set_freq(s, index);
            if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
                ptimer_set_count(s->timer[index], s->interval[index]);
            }
            if (s->control[index] & AW_A10_PIT_TIMER_EN) {
                int oneshot = 0;
                if (s->control[index] & AW_A10_PIT_TIMER_MODE) {
                    oneshot = 1;
                }
                ptimer_run(s->timer[index], oneshot);
            } else {
                ptimer_stop(s->timer[index]);
            }
            ptimer_transaction_commit(s->timer[index]);
            break;
        case AW_A10_PIT_TIMER_INTERVAL:
            s->interval[index] = value;
            ptimer_transaction_begin(s->timer[index]);
            ptimer_set_limit(s->timer[index], s->interval[index], 1);
            ptimer_transaction_commit(s->timer[index]);
            break;
        case AW_A10_PIT_TIMER_COUNT:
            s->count[index] = value;
            break;
        default:
            qemu_log_mask(LOG_GUEST_ERROR,
                          "%s: Bad offset 0x%x\n",  __func__, (int)offset);
        }
        break;
    case AW_A10_PIT_WDOG_CONTROL:
        s->watch_dog_control = value;
        break;
    case AW_A10_PIT_WDOG_MODE:
        s->watch_dog_mode = value;
        break;
    case AW_A10_PIT_COUNT_LO:
        s->count_lo = value;
        break;
    case AW_A10_PIT_COUNT_HI:
        s->count_hi = value;
        break;
    case AW_A10_PIT_COUNT_CTL:
        s->count_ctl = value;
        if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) {
            uint64_t  tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);

            s->count_lo = tmp_count;
            s->count_hi = tmp_count >> 32;
            s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN;
        }
        if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) {
            s->count_lo = 0;
            s->count_hi = 0;
            s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN;
        }
        break;
    default:
        qemu_log_mask(LOG_GUEST_ERROR,
                      "%s: Bad offset 0x%x\n",  __func__, (int)offset);
        break;
    }
}

static const MemoryRegionOps a10_pit_ops = {
    .read = a10_pit_read,
    .write = a10_pit_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static Property a10_pit_properties[] = {
    DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0),
    DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0),
    DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0),
    DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0),
    DEFINE_PROP_END_OF_LIST(),
};

static const VMStateDescription vmstate_a10_pit = {
    .name = "a10.pit",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(irq_enable, AwA10PITState),
        VMSTATE_UINT32(irq_status, AwA10PITState),
        VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_UINT32(watch_dog_mode, AwA10PITState),
        VMSTATE_UINT32(watch_dog_control, AwA10PITState),
        VMSTATE_UINT32(count_lo, AwA10PITState),
        VMSTATE_UINT32(count_hi, AwA10PITState),
        VMSTATE_UINT32(count_ctl, AwA10PITState),
        VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR),
        VMSTATE_END_OF_LIST()
    }
};

static void a10_pit_reset(DeviceState *dev)
{
    AwA10PITState *s = AW_A10_PIT(dev);
    uint8_t i;

    s->irq_enable = 0;
    s->irq_status = 0;
    a10_pit_update_irq(s);

    for (i = 0; i < 6; i++) {
        s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
        s->interval[i] = 0;
        s->count[i] = 0;
        ptimer_transaction_begin(s->timer[i]);
        ptimer_stop(s->timer[i]);
        a10_pit_set_freq(s, i);
        ptimer_transaction_commit(s->timer[i]);
    }
    s->watch_dog_mode = 0;
    s->watch_dog_control = 0;
    s->count_lo = 0;
    s->count_hi = 0;
    s->count_ctl = 0;
}

static void a10_pit_timer_cb(void *opaque)
{
    AwA10TimerContext *tc = opaque;
    AwA10PITState *s = tc->container;
    uint8_t i = tc->index;

    if (s->control[i] & AW_A10_PIT_TIMER_EN) {
        s->irq_status |= 1 << i;
        if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
            ptimer_stop(s->timer[i]);
            s->control[i] &= ~AW_A10_PIT_TIMER_EN;
        }
        a10_pit_update_irq(s);
    }
}

static void a10_pit_init(Object *obj)
{
    AwA10PITState *s = AW_A10_PIT(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    uint8_t i;

    for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
        sysbus_init_irq(sbd, &s->irq[i]);
    }
    memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s,
                          TYPE_AW_A10_PIT, 0x400);
    sysbus_init_mmio(sbd, &s->iomem);

    for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
        AwA10TimerContext *tc = &s->timer_context[i];

        tc->container = s;
        tc->index = i;
        s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT);
    }
}

static void a10_pit_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->reset = a10_pit_reset;
    device_class_set_props(dc, a10_pit_properties);
    dc->desc = "allwinner a10 timer";
    dc->vmsd = &vmstate_a10_pit;
}

static const TypeInfo a10_pit_info = {
    .name = TYPE_AW_A10_PIT,
    .parent = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(AwA10PITState),
    .instance_init = a10_pit_init,
    .class_init = a10_pit_class_init,
};

static void a10_register_types(void)
{
    type_register_static(&a10_pit_info);
}

type_init(a10_register_types);
Commit	Line	Data
3589de8c LG	1	/*
	2	* Allwinner A10 timer device emulation
	3	*
	4	* Copyright (C) 2013 Li Guang
	5	* Written by Li Guang <lig.fnst@cn.fujitsu.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms of the GNU General Public License as published by the
	9	* Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful, but WITHOUT
	13	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	14	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	15	* for more details.
	16	*/
	17
8ef94f0b	18	#include "qemu/osdep.h"
64552b6b	19	#include "hw/irq.h"
a27bd6c7	20	#include "hw/qdev-properties.h"
3589de8c	21	#include "hw/sysbus.h"
3589de8c	22	#include "hw/timer/allwinner-a10-pit.h"
d6454270	23	#include "migration/vmstate.h"
03dd024f	24	#include "qemu/log.h"
0b8fa32f	25	#include "qemu/module.h"
3589de8c	26
a63f9f85 BG	27	static void a10_pit_update_irq(AwA10PITState *s)
	28	{
	29	int i;
	30
	31	for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
	32	qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i)));
	33	}
	34	}
	35
3589de8c LG	36	static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size)
	37	{
	38	AwA10PITState *s = AW_A10_PIT(opaque);
	39	uint8_t index;
	40
	41	switch (offset) {
	42	case AW_A10_PIT_TIMER_IRQ_EN:
	43	return s->irq_enable;
	44	case AW_A10_PIT_TIMER_IRQ_ST:
	45	return s->irq_status;
	46	case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
	47	index = offset & 0xf0;
	48	index >>= 4;
	49	index -= 1;
	50	switch (offset & 0x0f) {
	51	case AW_A10_PIT_TIMER_CONTROL:
	52	return s->control[index];
	53	case AW_A10_PIT_TIMER_INTERVAL:
	54	return s->interval[index];
	55	case AW_A10_PIT_TIMER_COUNT:
	56	s->count[index] = ptimer_get_count(s->timer[index]);
	57	return s->count[index];
	58	default:
	59	qemu_log_mask(LOG_GUEST_ERROR,
	60	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	61	break;
	62	}
	63	case AW_A10_PIT_WDOG_CONTROL:
	64	break;
	65	case AW_A10_PIT_WDOG_MODE:
	66	break;
	67	case AW_A10_PIT_COUNT_LO:
	68	return s->count_lo;
	69	case AW_A10_PIT_COUNT_HI:
	70	return s->count_hi;
	71	case AW_A10_PIT_COUNT_CTL:
	72	return s->count_ctl;
	73	default:
	74	qemu_log_mask(LOG_GUEST_ERROR,
	75	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	76	break;
	77	}
	78
	79	return 0;
	80	}
	81
827c4214	82	/* Must be called inside a ptimer transaction block for s->timer[index] */
286226a4 BG	83	static void a10_pit_set_freq(AwA10PITState *s, int index)
	84	{
	85	uint32_t prescaler, source, source_freq;
	86
	87	prescaler = 1 << extract32(s->control[index], 4, 3);
	88	source = extract32(s->control[index], 2, 2);
	89	source_freq = s->clk_freq[source];
	90
	91	if (source_freq) {
	92	ptimer_set_freq(s->timer[index], source_freq / prescaler);
	93	} else {
	94	qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n",
	95	__func__, source);
	96	}
	97	}
	98
3589de8c LG	99	static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value,
	100	unsigned size)
	101	{
	102	AwA10PITState *s = AW_A10_PIT(opaque);
	103	uint8_t index;
	104
	105	switch (offset) {
	106	case AW_A10_PIT_TIMER_IRQ_EN:
	107	s->irq_enable = value;
a63f9f85	108	a10_pit_update_irq(s);
3589de8c LG	109	break;
	110	case AW_A10_PIT_TIMER_IRQ_ST:
	111	s->irq_status &= ~value;
a63f9f85	112	a10_pit_update_irq(s);
3589de8c LG	113	break;
	114	case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END:
	115	index = offset & 0xf0;
	116	index >>= 4;
	117	index -= 1;
	118	switch (offset & 0x0f) {
	119	case AW_A10_PIT_TIMER_CONTROL:
	120	s->control[index] = value;
827c4214	121	ptimer_transaction_begin(s->timer[index]);
286226a4	122	a10_pit_set_freq(s, index);
3589de8c LG	123	if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) {
	124	ptimer_set_count(s->timer[index], s->interval[index]);
	125	}
	126	if (s->control[index] & AW_A10_PIT_TIMER_EN) {
	127	int oneshot = 0;
	128	if (s->control[index] & AW_A10_PIT_TIMER_MODE) {
	129	oneshot = 1;
	130	}
	131	ptimer_run(s->timer[index], oneshot);
	132	} else {
	133	ptimer_stop(s->timer[index]);
	134	}
827c4214	135	ptimer_transaction_commit(s->timer[index]);
3589de8c LG	136	break;
	137	case AW_A10_PIT_TIMER_INTERVAL:
	138	s->interval[index] = value;
827c4214	139	ptimer_transaction_begin(s->timer[index]);
3589de8c	140	ptimer_set_limit(s->timer[index], s->interval[index], 1);
827c4214	141	ptimer_transaction_commit(s->timer[index]);
3589de8c LG	142	break;
	143	case AW_A10_PIT_TIMER_COUNT:
	144	s->count[index] = value;
	145	break;
	146	default:
	147	qemu_log_mask(LOG_GUEST_ERROR,
	148	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	149	}
	150	break;
	151	case AW_A10_PIT_WDOG_CONTROL:
	152	s->watch_dog_control = value;
	153	break;
	154	case AW_A10_PIT_WDOG_MODE:
	155	s->watch_dog_mode = value;
	156	break;
	157	case AW_A10_PIT_COUNT_LO:
	158	s->count_lo = value;
	159	break;
	160	case AW_A10_PIT_COUNT_HI:
	161	s->count_hi = value;
	162	break;
	163	case AW_A10_PIT_COUNT_CTL:
	164	s->count_ctl = value;
	165	if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) {
	166	uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
	167
	168	s->count_lo = tmp_count;
	169	s->count_hi = tmp_count >> 32;
	170	s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN;
	171	}
	172	if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) {
	173	s->count_lo = 0;
	174	s->count_hi = 0;
	175	s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN;
	176	}
	177	break;
	178	default:
	179	qemu_log_mask(LOG_GUEST_ERROR,
	180	"%s: Bad offset 0x%x\n", __func__, (int)offset);
	181	break;
	182	}
	183	}
	184
	185	static const MemoryRegionOps a10_pit_ops = {
	186	.read = a10_pit_read,
	187	.write = a10_pit_write,
	188	.endianness = DEVICE_NATIVE_ENDIAN,
	189	};
	190
286226a4 BG	191	static Property a10_pit_properties[] = {
	192	DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0),
	193	DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0),
	194	DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0),
	195	DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0),
	196	DEFINE_PROP_END_OF_LIST(),
	197	};
	198
3589de8c LG	199	static const VMStateDescription vmstate_a10_pit = {
	200	.name = "a10.pit",
	201	.version_id = 1,
	202	.minimum_version_id = 1,
3589de8c LG	203	.fields = (VMStateField[]) {
	204	VMSTATE_UINT32(irq_enable, AwA10PITState),
	205	VMSTATE_UINT32(irq_status, AwA10PITState),
	206	VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR),
	207	VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR),
	208	VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR),
	209	VMSTATE_UINT32(watch_dog_mode, AwA10PITState),
	210	VMSTATE_UINT32(watch_dog_control, AwA10PITState),
	211	VMSTATE_UINT32(count_lo, AwA10PITState),
	212	VMSTATE_UINT32(count_hi, AwA10PITState),
	213	VMSTATE_UINT32(count_ctl, AwA10PITState),
	214	VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR),
	215	VMSTATE_END_OF_LIST()
	216	}
	217	};
	218
	219	static void a10_pit_reset(DeviceState *dev)
	220	{
	221	AwA10PITState *s = AW_A10_PIT(dev);
	222	uint8_t i;
	223
	224	s->irq_enable = 0;
	225	s->irq_status = 0;
a63f9f85 BG	226	a10_pit_update_irq(s);
a63f9f85 BG	227
3589de8c LG	228	for (i = 0; i < 6; i++) {
	229	s->control[i] = AW_A10_PIT_DEFAULT_CLOCK;
	230	s->interval[i] = 0;
	231	s->count[i] = 0;
827c4214	232	ptimer_transaction_begin(s->timer[i]);
3589de8c	233	ptimer_stop(s->timer[i]);
286226a4	234	a10_pit_set_freq(s, i);
827c4214	235	ptimer_transaction_commit(s->timer[i]);
3589de8c LG	236	}
	237	s->watch_dog_mode = 0;
	238	s->watch_dog_control = 0;
	239	s->count_lo = 0;
	240	s->count_hi = 0;
	241	s->count_ctl = 0;
	242	}
	243
	244	static void a10_pit_timer_cb(void *opaque)
	245	{
323a8771 BG	246	AwA10TimerContext *tc = opaque;
	247	AwA10PITState *s = tc->container;
	248	uint8_t i = tc->index;
3589de8c	249
323a8771 BG	250	if (s->control[i] & AW_A10_PIT_TIMER_EN) {
	251	s->irq_status \|= 1 << i;
	252	if (s->control[i] & AW_A10_PIT_TIMER_MODE) {
	253	ptimer_stop(s->timer[i]);
	254	s->control[i] &= ~AW_A10_PIT_TIMER_EN;
3589de8c	255	}
a63f9f85	256	a10_pit_update_irq(s);
3589de8c LG	257	}
	258	}
	259
	260	static void a10_pit_init(Object *obj)
	261	{
	262	AwA10PITState *s = AW_A10_PIT(obj);
	263	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
3589de8c LG	264	uint8_t i;
	265
	266	for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
	267	sysbus_init_irq(sbd, &s->irq[i]);
	268	}
	269	memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s,
	270	TYPE_AW_A10_PIT, 0x400);
	271	sysbus_init_mmio(sbd, &s->iomem);
	272
	273	for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) {
323a8771 BG	274	AwA10TimerContext *tc = &s->timer_context[i];
	275
	276	tc->container = s;
	277	tc->index = i;
827c4214	278	s->timer[i] = ptimer_init(a10_pit_timer_cb, tc, PTIMER_POLICY_DEFAULT);
3589de8c LG	279	}
	280	}
	281
	282	static void a10_pit_class_init(ObjectClass klass, void data)
	283	{
	284	DeviceClass *dc = DEVICE_CLASS(klass);
	285
	286	dc->reset = a10_pit_reset;
4f67d30b	287	device_class_set_props(dc, a10_pit_properties);
3589de8c LG	288	dc->desc = "allwinner a10 timer";
	289	dc->vmsd = &vmstate_a10_pit;
	290	}
	291
	292	static const TypeInfo a10_pit_info = {
	293	.name = TYPE_AW_A10_PIT,
	294	.parent = TYPE_SYS_BUS_DEVICE,
	295	.instance_size = sizeof(AwA10PITState),
	296	.instance_init = a10_pit_init,
	297	.class_init = a10_pit_class_init,
	298	};
	299
	300	static void a10_register_types(void)
	301	{
	302	type_register_static(&a10_pit_info);
	303	}
	304
	305	type_init(a10_register_types);