[mirror_qemu.git] / hw / timer / altera_timer.c

/*
 * QEMU model of the Altera timer.
 *
 * Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2.1 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see
 * <http://www.gnu.org/licenses/lgpl-2.1.html>
 */

#include "qemu/osdep.h"
#include "qemu/module.h"
#include "qapi/error.h"

#include "hw/sysbus.h"
#include "sysemu/sysemu.h"
#include "hw/irq.h"
#include "hw/ptimer.h"

#define R_STATUS      0
#define R_CONTROL     1
#define R_PERIODL     2
#define R_PERIODH     3
#define R_SNAPL       4
#define R_SNAPH       5
#define R_MAX         6

#define STATUS_TO     0x0001
#define STATUS_RUN    0x0002

#define CONTROL_ITO   0x0001
#define CONTROL_CONT  0x0002
#define CONTROL_START 0x0004
#define CONTROL_STOP  0x0008

#define TYPE_ALTERA_TIMER "ALTR.timer"
#define ALTERA_TIMER(obj) \
    OBJECT_CHECK(AlteraTimer, (obj), TYPE_ALTERA_TIMER)

typedef struct AlteraTimer {
    SysBusDevice  busdev;
    MemoryRegion  mmio;
    qemu_irq      irq;
    uint32_t      freq_hz;
    QEMUBH       *bh;
    ptimer_state *ptimer;
    uint32_t      regs[R_MAX];
} AlteraTimer;

static int timer_irq_state(AlteraTimer *t)
{
    bool irq = (t->regs[R_STATUS] & STATUS_TO) &&
               (t->regs[R_CONTROL] & CONTROL_ITO);
    return irq;
}

static uint64_t timer_read(void *opaque, hwaddr addr,
                           unsigned int size)
{
    AlteraTimer *t = opaque;
    uint64_t r = 0;

    addr >>= 2;

    switch (addr) {
    case R_CONTROL:
        r = t->regs[R_CONTROL] & (CONTROL_ITO | CONTROL_CONT);
        break;

    default:
        if (addr < ARRAY_SIZE(t->regs)) {
            r = t->regs[addr];
        }
        break;
    }

    return r;
}

static void timer_write(void *opaque, hwaddr addr,
                        uint64_t value, unsigned int size)
{
    AlteraTimer *t = opaque;
    uint64_t tvalue;
    uint32_t count = 0;
    int irqState = timer_irq_state(t);

    addr >>= 2;

    switch (addr) {
    case R_STATUS:
        /* The timeout bit is cleared by writing the status register. */
        t->regs[R_STATUS] &= ~STATUS_TO;
        break;

    case R_CONTROL:
        t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT);
        if ((value & CONTROL_START) &&
            !(t->regs[R_STATUS] & STATUS_RUN)) {
            ptimer_run(t->ptimer, 1);
            t->regs[R_STATUS] |= STATUS_RUN;
        }
        if ((value & CONTROL_STOP) && (t->regs[R_STATUS] & STATUS_RUN)) {
            ptimer_stop(t->ptimer);
            t->regs[R_STATUS] &= ~STATUS_RUN;
        }
        break;

    case R_PERIODL:
    case R_PERIODH:
        t->regs[addr] = value & 0xFFFF;
        if (t->regs[R_STATUS] & STATUS_RUN) {
            ptimer_stop(t->ptimer);
            t->regs[R_STATUS] &= ~STATUS_RUN;
        }
        tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
        ptimer_set_limit(t->ptimer, tvalue + 1, 1);
        break;

    case R_SNAPL:
    case R_SNAPH:
        count = ptimer_get_count(t->ptimer);
        t->regs[R_SNAPL] = count & 0xFFFF;
        t->regs[R_SNAPH] = count >> 16;
        break;

    default:
        break;
    }

    if (irqState != timer_irq_state(t)) {
        qemu_set_irq(t->irq, timer_irq_state(t));
    }
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 1,
        .max_access_size = 4
    }
};

static void timer_hit(void *opaque)
{
    AlteraTimer *t = opaque;
    const uint64_t tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];

    t->regs[R_STATUS] |= STATUS_TO;

    ptimer_set_limit(t->ptimer, tvalue + 1, 1);

    if (!(t->regs[R_CONTROL] & CONTROL_CONT)) {
        t->regs[R_STATUS] &= ~STATUS_RUN;
        ptimer_set_count(t->ptimer, tvalue);
    } else {
        ptimer_run(t->ptimer, 1);
    }

    qemu_set_irq(t->irq, timer_irq_state(t));
}

static void altera_timer_realize(DeviceState *dev, Error **errp)
{
    AlteraTimer *t = ALTERA_TIMER(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    if (t->freq_hz == 0) {
        error_setg(errp, "\"clock-frequency\" property must be provided.");
        return;
    }

    t->bh = qemu_bh_new(timer_hit, t);
    t->ptimer = ptimer_init(t->bh, PTIMER_POLICY_DEFAULT);
    ptimer_set_freq(t->ptimer, t->freq_hz);

    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
                          TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t));
    sysbus_init_mmio(sbd, &t->mmio);
}

static void altera_timer_init(Object *obj)
{
    AlteraTimer *t = ALTERA_TIMER(obj);
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);

    sysbus_init_irq(sbd, &t->irq);
}

static void altera_timer_reset(DeviceState *dev)
{
    AlteraTimer *t = ALTERA_TIMER(dev);

    ptimer_stop(t->ptimer);
    ptimer_set_limit(t->ptimer, 0xffffffff, 1);
    memset(t->regs, 0, sizeof(t->regs));
}

static Property altera_timer_properties[] = {
    DEFINE_PROP_UINT32("clock-frequency", AlteraTimer, freq_hz, 0),
    DEFINE_PROP_END_OF_LIST(),
};

static void altera_timer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = altera_timer_realize;
    dc->props = altera_timer_properties;
    dc->reset = altera_timer_reset;
}

static const TypeInfo altera_timer_info = {
    .name          = TYPE_ALTERA_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(AlteraTimer),
    .instance_init = altera_timer_init,
    .class_init    = altera_timer_class_init,
};

static void altera_timer_register(void)
{
    type_register_static(&altera_timer_info);
}

type_init(altera_timer_register)
Commit	Line	Data
a32a2253 CW	1	/*
	2	* QEMU model of the Altera timer.
	3	*
	4	* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2.1 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see
	18	* <http://www.gnu.org/licenses/lgpl-2.1.html>
	19	*/
	20
	21	#include "qemu/osdep.h"
0b8fa32f	22	#include "qemu/module.h"
a32a2253 CW	23	#include "qapi/error.h"
	24
	25	#include "hw/sysbus.h"
	26	#include "sysemu/sysemu.h"
64552b6b	27	#include "hw/irq.h"
a32a2253 CW	28	#include "hw/ptimer.h"
	29
	30	#define R_STATUS 0
	31	#define R_CONTROL 1
	32	#define R_PERIODL 2
	33	#define R_PERIODH 3
	34	#define R_SNAPL 4
	35	#define R_SNAPH 5
	36	#define R_MAX 6
	37
	38	#define STATUS_TO 0x0001
	39	#define STATUS_RUN 0x0002
	40
	41	#define CONTROL_ITO 0x0001
	42	#define CONTROL_CONT 0x0002
	43	#define CONTROL_START 0x0004
	44	#define CONTROL_STOP 0x0008
	45
	46	#define TYPE_ALTERA_TIMER "ALTR.timer"
	47	#define ALTERA_TIMER(obj) \
	48	OBJECT_CHECK(AlteraTimer, (obj), TYPE_ALTERA_TIMER)
	49
	50	typedef struct AlteraTimer {
	51	SysBusDevice busdev;
	52	MemoryRegion mmio;
	53	qemu_irq irq;
	54	uint32_t freq_hz;
	55	QEMUBH *bh;
	56	ptimer_state *ptimer;
	57	uint32_t regs[R_MAX];
	58	} AlteraTimer;
	59
	60	static int timer_irq_state(AlteraTimer *t)
	61	{
	62	bool irq = (t->regs[R_STATUS] & STATUS_TO) &&
	63	(t->regs[R_CONTROL] & CONTROL_ITO);
	64	return irq;
	65	}
	66
	67	static uint64_t timer_read(void *opaque, hwaddr addr,
	68	unsigned int size)
	69	{
	70	AlteraTimer *t = opaque;
	71	uint64_t r = 0;
	72
	73	addr >>= 2;
	74
	75	switch (addr) {
	76	case R_CONTROL:
	77	r = t->regs[R_CONTROL] & (CONTROL_ITO \| CONTROL_CONT);
	78	break;
	79
	80	default:
	81	if (addr < ARRAY_SIZE(t->regs)) {
	82	r = t->regs[addr];
	83	}
	84	break;
	85	}
	86
	87	return r;
	88	}
	89
	90	static void timer_write(void *opaque, hwaddr addr,
	91	uint64_t value, unsigned int size)
92	{
93	AlteraTimer *t = opaque;
94	uint64_t tvalue;
95	uint32_t count = 0;
96	int irqState = timer_irq_state(t);
97
98	addr >>= 2;
99
100	switch (addr) {
101	case R_STATUS:
102	/* The timeout bit is cleared by writing the status register. */
103	t->regs[R_STATUS] &= ~STATUS_TO;
104	break;
105
106	case R_CONTROL:
107	t->regs[R_CONTROL] = value & (CONTROL_ITO \| CONTROL_CONT);
108	if ((value & CONTROL_START) &&
109	!(t->regs[R_STATUS] & STATUS_RUN)) {
110	ptimer_run(t->ptimer, 1);
111	t->regs[R_STATUS] \|= STATUS_RUN;
112	}
113	if ((value & CONTROL_STOP) && (t->regs[R_STATUS] & STATUS_RUN)) {
114	ptimer_stop(t->ptimer);
115	t->regs[R_STATUS] &= ~STATUS_RUN;
116	}
117	break;
118
119	case R_PERIODL:
120	case R_PERIODH:
121	t->regs[addr] = value & 0xFFFF;
122	if (t->regs[R_STATUS] & STATUS_RUN) {
123	ptimer_stop(t->ptimer);
124	t->regs[R_STATUS] &= ~STATUS_RUN;
125	}
126	tvalue = (t->regs[R_PERIODH] << 16) \| t->regs[R_PERIODL];
127	ptimer_set_limit(t->ptimer, tvalue + 1, 1);
128	break;
129
130	case R_SNAPL:
131	case R_SNAPH:
132	count = ptimer_get_count(t->ptimer);
133	t->regs[R_SNAPL] = count & 0xFFFF;
134	t->regs[R_SNAPH] = count >> 16;
135	break;
136
137	default:
138	break;
139	}
140
141	if (irqState != timer_irq_state(t)) {
142	qemu_set_irq(t->irq, timer_irq_state(t));
143	}
144	}
145
146	static const MemoryRegionOps timer_ops = {
147	.read = timer_read,
148	.write = timer_write,
149	.endianness = DEVICE_NATIVE_ENDIAN,
150	.valid = {
151	.min_access_size = 1,
152	.max_access_size = 4
153	}
154	};
155
156	static void timer_hit(void *opaque)
157	{
158	AlteraTimer *t = opaque;
159	const uint64_t tvalue = (t->regs[R_PERIODH] << 16) \| t->regs[R_PERIODL];
160
161	t->regs[R_STATUS] \|= STATUS_TO;
162
163	ptimer_set_limit(t->ptimer, tvalue + 1, 1);
164
165	if (!(t->regs[R_CONTROL] & CONTROL_CONT)) {
166	t->regs[R_STATUS] &= ~STATUS_RUN;
167	ptimer_set_count(t->ptimer, tvalue);
168	} else {
169	ptimer_run(t->ptimer, 1);
170	}
171
172	qemu_set_irq(t->irq, timer_irq_state(t));
173	}
174
175	static void altera_timer_realize(DeviceState dev, Error *errp)
176	{
177	AlteraTimer *t = ALTERA_TIMER(dev);
178	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
179
180	if (t->freq_hz == 0) {
181	error_setg(errp, "\"clock-frequency\" property must be provided.");
182	return;
183	}
184
185	t->bh = qemu_bh_new(timer_hit, t);
186	t->ptimer = ptimer_init(t->bh, PTIMER_POLICY_DEFAULT);
187	ptimer_set_freq(t->ptimer, t->freq_hz);
188
189	memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
190	TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t));
191	sysbus_init_mmio(sbd, &t->mmio);
192	}
193
194	static void altera_timer_init(Object *obj)
195	{
196	AlteraTimer *t = ALTERA_TIMER(obj);
197	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
198
199	sysbus_init_irq(sbd, &t->irq);
200	}
201
202	static void altera_timer_reset(DeviceState *dev)
203	{
204	AlteraTimer *t = ALTERA_TIMER(dev);
205
206	ptimer_stop(t->ptimer);
207	ptimer_set_limit(t->ptimer, 0xffffffff, 1);
cc16ee9d	208	memset(t->regs, 0, sizeof(t->regs));
a32a2253 CW	209	}
	210
	211	static Property altera_timer_properties[] = {
	212	DEFINE_PROP_UINT32("clock-frequency", AlteraTimer, freq_hz, 0),
	213	DEFINE_PROP_END_OF_LIST(),
	214	};
	215
	216	static void altera_timer_class_init(ObjectClass klass, void data)
	217	{
	218	DeviceClass *dc = DEVICE_CLASS(klass);
	219
	220	dc->realize = altera_timer_realize;
	221	dc->props = altera_timer_properties;
	222	dc->reset = altera_timer_reset;
	223	}
	224
	225	static const TypeInfo altera_timer_info = {
	226	.name = TYPE_ALTERA_TIMER,
	227	.parent = TYPE_SYS_BUS_DEVICE,
	228	.instance_size = sizeof(AlteraTimer),
	229	.instance_init = altera_timer_init,
	230	.class_init = altera_timer_class_init,
	231	};
	232
	233	static void altera_timer_register(void)
	234	{
	235	type_register_static(&altera_timer_info);
	236	}
	237
	238	type_init(altera_timer_register)