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b9dc07d4 PM |
1 | /* |
2 | * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Copyright (c) 2011 Linaro Limited | |
6 | * Written by Paul Brook, Peter Maydell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
8ef94f0b | 22 | #include "qemu/osdep.h" |
226fb5aa | 23 | #include "hw/ptimer.h" |
eb110bd8 | 24 | #include "hw/timer/arm_mptimer.h" |
da34e65c | 25 | #include "qapi/error.h" |
226fb5aa | 26 | #include "qemu/main-loop.h" |
0b8fa32f | 27 | #include "qemu/module.h" |
de6db419 | 28 | #include "qom/cpu.h" |
b9dc07d4 | 29 | |
226fb5aa DO |
30 | #define PTIMER_POLICY \ |
31 | (PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD | \ | |
32 | PTIMER_POLICY_CONTINUOUS_TRIGGER | \ | |
33 | PTIMER_POLICY_NO_IMMEDIATE_TRIGGER | \ | |
34 | PTIMER_POLICY_NO_IMMEDIATE_RELOAD | \ | |
35 | PTIMER_POLICY_NO_COUNTER_ROUND_DOWN) | |
36 | ||
b9dc07d4 PM |
37 | /* This device implements the per-cpu private timer and watchdog block |
38 | * which is used in both the ARM11MPCore and Cortex-A9MP. | |
39 | */ | |
40 | ||
c6205ddf | 41 | static inline int get_current_cpu(ARMMPTimerState *s) |
b9dc07d4 | 42 | { |
226fb5aa DO |
43 | int cpu_id = current_cpu ? current_cpu->cpu_index : 0; |
44 | ||
45 | if (cpu_id >= s->num_cpu) { | |
b9dc07d4 | 46 | hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", |
226fb5aa | 47 | s->num_cpu, cpu_id); |
b9dc07d4 | 48 | } |
226fb5aa DO |
49 | |
50 | return cpu_id; | |
b9dc07d4 PM |
51 | } |
52 | ||
c6205ddf | 53 | static inline void timerblock_update_irq(TimerBlock *tb) |
b9dc07d4 | 54 | { |
257621a9 | 55 | qemu_set_irq(tb->irq, tb->status && (tb->control & 4)); |
b9dc07d4 PM |
56 | } |
57 | ||
58 | /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */ | |
226fb5aa | 59 | static inline uint32_t timerblock_scale(uint32_t control) |
b9dc07d4 | 60 | { |
226fb5aa | 61 | return (((control >> 8) & 0xff) + 1) * 10; |
b9dc07d4 PM |
62 | } |
63 | ||
226fb5aa DO |
64 | static inline void timerblock_set_count(struct ptimer_state *timer, |
65 | uint32_t control, uint64_t *count) | |
b9dc07d4 | 66 | { |
226fb5aa DO |
67 | /* PTimer would trigger interrupt for periodic timer when counter set |
68 | * to 0, MPtimer under certain condition only. | |
69 | */ | |
70 | if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) { | |
71 | *count = ptimer_get_limit(timer); | |
b9dc07d4 | 72 | } |
226fb5aa DO |
73 | ptimer_set_count(timer, *count); |
74 | } | |
75 | ||
76 | static inline void timerblock_run(struct ptimer_state *timer, | |
77 | uint32_t control, uint32_t load) | |
78 | { | |
79 | if ((control & 1) && ((control & 0xff00) || load != 0)) { | |
80 | ptimer_run(timer, !(control & 2)); | |
b9dc07d4 | 81 | } |
b9dc07d4 PM |
82 | } |
83 | ||
84 | static void timerblock_tick(void *opaque) | |
85 | { | |
c6205ddf | 86 | TimerBlock *tb = (TimerBlock *)opaque; |
226fb5aa DO |
87 | /* Periodic timer with load = 0 and prescaler != 0 would re-trigger |
88 | * IRQ after one period, otherwise it either stops or wraps around. | |
89 | */ | |
90 | if ((tb->control & 2) && (tb->control & 0xff00) == 0 && | |
91 | ptimer_get_limit(tb->timer) == 0) { | |
92 | ptimer_stop(tb->timer); | |
b9dc07d4 | 93 | } |
226fb5aa | 94 | tb->status = 1; |
b9dc07d4 PM |
95 | timerblock_update_irq(tb); |
96 | } | |
97 | ||
a8170e5e | 98 | static uint64_t timerblock_read(void *opaque, hwaddr addr, |
b9dc07d4 PM |
99 | unsigned size) |
100 | { | |
c6205ddf | 101 | TimerBlock *tb = (TimerBlock *)opaque; |
b9dc07d4 PM |
102 | switch (addr) { |
103 | case 0: /* Load */ | |
226fb5aa | 104 | return ptimer_get_limit(tb->timer); |
b9dc07d4 | 105 | case 4: /* Counter. */ |
226fb5aa | 106 | return ptimer_get_count(tb->timer); |
b9dc07d4 PM |
107 | case 8: /* Control. */ |
108 | return tb->control; | |
109 | case 12: /* Interrupt status. */ | |
110 | return tb->status; | |
111 | default: | |
112 | return 0; | |
113 | } | |
114 | } | |
115 | ||
a8170e5e | 116 | static void timerblock_write(void *opaque, hwaddr addr, |
b9dc07d4 PM |
117 | uint64_t value, unsigned size) |
118 | { | |
c6205ddf | 119 | TimerBlock *tb = (TimerBlock *)opaque; |
226fb5aa | 120 | uint32_t control = tb->control; |
b9dc07d4 PM |
121 | switch (addr) { |
122 | case 0: /* Load */ | |
226fb5aa DO |
123 | /* Setting load to 0 stops the timer without doing the tick if |
124 | * prescaler = 0. | |
125 | */ | |
126 | if ((control & 1) && (control & 0xff00) == 0 && value == 0) { | |
127 | ptimer_stop(tb->timer); | |
b9dc07d4 | 128 | } |
226fb5aa DO |
129 | ptimer_set_limit(tb->timer, value, 1); |
130 | timerblock_run(tb->timer, control, value); | |
131 | break; | |
132 | case 4: /* Counter. */ | |
133 | /* Setting counter to 0 stops the one-shot timer, or periodic with | |
134 | * load = 0, without doing the tick if prescaler = 0. | |
135 | */ | |
136 | if ((control & 1) && (control & 0xff00) == 0 && value == 0 && | |
137 | (!(control & 2) || ptimer_get_limit(tb->timer) == 0)) { | |
138 | ptimer_stop(tb->timer); | |
b9dc07d4 | 139 | } |
226fb5aa DO |
140 | timerblock_set_count(tb->timer, control, &value); |
141 | timerblock_run(tb->timer, control, value); | |
b9dc07d4 PM |
142 | break; |
143 | case 8: /* Control. */ | |
226fb5aa DO |
144 | if ((control & 3) != (value & 3)) { |
145 | ptimer_stop(tb->timer); | |
146 | } | |
147 | if ((control & 0xff00) != (value & 0xff00)) { | |
148 | ptimer_set_period(tb->timer, timerblock_scale(value)); | |
149 | } | |
8a52340c | 150 | if (value & 1) { |
226fb5aa DO |
151 | uint64_t count = ptimer_get_count(tb->timer); |
152 | /* Re-load periodic timer counter if needed. */ | |
153 | if ((value & 2) && count == 0) { | |
154 | timerblock_set_count(tb->timer, value, &count); | |
8a52340c | 155 | } |
226fb5aa | 156 | timerblock_run(tb->timer, value, count); |
b9dc07d4 | 157 | } |
226fb5aa | 158 | tb->control = value; |
b9dc07d4 PM |
159 | break; |
160 | case 12: /* Interrupt status. */ | |
161 | tb->status &= ~value; | |
162 | timerblock_update_irq(tb); | |
163 | break; | |
164 | } | |
165 | } | |
166 | ||
167 | /* Wrapper functions to implement the "read timer/watchdog for | |
168 | * the current CPU" memory regions. | |
169 | */ | |
a8170e5e | 170 | static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, |
b9dc07d4 PM |
171 | unsigned size) |
172 | { | |
c6205ddf | 173 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
b9dc07d4 | 174 | int id = get_current_cpu(s); |
cde4577f | 175 | return timerblock_read(&s->timerblock[id], addr, size); |
b9dc07d4 PM |
176 | } |
177 | ||
a8170e5e | 178 | static void arm_thistimer_write(void *opaque, hwaddr addr, |
b9dc07d4 PM |
179 | uint64_t value, unsigned size) |
180 | { | |
c6205ddf | 181 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
b9dc07d4 | 182 | int id = get_current_cpu(s); |
cde4577f | 183 | timerblock_write(&s->timerblock[id], addr, value, size); |
b9dc07d4 PM |
184 | } |
185 | ||
186 | static const MemoryRegionOps arm_thistimer_ops = { | |
187 | .read = arm_thistimer_read, | |
188 | .write = arm_thistimer_write, | |
189 | .valid = { | |
190 | .min_access_size = 4, | |
191 | .max_access_size = 4, | |
192 | }, | |
193 | .endianness = DEVICE_NATIVE_ENDIAN, | |
194 | }; | |
195 | ||
b9dc07d4 PM |
196 | static const MemoryRegionOps timerblock_ops = { |
197 | .read = timerblock_read, | |
198 | .write = timerblock_write, | |
199 | .valid = { | |
200 | .min_access_size = 4, | |
201 | .max_access_size = 4, | |
202 | }, | |
203 | .endianness = DEVICE_NATIVE_ENDIAN, | |
204 | }; | |
205 | ||
c6205ddf | 206 | static void timerblock_reset(TimerBlock *tb) |
b9dc07d4 | 207 | { |
b9dc07d4 PM |
208 | tb->control = 0; |
209 | tb->status = 0; | |
bdac1c1e | 210 | if (tb->timer) { |
226fb5aa DO |
211 | ptimer_stop(tb->timer); |
212 | ptimer_set_limit(tb->timer, 0, 1); | |
213 | ptimer_set_period(tb->timer, timerblock_scale(0)); | |
bdac1c1e | 214 | } |
b9dc07d4 PM |
215 | } |
216 | ||
217 | static void arm_mptimer_reset(DeviceState *dev) | |
218 | { | |
68653fd6 | 219 | ARMMPTimerState *s = ARM_MPTIMER(dev); |
b9dc07d4 | 220 | int i; |
68653fd6 | 221 | |
b9dc07d4 PM |
222 | for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) { |
223 | timerblock_reset(&s->timerblock[i]); | |
224 | } | |
225 | } | |
226 | ||
0aadb490 | 227 | static void arm_mptimer_init(Object *obj) |
b9dc07d4 | 228 | { |
0aadb490 AF |
229 | ARMMPTimerState *s = ARM_MPTIMER(obj); |
230 | ||
231 | memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s, | |
232 | "arm_mptimer_timer", 0x20); | |
233 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); | |
234 | } | |
235 | ||
236 | static void arm_mptimer_realize(DeviceState *dev, Error **errp) | |
237 | { | |
238 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
68653fd6 | 239 | ARMMPTimerState *s = ARM_MPTIMER(dev); |
b9dc07d4 | 240 | int i; |
68653fd6 | 241 | |
eb110bd8 | 242 | if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) { |
b097e481 MA |
243 | error_setg(errp, "num-cpu must be between 1 and %d", |
244 | ARM_MPTIMER_MAX_CPUS); | |
245 | return; | |
b9dc07d4 | 246 | } |
cde4577f | 247 | /* We implement one timer block per CPU, and expose multiple MMIO regions: |
b9dc07d4 | 248 | * * region 0 is "timer for this core" |
cde4577f PC |
249 | * * region 1 is "timer for core 0" |
250 | * * region 2 is "timer for core 1" | |
b9dc07d4 PM |
251 | * and so on. |
252 | * The outgoing interrupt lines are | |
253 | * * timer for core 0 | |
b9dc07d4 | 254 | * * timer for core 1 |
b9dc07d4 PM |
255 | * and so on. |
256 | */ | |
cde4577f | 257 | for (i = 0; i < s->num_cpu; i++) { |
c6205ddf | 258 | TimerBlock *tb = &s->timerblock[i]; |
226fb5aa DO |
259 | QEMUBH *bh = qemu_bh_new(timerblock_tick, tb); |
260 | tb->timer = ptimer_init(bh, PTIMER_POLICY); | |
0aadb490 | 261 | sysbus_init_irq(sbd, &tb->irq); |
853dca12 | 262 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, |
b9dc07d4 | 263 | "arm_mptimer_timerblock", 0x20); |
0aadb490 | 264 | sysbus_init_mmio(sbd, &tb->iomem); |
b9dc07d4 | 265 | } |
b9dc07d4 PM |
266 | } |
267 | ||
268 | static const VMStateDescription vmstate_timerblock = { | |
269 | .name = "arm_mptimer_timerblock", | |
226fb5aa DO |
270 | .version_id = 3, |
271 | .minimum_version_id = 3, | |
b9dc07d4 | 272 | .fields = (VMStateField[]) { |
c6205ddf PC |
273 | VMSTATE_UINT32(control, TimerBlock), |
274 | VMSTATE_UINT32(status, TimerBlock), | |
226fb5aa | 275 | VMSTATE_PTIMER(timer, TimerBlock), |
b9dc07d4 PM |
276 | VMSTATE_END_OF_LIST() |
277 | } | |
278 | }; | |
279 | ||
280 | static const VMStateDescription vmstate_arm_mptimer = { | |
281 | .name = "arm_mptimer", | |
226fb5aa DO |
282 | .version_id = 3, |
283 | .minimum_version_id = 3, | |
b9dc07d4 | 284 | .fields = (VMStateField[]) { |
cde4577f | 285 | VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu, |
226fb5aa | 286 | 3, vmstate_timerblock, TimerBlock), |
b9dc07d4 PM |
287 | VMSTATE_END_OF_LIST() |
288 | } | |
289 | }; | |
290 | ||
39bffca2 | 291 | static Property arm_mptimer_properties[] = { |
c6205ddf | 292 | DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), |
39bffca2 AL |
293 | DEFINE_PROP_END_OF_LIST() |
294 | }; | |
295 | ||
999e12bb AL |
296 | static void arm_mptimer_class_init(ObjectClass *klass, void *data) |
297 | { | |
39bffca2 | 298 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 299 | |
0aadb490 | 300 | dc->realize = arm_mptimer_realize; |
39bffca2 AL |
301 | dc->vmsd = &vmstate_arm_mptimer; |
302 | dc->reset = arm_mptimer_reset; | |
39bffca2 | 303 | dc->props = arm_mptimer_properties; |
999e12bb AL |
304 | } |
305 | ||
8c43a6f0 | 306 | static const TypeInfo arm_mptimer_info = { |
68653fd6 | 307 | .name = TYPE_ARM_MPTIMER, |
39bffca2 | 308 | .parent = TYPE_SYS_BUS_DEVICE, |
c6205ddf | 309 | .instance_size = sizeof(ARMMPTimerState), |
0aadb490 | 310 | .instance_init = arm_mptimer_init, |
39bffca2 | 311 | .class_init = arm_mptimer_class_init, |
b9dc07d4 PM |
312 | }; |
313 | ||
83f7d43a | 314 | static void arm_mptimer_register_types(void) |
b9dc07d4 | 315 | { |
39bffca2 | 316 | type_register_static(&arm_mptimer_info); |
b9dc07d4 PM |
317 | } |
318 | ||
83f7d43a | 319 | type_init(arm_mptimer_register_types) |