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b9dc07d4 PM |
1 | /* |
2 | * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP | |
3 | * | |
4 | * Copyright (c) 2006-2007 CodeSourcery. | |
5 | * Copyright (c) 2011 Linaro Limited | |
6 | * Written by Paul Brook, Peter Maydell | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License | |
10 | * as published by the Free Software Foundation; either version | |
11 | * 2 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License along | |
19 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
20 | */ | |
21 | ||
83c9f4ca | 22 | #include "hw/sysbus.h" |
1de7afc9 | 23 | #include "qemu/timer.h" |
b9dc07d4 PM |
24 | |
25 | /* This device implements the per-cpu private timer and watchdog block | |
26 | * which is used in both the ARM11MPCore and Cortex-A9MP. | |
27 | */ | |
28 | ||
29 | #define MAX_CPUS 4 | |
30 | ||
31 | /* State of a single timer or watchdog block */ | |
32 | typedef struct { | |
33 | uint32_t count; | |
34 | uint32_t load; | |
35 | uint32_t control; | |
36 | uint32_t status; | |
37 | int64_t tick; | |
38 | QEMUTimer *timer; | |
39 | qemu_irq irq; | |
40 | MemoryRegion iomem; | |
c6205ddf | 41 | } TimerBlock; |
b9dc07d4 PM |
42 | |
43 | typedef struct { | |
44 | SysBusDevice busdev; | |
45 | uint32_t num_cpu; | |
cde4577f PC |
46 | TimerBlock timerblock[MAX_CPUS]; |
47 | MemoryRegion iomem; | |
c6205ddf | 48 | } ARMMPTimerState; |
b9dc07d4 | 49 | |
c6205ddf | 50 | static inline int get_current_cpu(ARMMPTimerState *s) |
b9dc07d4 | 51 | { |
4917cf44 | 52 | if (current_cpu->cpu_index >= s->num_cpu) { |
b9dc07d4 | 53 | hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n", |
4917cf44 | 54 | s->num_cpu, current_cpu->cpu_index); |
b9dc07d4 | 55 | } |
4917cf44 | 56 | return current_cpu->cpu_index; |
b9dc07d4 PM |
57 | } |
58 | ||
c6205ddf | 59 | static inline void timerblock_update_irq(TimerBlock *tb) |
b9dc07d4 PM |
60 | { |
61 | qemu_set_irq(tb->irq, tb->status); | |
62 | } | |
63 | ||
64 | /* Return conversion factor from mpcore timer ticks to qemu timer ticks. */ | |
c6205ddf | 65 | static inline uint32_t timerblock_scale(TimerBlock *tb) |
b9dc07d4 PM |
66 | { |
67 | return (((tb->control >> 8) & 0xff) + 1) * 10; | |
68 | } | |
69 | ||
c6205ddf | 70 | static void timerblock_reload(TimerBlock *tb, int restart) |
b9dc07d4 PM |
71 | { |
72 | if (tb->count == 0) { | |
73 | return; | |
74 | } | |
75 | if (restart) { | |
76 | tb->tick = qemu_get_clock_ns(vm_clock); | |
77 | } | |
78 | tb->tick += (int64_t)tb->count * timerblock_scale(tb); | |
79 | qemu_mod_timer(tb->timer, tb->tick); | |
80 | } | |
81 | ||
82 | static void timerblock_tick(void *opaque) | |
83 | { | |
c6205ddf | 84 | TimerBlock *tb = (TimerBlock *)opaque; |
b9dc07d4 PM |
85 | tb->status = 1; |
86 | if (tb->control & 2) { | |
87 | tb->count = tb->load; | |
88 | timerblock_reload(tb, 0); | |
89 | } else { | |
90 | tb->count = 0; | |
91 | } | |
92 | timerblock_update_irq(tb); | |
93 | } | |
94 | ||
a8170e5e | 95 | static uint64_t timerblock_read(void *opaque, hwaddr addr, |
b9dc07d4 PM |
96 | unsigned size) |
97 | { | |
c6205ddf | 98 | TimerBlock *tb = (TimerBlock *)opaque; |
b9dc07d4 | 99 | int64_t val; |
b9dc07d4 PM |
100 | switch (addr) { |
101 | case 0: /* Load */ | |
102 | return tb->load; | |
103 | case 4: /* Counter. */ | |
104 | if (((tb->control & 1) == 0) || (tb->count == 0)) { | |
105 | return 0; | |
106 | } | |
107 | /* Slow and ugly, but hopefully won't happen too often. */ | |
108 | val = tb->tick - qemu_get_clock_ns(vm_clock); | |
109 | val /= timerblock_scale(tb); | |
110 | if (val < 0) { | |
111 | val = 0; | |
112 | } | |
113 | return val; | |
114 | case 8: /* Control. */ | |
115 | return tb->control; | |
116 | case 12: /* Interrupt status. */ | |
117 | return tb->status; | |
118 | default: | |
119 | return 0; | |
120 | } | |
121 | } | |
122 | ||
a8170e5e | 123 | static void timerblock_write(void *opaque, hwaddr addr, |
b9dc07d4 PM |
124 | uint64_t value, unsigned size) |
125 | { | |
c6205ddf | 126 | TimerBlock *tb = (TimerBlock *)opaque; |
b9dc07d4 | 127 | int64_t old; |
b9dc07d4 PM |
128 | switch (addr) { |
129 | case 0: /* Load */ | |
130 | tb->load = value; | |
131 | /* Fall through. */ | |
132 | case 4: /* Counter. */ | |
133 | if ((tb->control & 1) && tb->count) { | |
134 | /* Cancel the previous timer. */ | |
135 | qemu_del_timer(tb->timer); | |
136 | } | |
137 | tb->count = value; | |
138 | if (tb->control & 1) { | |
139 | timerblock_reload(tb, 1); | |
140 | } | |
141 | break; | |
142 | case 8: /* Control. */ | |
143 | old = tb->control; | |
144 | tb->control = value; | |
145 | if (((old & 1) == 0) && (value & 1)) { | |
146 | if (tb->count == 0 && (tb->control & 2)) { | |
147 | tb->count = tb->load; | |
148 | } | |
149 | timerblock_reload(tb, 1); | |
150 | } | |
151 | break; | |
152 | case 12: /* Interrupt status. */ | |
153 | tb->status &= ~value; | |
154 | timerblock_update_irq(tb); | |
155 | break; | |
156 | } | |
157 | } | |
158 | ||
159 | /* Wrapper functions to implement the "read timer/watchdog for | |
160 | * the current CPU" memory regions. | |
161 | */ | |
a8170e5e | 162 | static uint64_t arm_thistimer_read(void *opaque, hwaddr addr, |
b9dc07d4 PM |
163 | unsigned size) |
164 | { | |
c6205ddf | 165 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
b9dc07d4 | 166 | int id = get_current_cpu(s); |
cde4577f | 167 | return timerblock_read(&s->timerblock[id], addr, size); |
b9dc07d4 PM |
168 | } |
169 | ||
a8170e5e | 170 | static void arm_thistimer_write(void *opaque, hwaddr addr, |
b9dc07d4 PM |
171 | uint64_t value, unsigned size) |
172 | { | |
c6205ddf | 173 | ARMMPTimerState *s = (ARMMPTimerState *)opaque; |
b9dc07d4 | 174 | int id = get_current_cpu(s); |
cde4577f | 175 | timerblock_write(&s->timerblock[id], addr, value, size); |
b9dc07d4 PM |
176 | } |
177 | ||
178 | static const MemoryRegionOps arm_thistimer_ops = { | |
179 | .read = arm_thistimer_read, | |
180 | .write = arm_thistimer_write, | |
181 | .valid = { | |
182 | .min_access_size = 4, | |
183 | .max_access_size = 4, | |
184 | }, | |
185 | .endianness = DEVICE_NATIVE_ENDIAN, | |
186 | }; | |
187 | ||
b9dc07d4 PM |
188 | static const MemoryRegionOps timerblock_ops = { |
189 | .read = timerblock_read, | |
190 | .write = timerblock_write, | |
191 | .valid = { | |
192 | .min_access_size = 4, | |
193 | .max_access_size = 4, | |
194 | }, | |
195 | .endianness = DEVICE_NATIVE_ENDIAN, | |
196 | }; | |
197 | ||
c6205ddf | 198 | static void timerblock_reset(TimerBlock *tb) |
b9dc07d4 PM |
199 | { |
200 | tb->count = 0; | |
201 | tb->load = 0; | |
202 | tb->control = 0; | |
203 | tb->status = 0; | |
204 | tb->tick = 0; | |
bdac1c1e PM |
205 | if (tb->timer) { |
206 | qemu_del_timer(tb->timer); | |
207 | } | |
b9dc07d4 PM |
208 | } |
209 | ||
210 | static void arm_mptimer_reset(DeviceState *dev) | |
211 | { | |
c6205ddf PC |
212 | ARMMPTimerState *s = |
213 | FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev)); | |
b9dc07d4 | 214 | int i; |
b9dc07d4 PM |
215 | for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) { |
216 | timerblock_reset(&s->timerblock[i]); | |
217 | } | |
218 | } | |
219 | ||
220 | static int arm_mptimer_init(SysBusDevice *dev) | |
221 | { | |
c6205ddf | 222 | ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev); |
b9dc07d4 PM |
223 | int i; |
224 | if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) { | |
225 | hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS); | |
226 | } | |
cde4577f | 227 | /* We implement one timer block per CPU, and expose multiple MMIO regions: |
b9dc07d4 | 228 | * * region 0 is "timer for this core" |
cde4577f PC |
229 | * * region 1 is "timer for core 0" |
230 | * * region 2 is "timer for core 1" | |
b9dc07d4 PM |
231 | * and so on. |
232 | * The outgoing interrupt lines are | |
233 | * * timer for core 0 | |
b9dc07d4 | 234 | * * timer for core 1 |
b9dc07d4 PM |
235 | * and so on. |
236 | */ | |
853dca12 | 237 | memory_region_init_io(&s->iomem, OBJECT(s), &arm_thistimer_ops, s, |
b9dc07d4 | 238 | "arm_mptimer_timer", 0x20); |
cde4577f PC |
239 | sysbus_init_mmio(dev, &s->iomem); |
240 | for (i = 0; i < s->num_cpu; i++) { | |
c6205ddf | 241 | TimerBlock *tb = &s->timerblock[i]; |
b9dc07d4 PM |
242 | tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb); |
243 | sysbus_init_irq(dev, &tb->irq); | |
853dca12 | 244 | memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb, |
b9dc07d4 PM |
245 | "arm_mptimer_timerblock", 0x20); |
246 | sysbus_init_mmio(dev, &tb->iomem); | |
247 | } | |
248 | ||
249 | return 0; | |
250 | } | |
251 | ||
252 | static const VMStateDescription vmstate_timerblock = { | |
253 | .name = "arm_mptimer_timerblock", | |
28092a23 PM |
254 | .version_id = 2, |
255 | .minimum_version_id = 2, | |
b9dc07d4 | 256 | .fields = (VMStateField[]) { |
c6205ddf PC |
257 | VMSTATE_UINT32(count, TimerBlock), |
258 | VMSTATE_UINT32(load, TimerBlock), | |
259 | VMSTATE_UINT32(control, TimerBlock), | |
260 | VMSTATE_UINT32(status, TimerBlock), | |
261 | VMSTATE_INT64(tick, TimerBlock), | |
28092a23 | 262 | VMSTATE_TIMER(timer, TimerBlock), |
b9dc07d4 PM |
263 | VMSTATE_END_OF_LIST() |
264 | } | |
265 | }; | |
266 | ||
267 | static const VMStateDescription vmstate_arm_mptimer = { | |
268 | .name = "arm_mptimer", | |
cde4577f PC |
269 | .version_id = 2, |
270 | .minimum_version_id = 2, | |
b9dc07d4 | 271 | .fields = (VMStateField[]) { |
cde4577f PC |
272 | VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu, |
273 | 2, vmstate_timerblock, TimerBlock), | |
b9dc07d4 PM |
274 | VMSTATE_END_OF_LIST() |
275 | } | |
276 | }; | |
277 | ||
39bffca2 | 278 | static Property arm_mptimer_properties[] = { |
c6205ddf | 279 | DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), |
39bffca2 AL |
280 | DEFINE_PROP_END_OF_LIST() |
281 | }; | |
282 | ||
999e12bb AL |
283 | static void arm_mptimer_class_init(ObjectClass *klass, void *data) |
284 | { | |
39bffca2 | 285 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
286 | SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); |
287 | ||
288 | sbc->init = arm_mptimer_init; | |
39bffca2 AL |
289 | dc->vmsd = &vmstate_arm_mptimer; |
290 | dc->reset = arm_mptimer_reset; | |
291 | dc->no_user = 1; | |
292 | dc->props = arm_mptimer_properties; | |
999e12bb AL |
293 | } |
294 | ||
8c43a6f0 | 295 | static const TypeInfo arm_mptimer_info = { |
39bffca2 AL |
296 | .name = "arm_mptimer", |
297 | .parent = TYPE_SYS_BUS_DEVICE, | |
c6205ddf | 298 | .instance_size = sizeof(ARMMPTimerState), |
39bffca2 | 299 | .class_init = arm_mptimer_class_init, |
b9dc07d4 PM |
300 | }; |
301 | ||
83f7d43a | 302 | static void arm_mptimer_register_types(void) |
b9dc07d4 | 303 | { |
39bffca2 | 304 | type_register_static(&arm_mptimer_info); |
b9dc07d4 PM |
305 | } |
306 | ||
83f7d43a | 307 | type_init(arm_mptimer_register_types) |