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Commit | Line | Data |
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5fafdf24 | 1 | /* |
cdbdb648 PB |
2 | * ARM PrimeCell Timer modules. |
3 | * | |
4 | * Copyright (c) 2005-2006 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
cdbdb648 PB |
8 | */ |
9 | ||
8ef94f0b | 10 | #include "qemu/osdep.h" |
83c9f4ca | 11 | #include "hw/sysbus.h" |
d6454270 | 12 | #include "migration/vmstate.h" |
1de7afc9 | 13 | #include "qemu/timer.h" |
64552b6b | 14 | #include "hw/irq.h" |
83c9f4ca | 15 | #include "hw/ptimer.h" |
a27bd6c7 | 16 | #include "hw/qdev-properties.h" |
6a1751b7 | 17 | #include "qemu/main-loop.h" |
0b8fa32f | 18 | #include "qemu/module.h" |
03dd024f | 19 | #include "qemu/log.h" |
cdbdb648 PB |
20 | |
21 | /* Common timer implementation. */ | |
22 | ||
23 | #define TIMER_CTRL_ONESHOT (1 << 0) | |
24 | #define TIMER_CTRL_32BIT (1 << 1) | |
25 | #define TIMER_CTRL_DIV1 (0 << 2) | |
26 | #define TIMER_CTRL_DIV16 (1 << 2) | |
27 | #define TIMER_CTRL_DIV256 (2 << 2) | |
28 | #define TIMER_CTRL_IE (1 << 5) | |
29 | #define TIMER_CTRL_PERIODIC (1 << 6) | |
30 | #define TIMER_CTRL_ENABLE (1 << 7) | |
31 | ||
32 | typedef struct { | |
423f0742 | 33 | ptimer_state *timer; |
cdbdb648 | 34 | uint32_t control; |
cdbdb648 | 35 | uint32_t limit; |
cdbdb648 PB |
36 | int freq; |
37 | int int_level; | |
d537cf6c | 38 | qemu_irq irq; |
cdbdb648 PB |
39 | } arm_timer_state; |
40 | ||
cdbdb648 PB |
41 | /* Check all active timers, and schedule the next timer interrupt. */ |
42 | ||
423f0742 | 43 | static void arm_timer_update(arm_timer_state *s) |
cdbdb648 | 44 | { |
cdbdb648 PB |
45 | /* Update interrupts. */ |
46 | if (s->int_level && (s->control & TIMER_CTRL_IE)) { | |
d537cf6c | 47 | qemu_irq_raise(s->irq); |
cdbdb648 | 48 | } else { |
d537cf6c | 49 | qemu_irq_lower(s->irq); |
cdbdb648 | 50 | } |
cdbdb648 PB |
51 | } |
52 | ||
a8170e5e | 53 | static uint32_t arm_timer_read(void *opaque, hwaddr offset) |
cdbdb648 PB |
54 | { |
55 | arm_timer_state *s = (arm_timer_state *)opaque; | |
56 | ||
57 | switch (offset >> 2) { | |
58 | case 0: /* TimerLoad */ | |
59 | case 6: /* TimerBGLoad */ | |
60 | return s->limit; | |
61 | case 1: /* TimerValue */ | |
423f0742 | 62 | return ptimer_get_count(s->timer); |
cdbdb648 PB |
63 | case 2: /* TimerControl */ |
64 | return s->control; | |
65 | case 4: /* TimerRIS */ | |
66 | return s->int_level; | |
67 | case 5: /* TimerMIS */ | |
68 | if ((s->control & TIMER_CTRL_IE) == 0) | |
69 | return 0; | |
70 | return s->int_level; | |
71 | default: | |
edb94a41 PM |
72 | qemu_log_mask(LOG_GUEST_ERROR, |
73 | "%s: Bad offset %x\n", __func__, (int)offset); | |
cdbdb648 PB |
74 | return 0; |
75 | } | |
76 | } | |
77 | ||
423f0742 PB |
78 | /* Reset the timer limit after settings have changed. */ |
79 | static void arm_timer_recalibrate(arm_timer_state *s, int reload) | |
80 | { | |
81 | uint32_t limit; | |
82 | ||
a9cf98d9 | 83 | if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { |
423f0742 PB |
84 | /* Free running. */ |
85 | if (s->control & TIMER_CTRL_32BIT) | |
86 | limit = 0xffffffff; | |
87 | else | |
88 | limit = 0xffff; | |
89 | } else { | |
90 | /* Periodic. */ | |
91 | limit = s->limit; | |
92 | } | |
93 | ptimer_set_limit(s->timer, limit, reload); | |
94 | } | |
95 | ||
a8170e5e | 96 | static void arm_timer_write(void *opaque, hwaddr offset, |
cdbdb648 PB |
97 | uint32_t value) |
98 | { | |
99 | arm_timer_state *s = (arm_timer_state *)opaque; | |
423f0742 | 100 | int freq; |
cdbdb648 | 101 | |
cdbdb648 PB |
102 | switch (offset >> 2) { |
103 | case 0: /* TimerLoad */ | |
104 | s->limit = value; | |
423f0742 | 105 | arm_timer_recalibrate(s, 1); |
cdbdb648 PB |
106 | break; |
107 | case 1: /* TimerValue */ | |
108 | /* ??? Linux seems to want to write to this readonly register. | |
109 | Ignore it. */ | |
110 | break; | |
111 | case 2: /* TimerControl */ | |
112 | if (s->control & TIMER_CTRL_ENABLE) { | |
113 | /* Pause the timer if it is running. This may cause some | |
114 | inaccuracy dure to rounding, but avoids a whole lot of other | |
115 | messyness. */ | |
423f0742 | 116 | ptimer_stop(s->timer); |
cdbdb648 PB |
117 | } |
118 | s->control = value; | |
423f0742 | 119 | freq = s->freq; |
cdbdb648 PB |
120 | /* ??? Need to recalculate expiry time after changing divisor. */ |
121 | switch ((value >> 2) & 3) { | |
423f0742 PB |
122 | case 1: freq >>= 4; break; |
123 | case 2: freq >>= 8; break; | |
cdbdb648 | 124 | } |
d6759902 | 125 | arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); |
423f0742 | 126 | ptimer_set_freq(s->timer, freq); |
cdbdb648 PB |
127 | if (s->control & TIMER_CTRL_ENABLE) { |
128 | /* Restart the timer if still enabled. */ | |
423f0742 | 129 | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); |
cdbdb648 PB |
130 | } |
131 | break; | |
132 | case 3: /* TimerIntClr */ | |
133 | s->int_level = 0; | |
134 | break; | |
135 | case 6: /* TimerBGLoad */ | |
136 | s->limit = value; | |
423f0742 | 137 | arm_timer_recalibrate(s, 0); |
cdbdb648 PB |
138 | break; |
139 | default: | |
edb94a41 PM |
140 | qemu_log_mask(LOG_GUEST_ERROR, |
141 | "%s: Bad offset %x\n", __func__, (int)offset); | |
cdbdb648 | 142 | } |
423f0742 | 143 | arm_timer_update(s); |
cdbdb648 PB |
144 | } |
145 | ||
146 | static void arm_timer_tick(void *opaque) | |
147 | { | |
423f0742 PB |
148 | arm_timer_state *s = (arm_timer_state *)opaque; |
149 | s->int_level = 1; | |
150 | arm_timer_update(s); | |
cdbdb648 PB |
151 | } |
152 | ||
eecd33a5 JQ |
153 | static const VMStateDescription vmstate_arm_timer = { |
154 | .name = "arm_timer", | |
155 | .version_id = 1, | |
156 | .minimum_version_id = 1, | |
8f1e884b | 157 | .fields = (VMStateField[]) { |
eecd33a5 JQ |
158 | VMSTATE_UINT32(control, arm_timer_state), |
159 | VMSTATE_UINT32(limit, arm_timer_state), | |
160 | VMSTATE_INT32(int_level, arm_timer_state), | |
161 | VMSTATE_PTIMER(timer, arm_timer_state), | |
162 | VMSTATE_END_OF_LIST() | |
163 | } | |
164 | }; | |
23e39294 | 165 | |
6a824ec3 | 166 | static arm_timer_state *arm_timer_init(uint32_t freq) |
cdbdb648 PB |
167 | { |
168 | arm_timer_state *s; | |
423f0742 | 169 | QEMUBH *bh; |
cdbdb648 | 170 | |
7267c094 | 171 | s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state)); |
423f0742 | 172 | s->freq = freq; |
cdbdb648 | 173 | s->control = TIMER_CTRL_IE; |
cdbdb648 | 174 | |
423f0742 | 175 | bh = qemu_bh_new(arm_timer_tick, s); |
e7ea81c3 | 176 | s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); |
eecd33a5 | 177 | vmstate_register(NULL, -1, &vmstate_arm_timer, s); |
cdbdb648 PB |
178 | return s; |
179 | } | |
180 | ||
181 | /* ARM PrimeCell SP804 dual timer module. | |
7b4252e8 PC |
182 | * Docs at |
183 | * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html | |
184 | */ | |
cdbdb648 | 185 | |
0c88dea5 AF |
186 | #define TYPE_SP804 "sp804" |
187 | #define SP804(obj) OBJECT_CHECK(SP804State, (obj), TYPE_SP804) | |
188 | ||
1024d7f0 | 189 | typedef struct SP804State { |
0c88dea5 AF |
190 | SysBusDevice parent_obj; |
191 | ||
e219dea2 | 192 | MemoryRegion iomem; |
6a824ec3 | 193 | arm_timer_state *timer[2]; |
104a26a2 | 194 | uint32_t freq0, freq1; |
cdbdb648 | 195 | int level[2]; |
d537cf6c | 196 | qemu_irq irq; |
1024d7f0 | 197 | } SP804State; |
cdbdb648 | 198 | |
7b4252e8 PC |
199 | static const uint8_t sp804_ids[] = { |
200 | /* Timer ID */ | |
201 | 0x04, 0x18, 0x14, 0, | |
202 | /* PrimeCell ID */ | |
203 | 0xd, 0xf0, 0x05, 0xb1 | |
204 | }; | |
205 | ||
d537cf6c | 206 | /* Merge the IRQs from the two component devices. */ |
cdbdb648 PB |
207 | static void sp804_set_irq(void *opaque, int irq, int level) |
208 | { | |
1024d7f0 | 209 | SP804State *s = (SP804State *)opaque; |
cdbdb648 PB |
210 | |
211 | s->level[irq] = level; | |
d537cf6c | 212 | qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
cdbdb648 PB |
213 | } |
214 | ||
a8170e5e | 215 | static uint64_t sp804_read(void *opaque, hwaddr offset, |
e219dea2 | 216 | unsigned size) |
cdbdb648 | 217 | { |
1024d7f0 | 218 | SP804State *s = (SP804State *)opaque; |
cdbdb648 | 219 | |
cdbdb648 PB |
220 | if (offset < 0x20) { |
221 | return arm_timer_read(s->timer[0], offset); | |
7b4252e8 PC |
222 | } |
223 | if (offset < 0x40) { | |
cdbdb648 PB |
224 | return arm_timer_read(s->timer[1], offset - 0x20); |
225 | } | |
7b4252e8 PC |
226 | |
227 | /* TimerPeriphID */ | |
228 | if (offset >= 0xfe0 && offset <= 0xffc) { | |
229 | return sp804_ids[(offset - 0xfe0) >> 2]; | |
230 | } | |
231 | ||
232 | switch (offset) { | |
233 | /* Integration Test control registers, which we won't support */ | |
234 | case 0xf00: /* TimerITCR */ | |
235 | case 0xf04: /* TimerITOP (strictly write only but..) */ | |
edb94a41 PM |
236 | qemu_log_mask(LOG_UNIMP, |
237 | "%s: integration test registers unimplemented\n", | |
238 | __func__); | |
7b4252e8 PC |
239 | return 0; |
240 | } | |
241 | ||
edb94a41 PM |
242 | qemu_log_mask(LOG_GUEST_ERROR, |
243 | "%s: Bad offset %x\n", __func__, (int)offset); | |
7b4252e8 | 244 | return 0; |
cdbdb648 PB |
245 | } |
246 | ||
a8170e5e | 247 | static void sp804_write(void *opaque, hwaddr offset, |
e219dea2 | 248 | uint64_t value, unsigned size) |
cdbdb648 | 249 | { |
1024d7f0 | 250 | SP804State *s = (SP804State *)opaque; |
cdbdb648 | 251 | |
cdbdb648 PB |
252 | if (offset < 0x20) { |
253 | arm_timer_write(s->timer[0], offset, value); | |
7b4252e8 PC |
254 | return; |
255 | } | |
256 | ||
257 | if (offset < 0x40) { | |
cdbdb648 | 258 | arm_timer_write(s->timer[1], offset - 0x20, value); |
7b4252e8 | 259 | return; |
cdbdb648 | 260 | } |
7b4252e8 PC |
261 | |
262 | /* Technically we could be writing to the Test Registers, but not likely */ | |
edb94a41 PM |
263 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", |
264 | __func__, (int)offset); | |
cdbdb648 PB |
265 | } |
266 | ||
e219dea2 AK |
267 | static const MemoryRegionOps sp804_ops = { |
268 | .read = sp804_read, | |
269 | .write = sp804_write, | |
270 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
271 | }; |
272 | ||
81986ac4 JQ |
273 | static const VMStateDescription vmstate_sp804 = { |
274 | .name = "sp804", | |
275 | .version_id = 1, | |
276 | .minimum_version_id = 1, | |
8f1e884b | 277 | .fields = (VMStateField[]) { |
1024d7f0 | 278 | VMSTATE_INT32_ARRAY(level, SP804State, 2), |
81986ac4 JQ |
279 | VMSTATE_END_OF_LIST() |
280 | } | |
281 | }; | |
23e39294 | 282 | |
0d175e74 | 283 | static void sp804_init(Object *obj) |
cdbdb648 | 284 | { |
0d175e74 XZ |
285 | SP804State *s = SP804(obj); |
286 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
cdbdb648 | 287 | |
0c88dea5 | 288 | sysbus_init_irq(sbd, &s->irq); |
0d175e74 XZ |
289 | memory_region_init_io(&s->iomem, obj, &sp804_ops, s, |
290 | "sp804", 0x1000); | |
291 | sysbus_init_mmio(sbd, &s->iomem); | |
292 | } | |
293 | ||
294 | static void sp804_realize(DeviceState *dev, Error **errp) | |
295 | { | |
296 | SP804State *s = SP804(dev); | |
297 | ||
104a26a2 ML |
298 | s->timer[0] = arm_timer_init(s->freq0); |
299 | s->timer[1] = arm_timer_init(s->freq1); | |
b6412724 SZ |
300 | s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); |
301 | s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); | |
cdbdb648 PB |
302 | } |
303 | ||
cdbdb648 PB |
304 | /* Integrator/CP timer module. */ |
305 | ||
e2051b42 AF |
306 | #define TYPE_INTEGRATOR_PIT "integrator_pit" |
307 | #define INTEGRATOR_PIT(obj) \ | |
308 | OBJECT_CHECK(icp_pit_state, (obj), TYPE_INTEGRATOR_PIT) | |
309 | ||
cdbdb648 | 310 | typedef struct { |
e2051b42 AF |
311 | SysBusDevice parent_obj; |
312 | ||
e219dea2 | 313 | MemoryRegion iomem; |
6a824ec3 | 314 | arm_timer_state *timer[3]; |
cdbdb648 PB |
315 | } icp_pit_state; |
316 | ||
a8170e5e | 317 | static uint64_t icp_pit_read(void *opaque, hwaddr offset, |
e219dea2 | 318 | unsigned size) |
cdbdb648 PB |
319 | { |
320 | icp_pit_state *s = (icp_pit_state *)opaque; | |
321 | int n; | |
322 | ||
323 | /* ??? Don't know the PrimeCell ID for this device. */ | |
cdbdb648 | 324 | n = offset >> 8; |
ee71c984 | 325 | if (n > 2) { |
edb94a41 | 326 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
cba933b2 | 327 | return 0; |
2ac71179 | 328 | } |
cdbdb648 PB |
329 | |
330 | return arm_timer_read(s->timer[n], offset & 0xff); | |
331 | } | |
332 | ||
a8170e5e | 333 | static void icp_pit_write(void *opaque, hwaddr offset, |
e219dea2 | 334 | uint64_t value, unsigned size) |
cdbdb648 PB |
335 | { |
336 | icp_pit_state *s = (icp_pit_state *)opaque; | |
337 | int n; | |
338 | ||
cdbdb648 | 339 | n = offset >> 8; |
ee71c984 | 340 | if (n > 2) { |
edb94a41 | 341 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
cba933b2 | 342 | return; |
2ac71179 | 343 | } |
cdbdb648 PB |
344 | |
345 | arm_timer_write(s->timer[n], offset & 0xff, value); | |
346 | } | |
347 | ||
e219dea2 AK |
348 | static const MemoryRegionOps icp_pit_ops = { |
349 | .read = icp_pit_read, | |
350 | .write = icp_pit_write, | |
351 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
352 | }; |
353 | ||
0d175e74 | 354 | static void icp_pit_init(Object *obj) |
cdbdb648 | 355 | { |
0d175e74 XZ |
356 | icp_pit_state *s = INTEGRATOR_PIT(obj); |
357 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
cdbdb648 | 358 | |
cdbdb648 | 359 | /* Timer 0 runs at the system clock speed (40MHz). */ |
6a824ec3 | 360 | s->timer[0] = arm_timer_init(40000000); |
cdbdb648 | 361 | /* The other two timers run at 1MHz. */ |
6a824ec3 PB |
362 | s->timer[1] = arm_timer_init(1000000); |
363 | s->timer[2] = arm_timer_init(1000000); | |
364 | ||
365 | sysbus_init_irq(dev, &s->timer[0]->irq); | |
366 | sysbus_init_irq(dev, &s->timer[1]->irq); | |
367 | sysbus_init_irq(dev, &s->timer[2]->irq); | |
cdbdb648 | 368 | |
0d175e74 | 369 | memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, |
853dca12 | 370 | "icp_pit", 0x1000); |
750ecd44 | 371 | sysbus_init_mmio(dev, &s->iomem); |
23e39294 PB |
372 | /* This device has no state to save/restore. The component timers will |
373 | save themselves. */ | |
999e12bb AL |
374 | } |
375 | ||
8c43a6f0 | 376 | static const TypeInfo icp_pit_info = { |
e2051b42 | 377 | .name = TYPE_INTEGRATOR_PIT, |
39bffca2 AL |
378 | .parent = TYPE_SYS_BUS_DEVICE, |
379 | .instance_size = sizeof(icp_pit_state), | |
0d175e74 | 380 | .instance_init = icp_pit_init, |
39bffca2 AL |
381 | }; |
382 | ||
383 | static Property sp804_properties[] = { | |
1024d7f0 AF |
384 | DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), |
385 | DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), | |
39bffca2 | 386 | DEFINE_PROP_END_OF_LIST(), |
999e12bb AL |
387 | }; |
388 | ||
389 | static void sp804_class_init(ObjectClass *klass, void *data) | |
390 | { | |
39bffca2 | 391 | DeviceClass *k = DEVICE_CLASS(klass); |
999e12bb | 392 | |
0d175e74 | 393 | k->realize = sp804_realize; |
39bffca2 | 394 | k->props = sp804_properties; |
d712a5a2 | 395 | k->vmsd = &vmstate_sp804; |
999e12bb AL |
396 | } |
397 | ||
8c43a6f0 | 398 | static const TypeInfo sp804_info = { |
0c88dea5 | 399 | .name = TYPE_SP804, |
39bffca2 | 400 | .parent = TYPE_SYS_BUS_DEVICE, |
1024d7f0 | 401 | .instance_size = sizeof(SP804State), |
0d175e74 | 402 | .instance_init = sp804_init, |
39bffca2 | 403 | .class_init = sp804_class_init, |
999e12bb AL |
404 | }; |
405 | ||
83f7d43a | 406 | static void arm_timer_register_types(void) |
6a824ec3 | 407 | { |
39bffca2 AL |
408 | type_register_static(&icp_pit_info); |
409 | type_register_static(&sp804_info); | |
6a824ec3 PB |
410 | } |
411 | ||
83f7d43a | 412 | type_init(arm_timer_register_types) |