]>
Commit | Line | Data |
---|---|---|
5fafdf24 | 1 | /* |
cdbdb648 PB |
2 | * ARM PrimeCell Timer modules. |
3 | * | |
4 | * Copyright (c) 2005-2006 CodeSourcery. | |
5 | * Written by Paul Brook | |
6 | * | |
8e31bf38 | 7 | * This code is licensed under the GPL. |
cdbdb648 PB |
8 | */ |
9 | ||
8ef94f0b | 10 | #include "qemu/osdep.h" |
83c9f4ca | 11 | #include "hw/sysbus.h" |
d6454270 | 12 | #include "migration/vmstate.h" |
1de7afc9 | 13 | #include "qemu/timer.h" |
64552b6b | 14 | #include "hw/irq.h" |
83c9f4ca | 15 | #include "hw/ptimer.h" |
a27bd6c7 | 16 | #include "hw/qdev-properties.h" |
0b8fa32f | 17 | #include "qemu/module.h" |
03dd024f | 18 | #include "qemu/log.h" |
db1015e9 | 19 | #include "qom/object.h" |
cdbdb648 PB |
20 | |
21 | /* Common timer implementation. */ | |
22 | ||
23 | #define TIMER_CTRL_ONESHOT (1 << 0) | |
24 | #define TIMER_CTRL_32BIT (1 << 1) | |
25 | #define TIMER_CTRL_DIV1 (0 << 2) | |
26 | #define TIMER_CTRL_DIV16 (1 << 2) | |
27 | #define TIMER_CTRL_DIV256 (2 << 2) | |
28 | #define TIMER_CTRL_IE (1 << 5) | |
29 | #define TIMER_CTRL_PERIODIC (1 << 6) | |
30 | #define TIMER_CTRL_ENABLE (1 << 7) | |
31 | ||
32 | typedef struct { | |
423f0742 | 33 | ptimer_state *timer; |
cdbdb648 | 34 | uint32_t control; |
cdbdb648 | 35 | uint32_t limit; |
cdbdb648 PB |
36 | int freq; |
37 | int int_level; | |
d537cf6c | 38 | qemu_irq irq; |
cdbdb648 PB |
39 | } arm_timer_state; |
40 | ||
cdbdb648 PB |
41 | /* Check all active timers, and schedule the next timer interrupt. */ |
42 | ||
423f0742 | 43 | static void arm_timer_update(arm_timer_state *s) |
cdbdb648 | 44 | { |
cdbdb648 PB |
45 | /* Update interrupts. */ |
46 | if (s->int_level && (s->control & TIMER_CTRL_IE)) { | |
d537cf6c | 47 | qemu_irq_raise(s->irq); |
cdbdb648 | 48 | } else { |
d537cf6c | 49 | qemu_irq_lower(s->irq); |
cdbdb648 | 50 | } |
cdbdb648 PB |
51 | } |
52 | ||
a8170e5e | 53 | static uint32_t arm_timer_read(void *opaque, hwaddr offset) |
cdbdb648 PB |
54 | { |
55 | arm_timer_state *s = (arm_timer_state *)opaque; | |
56 | ||
57 | switch (offset >> 2) { | |
58 | case 0: /* TimerLoad */ | |
59 | case 6: /* TimerBGLoad */ | |
60 | return s->limit; | |
61 | case 1: /* TimerValue */ | |
423f0742 | 62 | return ptimer_get_count(s->timer); |
cdbdb648 PB |
63 | case 2: /* TimerControl */ |
64 | return s->control; | |
65 | case 4: /* TimerRIS */ | |
66 | return s->int_level; | |
67 | case 5: /* TimerMIS */ | |
68 | if ((s->control & TIMER_CTRL_IE) == 0) | |
69 | return 0; | |
70 | return s->int_level; | |
71 | default: | |
edb94a41 PM |
72 | qemu_log_mask(LOG_GUEST_ERROR, |
73 | "%s: Bad offset %x\n", __func__, (int)offset); | |
cdbdb648 PB |
74 | return 0; |
75 | } | |
76 | } | |
77 | ||
5a65f7b5 PM |
78 | /* |
79 | * Reset the timer limit after settings have changed. | |
80 | * May only be called from inside a ptimer transaction block. | |
81 | */ | |
423f0742 PB |
82 | static void arm_timer_recalibrate(arm_timer_state *s, int reload) |
83 | { | |
84 | uint32_t limit; | |
85 | ||
a9cf98d9 | 86 | if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) { |
423f0742 PB |
87 | /* Free running. */ |
88 | if (s->control & TIMER_CTRL_32BIT) | |
89 | limit = 0xffffffff; | |
90 | else | |
91 | limit = 0xffff; | |
92 | } else { | |
93 | /* Periodic. */ | |
94 | limit = s->limit; | |
95 | } | |
96 | ptimer_set_limit(s->timer, limit, reload); | |
97 | } | |
98 | ||
a8170e5e | 99 | static void arm_timer_write(void *opaque, hwaddr offset, |
cdbdb648 PB |
100 | uint32_t value) |
101 | { | |
102 | arm_timer_state *s = (arm_timer_state *)opaque; | |
423f0742 | 103 | int freq; |
cdbdb648 | 104 | |
cdbdb648 PB |
105 | switch (offset >> 2) { |
106 | case 0: /* TimerLoad */ | |
107 | s->limit = value; | |
5a65f7b5 | 108 | ptimer_transaction_begin(s->timer); |
423f0742 | 109 | arm_timer_recalibrate(s, 1); |
5a65f7b5 | 110 | ptimer_transaction_commit(s->timer); |
cdbdb648 PB |
111 | break; |
112 | case 1: /* TimerValue */ | |
113 | /* ??? Linux seems to want to write to this readonly register. | |
114 | Ignore it. */ | |
115 | break; | |
116 | case 2: /* TimerControl */ | |
5a65f7b5 | 117 | ptimer_transaction_begin(s->timer); |
cdbdb648 PB |
118 | if (s->control & TIMER_CTRL_ENABLE) { |
119 | /* Pause the timer if it is running. This may cause some | |
120 | inaccuracy dure to rounding, but avoids a whole lot of other | |
121 | messyness. */ | |
423f0742 | 122 | ptimer_stop(s->timer); |
cdbdb648 PB |
123 | } |
124 | s->control = value; | |
423f0742 | 125 | freq = s->freq; |
cdbdb648 PB |
126 | /* ??? Need to recalculate expiry time after changing divisor. */ |
127 | switch ((value >> 2) & 3) { | |
423f0742 PB |
128 | case 1: freq >>= 4; break; |
129 | case 2: freq >>= 8; break; | |
cdbdb648 | 130 | } |
d6759902 | 131 | arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE); |
423f0742 | 132 | ptimer_set_freq(s->timer, freq); |
cdbdb648 PB |
133 | if (s->control & TIMER_CTRL_ENABLE) { |
134 | /* Restart the timer if still enabled. */ | |
423f0742 | 135 | ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0); |
cdbdb648 | 136 | } |
5a65f7b5 | 137 | ptimer_transaction_commit(s->timer); |
cdbdb648 PB |
138 | break; |
139 | case 3: /* TimerIntClr */ | |
140 | s->int_level = 0; | |
141 | break; | |
142 | case 6: /* TimerBGLoad */ | |
143 | s->limit = value; | |
5a65f7b5 | 144 | ptimer_transaction_begin(s->timer); |
423f0742 | 145 | arm_timer_recalibrate(s, 0); |
5a65f7b5 | 146 | ptimer_transaction_commit(s->timer); |
cdbdb648 PB |
147 | break; |
148 | default: | |
edb94a41 PM |
149 | qemu_log_mask(LOG_GUEST_ERROR, |
150 | "%s: Bad offset %x\n", __func__, (int)offset); | |
cdbdb648 | 151 | } |
423f0742 | 152 | arm_timer_update(s); |
cdbdb648 PB |
153 | } |
154 | ||
155 | static void arm_timer_tick(void *opaque) | |
156 | { | |
423f0742 PB |
157 | arm_timer_state *s = (arm_timer_state *)opaque; |
158 | s->int_level = 1; | |
159 | arm_timer_update(s); | |
cdbdb648 PB |
160 | } |
161 | ||
eecd33a5 JQ |
162 | static const VMStateDescription vmstate_arm_timer = { |
163 | .name = "arm_timer", | |
164 | .version_id = 1, | |
165 | .minimum_version_id = 1, | |
8f1e884b | 166 | .fields = (VMStateField[]) { |
eecd33a5 JQ |
167 | VMSTATE_UINT32(control, arm_timer_state), |
168 | VMSTATE_UINT32(limit, arm_timer_state), | |
169 | VMSTATE_INT32(int_level, arm_timer_state), | |
170 | VMSTATE_PTIMER(timer, arm_timer_state), | |
171 | VMSTATE_END_OF_LIST() | |
172 | } | |
173 | }; | |
23e39294 | 174 | |
6a824ec3 | 175 | static arm_timer_state *arm_timer_init(uint32_t freq) |
cdbdb648 PB |
176 | { |
177 | arm_timer_state *s; | |
178 | ||
b21e2380 | 179 | s = g_new0(arm_timer_state, 1); |
423f0742 | 180 | s->freq = freq; |
cdbdb648 | 181 | s->control = TIMER_CTRL_IE; |
cdbdb648 | 182 | |
5a65f7b5 | 183 | s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_DEFAULT); |
1df2c9a2 | 184 | vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); |
cdbdb648 PB |
185 | return s; |
186 | } | |
187 | ||
932a8d1f PM |
188 | /* |
189 | * ARM PrimeCell SP804 dual timer module. | |
7b4252e8 | 190 | * Docs at |
932a8d1f PM |
191 | * https://developer.arm.com/documentation/ddi0271/latest/ |
192 | */ | |
cdbdb648 | 193 | |
0c88dea5 | 194 | #define TYPE_SP804 "sp804" |
8063396b | 195 | OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804) |
0c88dea5 | 196 | |
db1015e9 | 197 | struct SP804State { |
0c88dea5 AF |
198 | SysBusDevice parent_obj; |
199 | ||
e219dea2 | 200 | MemoryRegion iomem; |
6a824ec3 | 201 | arm_timer_state *timer[2]; |
104a26a2 | 202 | uint32_t freq0, freq1; |
cdbdb648 | 203 | int level[2]; |
d537cf6c | 204 | qemu_irq irq; |
db1015e9 | 205 | }; |
cdbdb648 | 206 | |
7b4252e8 PC |
207 | static const uint8_t sp804_ids[] = { |
208 | /* Timer ID */ | |
209 | 0x04, 0x18, 0x14, 0, | |
210 | /* PrimeCell ID */ | |
211 | 0xd, 0xf0, 0x05, 0xb1 | |
212 | }; | |
213 | ||
d537cf6c | 214 | /* Merge the IRQs from the two component devices. */ |
cdbdb648 PB |
215 | static void sp804_set_irq(void *opaque, int irq, int level) |
216 | { | |
1024d7f0 | 217 | SP804State *s = (SP804State *)opaque; |
cdbdb648 PB |
218 | |
219 | s->level[irq] = level; | |
d537cf6c | 220 | qemu_set_irq(s->irq, s->level[0] || s->level[1]); |
cdbdb648 PB |
221 | } |
222 | ||
a8170e5e | 223 | static uint64_t sp804_read(void *opaque, hwaddr offset, |
e219dea2 | 224 | unsigned size) |
cdbdb648 | 225 | { |
1024d7f0 | 226 | SP804State *s = (SP804State *)opaque; |
cdbdb648 | 227 | |
cdbdb648 PB |
228 | if (offset < 0x20) { |
229 | return arm_timer_read(s->timer[0], offset); | |
7b4252e8 PC |
230 | } |
231 | if (offset < 0x40) { | |
cdbdb648 PB |
232 | return arm_timer_read(s->timer[1], offset - 0x20); |
233 | } | |
7b4252e8 PC |
234 | |
235 | /* TimerPeriphID */ | |
236 | if (offset >= 0xfe0 && offset <= 0xffc) { | |
237 | return sp804_ids[(offset - 0xfe0) >> 2]; | |
238 | } | |
239 | ||
240 | switch (offset) { | |
241 | /* Integration Test control registers, which we won't support */ | |
242 | case 0xf00: /* TimerITCR */ | |
243 | case 0xf04: /* TimerITOP (strictly write only but..) */ | |
edb94a41 PM |
244 | qemu_log_mask(LOG_UNIMP, |
245 | "%s: integration test registers unimplemented\n", | |
246 | __func__); | |
7b4252e8 PC |
247 | return 0; |
248 | } | |
249 | ||
edb94a41 PM |
250 | qemu_log_mask(LOG_GUEST_ERROR, |
251 | "%s: Bad offset %x\n", __func__, (int)offset); | |
7b4252e8 | 252 | return 0; |
cdbdb648 PB |
253 | } |
254 | ||
a8170e5e | 255 | static void sp804_write(void *opaque, hwaddr offset, |
e219dea2 | 256 | uint64_t value, unsigned size) |
cdbdb648 | 257 | { |
1024d7f0 | 258 | SP804State *s = (SP804State *)opaque; |
cdbdb648 | 259 | |
cdbdb648 PB |
260 | if (offset < 0x20) { |
261 | arm_timer_write(s->timer[0], offset, value); | |
7b4252e8 PC |
262 | return; |
263 | } | |
264 | ||
265 | if (offset < 0x40) { | |
cdbdb648 | 266 | arm_timer_write(s->timer[1], offset - 0x20, value); |
7b4252e8 | 267 | return; |
cdbdb648 | 268 | } |
7b4252e8 PC |
269 | |
270 | /* Technically we could be writing to the Test Registers, but not likely */ | |
edb94a41 PM |
271 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", |
272 | __func__, (int)offset); | |
cdbdb648 PB |
273 | } |
274 | ||
e219dea2 AK |
275 | static const MemoryRegionOps sp804_ops = { |
276 | .read = sp804_read, | |
277 | .write = sp804_write, | |
278 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
279 | }; |
280 | ||
81986ac4 JQ |
281 | static const VMStateDescription vmstate_sp804 = { |
282 | .name = "sp804", | |
283 | .version_id = 1, | |
284 | .minimum_version_id = 1, | |
8f1e884b | 285 | .fields = (VMStateField[]) { |
1024d7f0 | 286 | VMSTATE_INT32_ARRAY(level, SP804State, 2), |
81986ac4 JQ |
287 | VMSTATE_END_OF_LIST() |
288 | } | |
289 | }; | |
23e39294 | 290 | |
0d175e74 | 291 | static void sp804_init(Object *obj) |
cdbdb648 | 292 | { |
0d175e74 XZ |
293 | SP804State *s = SP804(obj); |
294 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); | |
cdbdb648 | 295 | |
0c88dea5 | 296 | sysbus_init_irq(sbd, &s->irq); |
0d175e74 XZ |
297 | memory_region_init_io(&s->iomem, obj, &sp804_ops, s, |
298 | "sp804", 0x1000); | |
299 | sysbus_init_mmio(sbd, &s->iomem); | |
300 | } | |
301 | ||
302 | static void sp804_realize(DeviceState *dev, Error **errp) | |
303 | { | |
304 | SP804State *s = SP804(dev); | |
305 | ||
104a26a2 ML |
306 | s->timer[0] = arm_timer_init(s->freq0); |
307 | s->timer[1] = arm_timer_init(s->freq1); | |
b6412724 SZ |
308 | s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); |
309 | s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); | |
cdbdb648 PB |
310 | } |
311 | ||
cdbdb648 PB |
312 | /* Integrator/CP timer module. */ |
313 | ||
e2051b42 | 314 | #define TYPE_INTEGRATOR_PIT "integrator_pit" |
8063396b | 315 | OBJECT_DECLARE_SIMPLE_TYPE(icp_pit_state, INTEGRATOR_PIT) |
e2051b42 | 316 | |
db1015e9 | 317 | struct icp_pit_state { |
e2051b42 AF |
318 | SysBusDevice parent_obj; |
319 | ||
e219dea2 | 320 | MemoryRegion iomem; |
6a824ec3 | 321 | arm_timer_state *timer[3]; |
db1015e9 | 322 | }; |
cdbdb648 | 323 | |
a8170e5e | 324 | static uint64_t icp_pit_read(void *opaque, hwaddr offset, |
e219dea2 | 325 | unsigned size) |
cdbdb648 PB |
326 | { |
327 | icp_pit_state *s = (icp_pit_state *)opaque; | |
328 | int n; | |
329 | ||
330 | /* ??? Don't know the PrimeCell ID for this device. */ | |
cdbdb648 | 331 | n = offset >> 8; |
ee71c984 | 332 | if (n > 2) { |
edb94a41 | 333 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
cba933b2 | 334 | return 0; |
2ac71179 | 335 | } |
cdbdb648 PB |
336 | |
337 | return arm_timer_read(s->timer[n], offset & 0xff); | |
338 | } | |
339 | ||
a8170e5e | 340 | static void icp_pit_write(void *opaque, hwaddr offset, |
e219dea2 | 341 | uint64_t value, unsigned size) |
cdbdb648 PB |
342 | { |
343 | icp_pit_state *s = (icp_pit_state *)opaque; | |
344 | int n; | |
345 | ||
cdbdb648 | 346 | n = offset >> 8; |
ee71c984 | 347 | if (n > 2) { |
edb94a41 | 348 | qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); |
cba933b2 | 349 | return; |
2ac71179 | 350 | } |
cdbdb648 PB |
351 | |
352 | arm_timer_write(s->timer[n], offset & 0xff, value); | |
353 | } | |
354 | ||
e219dea2 AK |
355 | static const MemoryRegionOps icp_pit_ops = { |
356 | .read = icp_pit_read, | |
357 | .write = icp_pit_write, | |
358 | .endianness = DEVICE_NATIVE_ENDIAN, | |
cdbdb648 PB |
359 | }; |
360 | ||
0d175e74 | 361 | static void icp_pit_init(Object *obj) |
cdbdb648 | 362 | { |
0d175e74 XZ |
363 | icp_pit_state *s = INTEGRATOR_PIT(obj); |
364 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
cdbdb648 | 365 | |
cdbdb648 | 366 | /* Timer 0 runs at the system clock speed (40MHz). */ |
6a824ec3 | 367 | s->timer[0] = arm_timer_init(40000000); |
cdbdb648 | 368 | /* The other two timers run at 1MHz. */ |
6a824ec3 PB |
369 | s->timer[1] = arm_timer_init(1000000); |
370 | s->timer[2] = arm_timer_init(1000000); | |
371 | ||
372 | sysbus_init_irq(dev, &s->timer[0]->irq); | |
373 | sysbus_init_irq(dev, &s->timer[1]->irq); | |
374 | sysbus_init_irq(dev, &s->timer[2]->irq); | |
cdbdb648 | 375 | |
0d175e74 | 376 | memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, |
853dca12 | 377 | "icp_pit", 0x1000); |
750ecd44 | 378 | sysbus_init_mmio(dev, &s->iomem); |
23e39294 PB |
379 | /* This device has no state to save/restore. The component timers will |
380 | save themselves. */ | |
999e12bb AL |
381 | } |
382 | ||
8c43a6f0 | 383 | static const TypeInfo icp_pit_info = { |
e2051b42 | 384 | .name = TYPE_INTEGRATOR_PIT, |
39bffca2 AL |
385 | .parent = TYPE_SYS_BUS_DEVICE, |
386 | .instance_size = sizeof(icp_pit_state), | |
0d175e74 | 387 | .instance_init = icp_pit_init, |
39bffca2 AL |
388 | }; |
389 | ||
390 | static Property sp804_properties[] = { | |
1024d7f0 AF |
391 | DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), |
392 | DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), | |
39bffca2 | 393 | DEFINE_PROP_END_OF_LIST(), |
999e12bb AL |
394 | }; |
395 | ||
396 | static void sp804_class_init(ObjectClass *klass, void *data) | |
397 | { | |
39bffca2 | 398 | DeviceClass *k = DEVICE_CLASS(klass); |
999e12bb | 399 | |
0d175e74 | 400 | k->realize = sp804_realize; |
4f67d30b | 401 | device_class_set_props(k, sp804_properties); |
d712a5a2 | 402 | k->vmsd = &vmstate_sp804; |
999e12bb AL |
403 | } |
404 | ||
8c43a6f0 | 405 | static const TypeInfo sp804_info = { |
0c88dea5 | 406 | .name = TYPE_SP804, |
39bffca2 | 407 | .parent = TYPE_SYS_BUS_DEVICE, |
1024d7f0 | 408 | .instance_size = sizeof(SP804State), |
0d175e74 | 409 | .instance_init = sp804_init, |
39bffca2 | 410 | .class_init = sp804_class_init, |
999e12bb AL |
411 | }; |
412 | ||
83f7d43a | 413 | static void arm_timer_register_types(void) |
6a824ec3 | 414 | { |
39bffca2 AL |
415 | type_register_static(&icp_pit_info); |
416 | type_register_static(&sp804_info); | |
6a824ec3 PB |
417 | } |
418 | ||
83f7d43a | 419 | type_init(arm_timer_register_types) |