[mirror_qemu.git] / hw / timer / etraxfs_timer.c

/*
 * QEMU ETRAX Timers
 *
 * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "qemu/main-loop.h"
#include "qemu/module.h"
#include "qemu/timer.h"
#include "hw/irq.h"
#include "hw/ptimer.h"

#define D(x)

#define RW_TMR0_DIV   0x00
#define R_TMR0_DATA   0x04
#define RW_TMR0_CTRL  0x08
#define RW_TMR1_DIV   0x10
#define R_TMR1_DATA   0x14
#define RW_TMR1_CTRL  0x18
#define R_TIME        0x38
#define RW_WD_CTRL    0x40
#define R_WD_STAT     0x44
#define RW_INTR_MASK  0x48
#define RW_ACK_INTR   0x4c
#define R_INTR        0x50
#define R_MASKED_INTR 0x54

#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
#define ETRAX_TIMER(obj) \
    OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)

typedef struct ETRAXTimerState {
    SysBusDevice parent_obj;

    MemoryRegion mmio;
    qemu_irq irq;
    qemu_irq nmi;

    QEMUBH *bh_t0;
    QEMUBH *bh_t1;
    QEMUBH *bh_wd;
    ptimer_state *ptimer_t0;
    ptimer_state *ptimer_t1;
    ptimer_state *ptimer_wd;

    int wd_hits;

    /* Control registers.  */
    uint32_t rw_tmr0_div;
    uint32_t r_tmr0_data;
    uint32_t rw_tmr0_ctrl;

    uint32_t rw_tmr1_div;
    uint32_t r_tmr1_data;
    uint32_t rw_tmr1_ctrl;

    uint32_t rw_wd_ctrl;

    uint32_t rw_intr_mask;
    uint32_t rw_ack_intr;
    uint32_t r_intr;
    uint32_t r_masked_intr;
} ETRAXTimerState;

static uint64_t
timer_read(void *opaque, hwaddr addr, unsigned int size)
{
    ETRAXTimerState *t = opaque;
    uint32_t r = 0;

    switch (addr) {
    case R_TMR0_DATA:
        r = ptimer_get_count(t->ptimer_t0);
        break;
    case R_TMR1_DATA:
        r = ptimer_get_count(t->ptimer_t1);
        break;
    case R_TIME:
        r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
        break;
    case RW_INTR_MASK:
        r = t->rw_intr_mask;
        break;
    case R_MASKED_INTR:
        r = t->r_intr & t->rw_intr_mask;
        break;
    default:
        D(printf ("%s %x\n", __func__, addr));
        break;
    }
    return r;
}

static void update_ctrl(ETRAXTimerState *t, int tnum)
{
    unsigned int op;
    unsigned int freq;
    unsigned int freq_hz;
    unsigned int div;
    uint32_t ctrl;

    ptimer_state *timer;

    if (tnum == 0) {
        ctrl = t->rw_tmr0_ctrl;
        div = t->rw_tmr0_div;
        timer = t->ptimer_t0;
    } else {
        ctrl = t->rw_tmr1_ctrl;
        div = t->rw_tmr1_div;
        timer = t->ptimer_t1;
    }


    op = ctrl & 3;
    freq = ctrl >> 2;
    freq_hz = 32000000;

    switch (freq)
    {
    case 0:
    case 1:
        D(printf ("extern or disabled timer clock?\n"));
        break;
    case 4: freq_hz =  29493000; break;
    case 5: freq_hz =  32000000; break;
    case 6: freq_hz =  32768000; break;
    case 7: freq_hz = 100000000; break;
    default:
        abort();
        break;
    }

    D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
    ptimer_set_freq(timer, freq_hz);
    ptimer_set_limit(timer, div, 0);

    switch (op)
    {
        case 0:
            /* Load.  */
            ptimer_set_limit(timer, div, 1);
            break;
        case 1:
            /* Hold.  */
            ptimer_stop(timer);
            break;
        case 2:
            /* Run.  */
            ptimer_run(timer, 0);
            break;
        default:
            abort();
            break;
    }
}

static void timer_update_irq(ETRAXTimerState *t)
{
    t->r_intr &= ~(t->rw_ack_intr);
    t->r_masked_intr = t->r_intr & t->rw_intr_mask;

    D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
    qemu_set_irq(t->irq, !!t->r_masked_intr);
}

static void timer0_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    t->r_intr |= 1;
    timer_update_irq(t);
}

static void timer1_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    t->r_intr |= 2;
    timer_update_irq(t);
}

static void watchdog_hit(void *opaque)
{
    ETRAXTimerState *t = opaque;
    if (t->wd_hits == 0) {
        /* real hw gives a single tick before reseting but we are
           a bit friendlier to compensate for our slower execution.  */
        ptimer_set_count(t->ptimer_wd, 10);
        ptimer_run(t->ptimer_wd, 1);
        qemu_irq_raise(t->nmi);
    }
    else
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

    t->wd_hits++;
}

static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
{
    unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
    unsigned int wd_key = t->rw_wd_ctrl >> 9;
    unsigned int wd_cnt = t->rw_wd_ctrl & 511;
    unsigned int new_key = value >> 9 & ((1 << 7) - 1);
    unsigned int new_cmd = (value >> 8) & 1;

    /* If the watchdog is enabled, they written key must match the
       complement of the previous.  */
    wd_key = ~wd_key & ((1 << 7) - 1);

    if (wd_en && wd_key != new_key)
        return;

    D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n", 
         wd_en, new_key, wd_key, new_cmd, wd_cnt));

    if (t->wd_hits)
        qemu_irq_lower(t->nmi);

    t->wd_hits = 0;

    ptimer_set_freq(t->ptimer_wd, 760);
    if (wd_cnt == 0)
        wd_cnt = 256;
    ptimer_set_count(t->ptimer_wd, wd_cnt);
    if (new_cmd)
        ptimer_run(t->ptimer_wd, 1);
    else
        ptimer_stop(t->ptimer_wd);

    t->rw_wd_ctrl = value;
}

static void
timer_write(void *opaque, hwaddr addr,
            uint64_t val64, unsigned int size)
{
    ETRAXTimerState *t = opaque;
    uint32_t value = val64;

    switch (addr)
    {
        case RW_TMR0_DIV:
            t->rw_tmr0_div = value;
            break;
        case RW_TMR0_CTRL:
            D(printf ("RW_TMR0_CTRL=%x\n", value));
            t->rw_tmr0_ctrl = value;
            update_ctrl(t, 0);
            break;
        case RW_TMR1_DIV:
            t->rw_tmr1_div = value;
            break;
        case RW_TMR1_CTRL:
            D(printf ("RW_TMR1_CTRL=%x\n", value));
            t->rw_tmr1_ctrl = value;
            update_ctrl(t, 1);
            break;
        case RW_INTR_MASK:
            D(printf ("RW_INTR_MASK=%x\n", value));
            t->rw_intr_mask = value;
            timer_update_irq(t);
            break;
        case RW_WD_CTRL:
            timer_watchdog_update(t, value);
            break;
        case RW_ACK_INTR:
            t->rw_ack_intr = value;
            timer_update_irq(t);
            t->rw_ack_intr = 0;
            break;
        default:
            printf ("%s " TARGET_FMT_plx " %x\n",
                __func__, addr, value);
            break;
    }
}

static const MemoryRegionOps timer_ops = {
    .read = timer_read,
    .write = timer_write,
    .endianness = DEVICE_LITTLE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4
    }
};

static void etraxfs_timer_reset(void *opaque)
{
    ETRAXTimerState *t = opaque;

    ptimer_stop(t->ptimer_t0);
    ptimer_stop(t->ptimer_t1);
    ptimer_stop(t->ptimer_wd);
    t->rw_wd_ctrl = 0;
    t->r_intr = 0;
    t->rw_intr_mask = 0;
    qemu_irq_lower(t->irq);
}

static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
{
    ETRAXTimerState *t = ETRAX_TIMER(dev);
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    t->bh_t0 = qemu_bh_new(timer0_hit, t);
    t->bh_t1 = qemu_bh_new(timer1_hit, t);
    t->bh_wd = qemu_bh_new(watchdog_hit, t);
    t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT);
    t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT);
    t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT);

    sysbus_init_irq(sbd, &t->irq);
    sysbus_init_irq(sbd, &t->nmi);

    memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
                          "etraxfs-timer", 0x5c);
    sysbus_init_mmio(sbd, &t->mmio);
    qemu_register_reset(etraxfs_timer_reset, t);
}

static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = etraxfs_timer_realize;
}

static const TypeInfo etraxfs_timer_info = {
    .name          = TYPE_ETRAX_FS_TIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ETRAXTimerState),
    .class_init    = etraxfs_timer_class_init,
};

static void etraxfs_timer_register_types(void)
{
    type_register_static(&etraxfs_timer_info);
}

type_init(etraxfs_timer_register_types)
Commit	Line	Data
83fa1010	1	/*
e62b5b13	2	* QEMU ETRAX Timers
83fa1010 TS	3	*
	4	* Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
0b8fa32f	24
282bc81e	25	#include "qemu/osdep.h"
83c9f4ca	26	#include "hw/sysbus.h"
71e8a915	27	#include "sysemu/reset.h"
54d31236	28	#include "sysemu/runstate.h"
db725815	29	#include "qemu/main-loop.h"
0b8fa32f	30	#include "qemu/module.h"
1de7afc9	31	#include "qemu/timer.h"
64552b6b	32	#include "hw/irq.h"
83c9f4ca	33	#include "hw/ptimer.h"
83fa1010	34
bbaf29c7 EI	35	#define D(x)
bbaf29c7 EI	36
ca87d03b EI	37	#define RW_TMR0_DIV 0x00
	38	#define R_TMR0_DATA 0x04
	39	#define RW_TMR0_CTRL 0x08
	40	#define RW_TMR1_DIV 0x10
	41	#define R_TMR1_DATA 0x14
	42	#define RW_TMR1_CTRL 0x18
	43	#define R_TIME 0x38
	44	#define RW_WD_CTRL 0x40
5439779e	45	#define R_WD_STAT 0x44
ca87d03b EI	46	#define RW_INTR_MASK 0x48
	47	#define RW_ACK_INTR 0x4c
	48	#define R_INTR 0x50
	49	#define R_MASKED_INTR 0x54
83fa1010	50
5880ce52 AF	51	#define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
	52	#define ETRAX_TIMER(obj) \
	53	OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
	54
3c9a8a8c	55	typedef struct ETRAXTimerState {
5880ce52 AF	56	SysBusDevice parent_obj;
5880ce52 AF	57
b8e5da2c	58	MemoryRegion mmio;
3b1fd90e EI	59	qemu_irq irq;
3b1fd90e EI	60	qemu_irq nmi;
84ceea57 EI	61
	62	QEMUBH *bh_t0;
	63	QEMUBH *bh_t1;
	64	QEMUBH *bh_wd;
	65	ptimer_state *ptimer_t0;
	66	ptimer_state *ptimer_t1;
	67	ptimer_state *ptimer_wd;
84ceea57 EI	68
	69	int wd_hits;
	70
	71	/* Control registers. */
	72	uint32_t rw_tmr0_div;
	73	uint32_t r_tmr0_data;
	74	uint32_t rw_tmr0_ctrl;
	75
	76	uint32_t rw_tmr1_div;
	77	uint32_t r_tmr1_data;
	78	uint32_t rw_tmr1_ctrl;
	79
	80	uint32_t rw_wd_ctrl;
	81
	82	uint32_t rw_intr_mask;
	83	uint32_t rw_ack_intr;
	84	uint32_t r_intr;
	85	uint32_t r_masked_intr;
3c9a8a8c	86	} ETRAXTimerState;
83fa1010	87
b8e5da2c	88	static uint64_t
a8170e5e	89	timer_read(void *opaque, hwaddr addr, unsigned int size)
83fa1010	90	{
3c9a8a8c	91	ETRAXTimerState *t = opaque;
84ceea57 EI	92	uint32_t r = 0;
	93
	94	switch (addr) {
	95	case R_TMR0_DATA:
	96	r = ptimer_get_count(t->ptimer_t0);
	97	break;
	98	case R_TMR1_DATA:
	99	r = ptimer_get_count(t->ptimer_t1);
	100	break;
	101	case R_TIME:
bc72ad67	102	r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
84ceea57 EI	103	break;
	104	case RW_INTR_MASK:
	105	r = t->rw_intr_mask;
	106	break;
	107	case R_MASKED_INTR:
	108	r = t->r_intr & t->rw_intr_mask;
	109	break;
	110	default:
	111	D(printf ("%s %x\n", __func__, addr));
	112	break;
	113	}
	114	return r;
83fa1010 TS	115	}
83fa1010 TS	116
3c9a8a8c	117	static void update_ctrl(ETRAXTimerState *t, int tnum)
83fa1010	118	{
84ceea57 EI	119	unsigned int op;
	120	unsigned int freq;
	121	unsigned int freq_hz;
	122	unsigned int div;
	123	uint32_t ctrl;
	124
	125	ptimer_state *timer;
	126
	127	if (tnum == 0) {
	128	ctrl = t->rw_tmr0_ctrl;
	129	div = t->rw_tmr0_div;
	130	timer = t->ptimer_t0;
	131	} else {
	132	ctrl = t->rw_tmr1_ctrl;
	133	div = t->rw_tmr1_div;
	134	timer = t->ptimer_t1;
	135	}
	136
	137
	138	op = ctrl & 3;
	139	freq = ctrl >> 2;
	140	freq_hz = 32000000;
	141
	142	switch (freq)
	143	{
	144	case 0:
	145	case 1:
	146	D(printf ("extern or disabled timer clock?\n"));
	147	break;
	148	case 4: freq_hz = 29493000; break;
	149	case 5: freq_hz = 32000000; break;
	150	case 6: freq_hz = 32768000; break;
	151	case 7: freq_hz = 100000000; break;
	152	default:
	153	abort();
	154	break;
	155	}
	156
	157	D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
84ceea57 EI	158	ptimer_set_freq(timer, freq_hz);
	159	ptimer_set_limit(timer, div, 0);
	160
	161	switch (op)
	162	{
	163	case 0:
	164	/* Load. */
	165	ptimer_set_limit(timer, div, 1);
	166	break;
	167	case 1:
	168	/* Hold. */
	169	ptimer_stop(timer);
	170	break;
	171	case 2:
	172	/* Run. */
	173	ptimer_run(timer, 0);
	174	break;
	175	default:
	176	abort();
	177	break;
	178	}
83fa1010 TS	179	}
83fa1010 TS	180
3c9a8a8c	181	static void timer_update_irq(ETRAXTimerState *t)
83fa1010	182	{
84ceea57 EI	183	t->r_intr &= ~(t->rw_ack_intr);
84ceea57 EI	184	t->r_masked_intr = t->r_intr & t->rw_intr_mask;
60237223	185
84ceea57	186	D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
3b1fd90e	187	qemu_set_irq(t->irq, !!t->r_masked_intr);
83fa1010 TS	188	}
83fa1010 TS	189
5439779e	190	static void timer0_hit(void *opaque)
60237223	191	{
3c9a8a8c	192	ETRAXTimerState *t = opaque;
84ceea57 EI	193	t->r_intr \|= 1;
84ceea57 EI	194	timer_update_irq(t);
60237223 EI	195	}
60237223 EI	196
5439779e EI	197	static void timer1_hit(void *opaque)
5439779e EI	198	{
3c9a8a8c	199	ETRAXTimerState *t = opaque;
84ceea57 EI	200	t->r_intr \|= 2;
84ceea57 EI	201	timer_update_irq(t);
5439779e EI	202	}
	203
	204	static void watchdog_hit(void *opaque)
	205	{
3c9a8a8c	206	ETRAXTimerState *t = opaque;
84ceea57 EI	207	if (t->wd_hits == 0) {
	208	/* real hw gives a single tick before reseting but we are
	209	a bit friendlier to compensate for our slower execution. */
	210	ptimer_set_count(t->ptimer_wd, 10);
	211	ptimer_run(t->ptimer_wd, 1);
3b1fd90e	212	qemu_irq_raise(t->nmi);
84ceea57 EI	213	}
84ceea57 EI	214	else
cf83f140	215	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
84ceea57 EI	216
84ceea57 EI	217	t->wd_hits++;
5439779e EI	218	}
5439779e EI	219
3c9a8a8c	220	static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
5439779e	221	{
84ceea57 EI	222	unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
	223	unsigned int wd_key = t->rw_wd_ctrl >> 9;
	224	unsigned int wd_cnt = t->rw_wd_ctrl & 511;
	225	unsigned int new_key = value >> 9 & ((1 << 7) - 1);
	226	unsigned int new_cmd = (value >> 8) & 1;
5439779e	227
84ceea57 EI	228	/* If the watchdog is enabled, they written key must match the
	229	complement of the previous. */
	230	wd_key = ~wd_key & ((1 << 7) - 1);
5439779e	231
84ceea57 EI	232	if (wd_en && wd_key != new_key)
84ceea57 EI	233	return;
5439779e	234
84ceea57 EI	235	D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
84ceea57 EI	236	wd_en, new_key, wd_key, new_cmd, wd_cnt));
5439779e	237
84ceea57	238	if (t->wd_hits)
3b1fd90e	239	qemu_irq_lower(t->nmi);
5ef98b47	240
84ceea57	241	t->wd_hits = 0;
5ef98b47	242
84ceea57 EI	243	ptimer_set_freq(t->ptimer_wd, 760);
	244	if (wd_cnt == 0)
	245	wd_cnt = 256;
	246	ptimer_set_count(t->ptimer_wd, wd_cnt);
	247	if (new_cmd)
	248	ptimer_run(t->ptimer_wd, 1);
	249	else
	250	ptimer_stop(t->ptimer_wd);
5439779e	251
84ceea57	252	t->rw_wd_ctrl = value;
5439779e EI	253	}
5439779e EI	254
83fa1010	255	static void
a8170e5e	256	timer_write(void *opaque, hwaddr addr,
b8e5da2c	257	uint64_t val64, unsigned int size)
83fa1010	258	{
3c9a8a8c	259	ETRAXTimerState *t = opaque;
b8e5da2c	260	uint32_t value = val64;
84ceea57 EI	261
	262	switch (addr)
	263	{
	264	case RW_TMR0_DIV:
	265	t->rw_tmr0_div = value;
	266	break;
	267	case RW_TMR0_CTRL:
	268	D(printf ("RW_TMR0_CTRL=%x\n", value));
	269	t->rw_tmr0_ctrl = value;
	270	update_ctrl(t, 0);
	271	break;
	272	case RW_TMR1_DIV:
	273	t->rw_tmr1_div = value;
	274	break;
	275	case RW_TMR1_CTRL:
	276	D(printf ("RW_TMR1_CTRL=%x\n", value));
	277	t->rw_tmr1_ctrl = value;
	278	update_ctrl(t, 1);
	279	break;
	280	case RW_INTR_MASK:
	281	D(printf ("RW_INTR_MASK=%x\n", value));
	282	t->rw_intr_mask = value;
	283	timer_update_irq(t);
	284	break;
	285	case RW_WD_CTRL:
	286	timer_watchdog_update(t, value);
	287	break;
	288	case RW_ACK_INTR:
	289	t->rw_ack_intr = value;
	290	timer_update_irq(t);
	291	t->rw_ack_intr = 0;
	292	break;
	293	default:
	294	printf ("%s " TARGET_FMT_plx " %x\n",
	295	__func__, addr, value);
	296	break;
	297	}
83fa1010 TS	298	}
83fa1010 TS	299
b8e5da2c EI	300	static const MemoryRegionOps timer_ops = {
	301	.read = timer_read,
	302	.write = timer_write,
	303	.endianness = DEVICE_LITTLE_ENDIAN,
	304	.valid = {
	305	.min_access_size = 4,
	306	.max_access_size = 4
	307	}
83fa1010 TS	308	};
83fa1010 TS	309
5439779e EI	310	static void etraxfs_timer_reset(void *opaque)
5439779e EI	311	{
3c9a8a8c	312	ETRAXTimerState *t = opaque;
84ceea57 EI	313
	314	ptimer_stop(t->ptimer_t0);
	315	ptimer_stop(t->ptimer_t1);
	316	ptimer_stop(t->ptimer_wd);
	317	t->rw_wd_ctrl = 0;
	318	t->r_intr = 0;
	319	t->rw_intr_mask = 0;
3b1fd90e	320	qemu_irq_lower(t->irq);
5439779e EI	321	}
5439779e EI	322
34a598f6	323	static void etraxfs_timer_realize(DeviceState dev, Error *errp)
83fa1010	324	{
5880ce52	325	ETRAXTimerState *t = ETRAX_TIMER(dev);
34a598f6	326	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
83fa1010	327
84ceea57 EI	328	t->bh_t0 = qemu_bh_new(timer0_hit, t);
	329	t->bh_t1 = qemu_bh_new(timer1_hit, t);
	330	t->bh_wd = qemu_bh_new(watchdog_hit, t);
b0142262 PM	331	t->ptimer_t0 = ptimer_init_with_bh(t->bh_t0, PTIMER_POLICY_DEFAULT);
	332	t->ptimer_t1 = ptimer_init_with_bh(t->bh_t1, PTIMER_POLICY_DEFAULT);
	333	t->ptimer_wd = ptimer_init_with_bh(t->bh_wd, PTIMER_POLICY_DEFAULT);
3b1fd90e	334
34a598f6 MZ	335	sysbus_init_irq(sbd, &t->irq);
34a598f6 MZ	336	sysbus_init_irq(sbd, &t->nmi);
83fa1010	337
853dca12 PB	338	memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
853dca12 PB	339	"etraxfs-timer", 0x5c);
34a598f6	340	sysbus_init_mmio(sbd, &t->mmio);
a08d4367	341	qemu_register_reset(etraxfs_timer_reset, t);
83fa1010	342	}
3b1fd90e	343
999e12bb AL	344	static void etraxfs_timer_class_init(ObjectClass klass, void data)
999e12bb AL	345	{
34a598f6	346	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	347
34a598f6	348	dc->realize = etraxfs_timer_realize;
999e12bb AL	349	}
999e12bb AL	350
8c43a6f0	351	static const TypeInfo etraxfs_timer_info = {
5880ce52	352	.name = TYPE_ETRAX_FS_TIMER,
39bffca2	353	.parent = TYPE_SYS_BUS_DEVICE,
3c9a8a8c	354	.instance_size = sizeof(ETRAXTimerState),
39bffca2	355	.class_init = etraxfs_timer_class_init,
999e12bb AL	356	};
999e12bb AL	357
83f7d43a	358	static void etraxfs_timer_register_types(void)
3b1fd90e	359	{
39bffca2	360	type_register_static(&etraxfs_timer_info);
3b1fd90e EI	361	}
3b1fd90e EI	362
83f7d43a	363	type_init(etraxfs_timer_register_types)