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62db8bf3 EV |
1 | /* |
2 | * Samsung exynos4210 Pulse Width Modulation Timer | |
3 | * | |
4 | * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. | |
5 | * All rights reserved. | |
6 | * | |
7 | * Evgeny Voevodin <e.voevodin@samsung.com> | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify it | |
10 | * under the terms of the GNU General Public License as published by the | |
11 | * Free Software Foundation; either version 2 of the License, or (at your | |
12 | * option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. | |
17 | * See the GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License along | |
20 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
21 | */ | |
22 | ||
8ef94f0b | 23 | #include "qemu/osdep.h" |
83c9f4ca | 24 | #include "hw/sysbus.h" |
1de7afc9 | 25 | #include "qemu/timer.h" |
62db8bf3 | 26 | #include "qemu-common.h" |
6a1751b7 | 27 | #include "qemu/main-loop.h" |
83c9f4ca | 28 | #include "hw/ptimer.h" |
62db8bf3 | 29 | |
0d09e41a | 30 | #include "hw/arm/exynos4210.h" |
62db8bf3 EV |
31 | |
32 | //#define DEBUG_PWM | |
33 | ||
34 | #ifdef DEBUG_PWM | |
35 | #define DPRINTF(fmt, ...) \ | |
36 | do { fprintf(stdout, "PWM: [%24s:%5d] " fmt, __func__, __LINE__, \ | |
37 | ## __VA_ARGS__); } while (0) | |
38 | #else | |
39 | #define DPRINTF(fmt, ...) do {} while (0) | |
40 | #endif | |
41 | ||
42 | #define EXYNOS4210_PWM_TIMERS_NUM 5 | |
43 | #define EXYNOS4210_PWM_REG_MEM_SIZE 0x50 | |
44 | ||
45 | #define TCFG0 0x0000 | |
46 | #define TCFG1 0x0004 | |
47 | #define TCON 0x0008 | |
48 | #define TCNTB0 0x000C | |
49 | #define TCMPB0 0x0010 | |
50 | #define TCNTO0 0x0014 | |
51 | #define TCNTB1 0x0018 | |
52 | #define TCMPB1 0x001C | |
53 | #define TCNTO1 0x0020 | |
54 | #define TCNTB2 0x0024 | |
55 | #define TCMPB2 0x0028 | |
56 | #define TCNTO2 0x002C | |
57 | #define TCNTB3 0x0030 | |
58 | #define TCMPB3 0x0034 | |
59 | #define TCNTO3 0x0038 | |
60 | #define TCNTB4 0x003C | |
61 | #define TCNTO4 0x0040 | |
62 | #define TINT_CSTAT 0x0044 | |
63 | ||
64 | #define TCNTB(x) (0xC * (x)) | |
65 | #define TCMPB(x) (0xC * (x) + 1) | |
66 | #define TCNTO(x) (0xC * (x) + 2) | |
67 | ||
68 | #define GET_PRESCALER(reg, x) (((reg) & (0xFF << (8 * (x)))) >> 8 * (x)) | |
69 | #define GET_DIVIDER(reg, x) (1 << (((reg) & (0xF << (4 * (x)))) >> (4 * (x)))) | |
70 | ||
71 | /* | |
72 | * Attention! Timer4 doesn't have OUTPUT_INVERTER, | |
73 | * so Auto Reload bit is not accessible by macros! | |
74 | */ | |
75 | #define TCON_TIMER_BASE(x) (((x) ? 1 : 0) * 4 + 4 * (x)) | |
76 | #define TCON_TIMER_START(x) (1 << (TCON_TIMER_BASE(x) + 0)) | |
77 | #define TCON_TIMER_MANUAL_UPD(x) (1 << (TCON_TIMER_BASE(x) + 1)) | |
78 | #define TCON_TIMER_OUTPUT_INV(x) (1 << (TCON_TIMER_BASE(x) + 2)) | |
79 | #define TCON_TIMER_AUTO_RELOAD(x) (1 << (TCON_TIMER_BASE(x) + 3)) | |
80 | #define TCON_TIMER4_AUTO_RELOAD (1 << 22) | |
81 | ||
82 | #define TINT_CSTAT_STATUS(x) (1 << (5 + (x))) | |
83 | #define TINT_CSTAT_ENABLE(x) (1 << (x)) | |
84 | ||
85 | /* timer struct */ | |
86 | typedef struct { | |
87 | uint32_t id; /* timer id */ | |
88 | qemu_irq irq; /* local timer irq */ | |
89 | uint32_t freq; /* timer frequency */ | |
90 | ||
91 | /* use ptimer.c to represent count down timer */ | |
92 | ptimer_state *ptimer; /* timer */ | |
93 | ||
94 | /* registers */ | |
95 | uint32_t reg_tcntb; /* counter register buffer */ | |
96 | uint32_t reg_tcmpb; /* compare register buffer */ | |
97 | ||
98 | struct Exynos4210PWMState *parent; | |
99 | ||
100 | } Exynos4210PWM; | |
101 | ||
25fce9ad AF |
102 | #define TYPE_EXYNOS4210_PWM "exynos4210.pwm" |
103 | #define EXYNOS4210_PWM(obj) \ | |
104 | OBJECT_CHECK(Exynos4210PWMState, (obj), TYPE_EXYNOS4210_PWM) | |
62db8bf3 EV |
105 | |
106 | typedef struct Exynos4210PWMState { | |
25fce9ad AF |
107 | SysBusDevice parent_obj; |
108 | ||
62db8bf3 EV |
109 | MemoryRegion iomem; |
110 | ||
111 | uint32_t reg_tcfg[2]; | |
112 | uint32_t reg_tcon; | |
113 | uint32_t reg_tint_cstat; | |
114 | ||
115 | Exynos4210PWM timer[EXYNOS4210_PWM_TIMERS_NUM]; | |
116 | ||
117 | } Exynos4210PWMState; | |
118 | ||
119 | /*** VMState ***/ | |
120 | static const VMStateDescription vmstate_exynos4210_pwm = { | |
121 | .name = "exynos4210.pwm.pwm", | |
122 | .version_id = 1, | |
123 | .minimum_version_id = 1, | |
62db8bf3 EV |
124 | .fields = (VMStateField[]) { |
125 | VMSTATE_UINT32(id, Exynos4210PWM), | |
126 | VMSTATE_UINT32(freq, Exynos4210PWM), | |
127 | VMSTATE_PTIMER(ptimer, Exynos4210PWM), | |
128 | VMSTATE_UINT32(reg_tcntb, Exynos4210PWM), | |
129 | VMSTATE_UINT32(reg_tcmpb, Exynos4210PWM), | |
130 | VMSTATE_END_OF_LIST() | |
131 | } | |
132 | }; | |
133 | ||
134 | static const VMStateDescription vmstate_exynos4210_pwm_state = { | |
135 | .name = "exynos4210.pwm", | |
136 | .version_id = 1, | |
137 | .minimum_version_id = 1, | |
62db8bf3 EV |
138 | .fields = (VMStateField[]) { |
139 | VMSTATE_UINT32_ARRAY(reg_tcfg, Exynos4210PWMState, 2), | |
140 | VMSTATE_UINT32(reg_tcon, Exynos4210PWMState), | |
141 | VMSTATE_UINT32(reg_tint_cstat, Exynos4210PWMState), | |
142 | VMSTATE_STRUCT_ARRAY(timer, Exynos4210PWMState, | |
143 | EXYNOS4210_PWM_TIMERS_NUM, 0, | |
144 | vmstate_exynos4210_pwm, Exynos4210PWM), | |
145 | VMSTATE_END_OF_LIST() | |
146 | } | |
147 | }; | |
148 | ||
149 | /* | |
150 | * PWM update frequency | |
151 | */ | |
152 | static void exynos4210_pwm_update_freq(Exynos4210PWMState *s, uint32_t id) | |
153 | { | |
154 | uint32_t freq; | |
155 | freq = s->timer[id].freq; | |
156 | if (id > 1) { | |
157 | s->timer[id].freq = 24000000 / | |
158 | ((GET_PRESCALER(s->reg_tcfg[0], 1) + 1) * | |
159 | (GET_DIVIDER(s->reg_tcfg[1], id))); | |
160 | } else { | |
161 | s->timer[id].freq = 24000000 / | |
162 | ((GET_PRESCALER(s->reg_tcfg[0], 0) + 1) * | |
163 | (GET_DIVIDER(s->reg_tcfg[1], id))); | |
164 | } | |
165 | ||
166 | if (freq != s->timer[id].freq) { | |
167 | ptimer_set_freq(s->timer[id].ptimer, s->timer[id].freq); | |
168 | DPRINTF("freq=%dHz\n", s->timer[id].freq); | |
169 | } | |
170 | } | |
171 | ||
172 | /* | |
173 | * Counter tick handler | |
174 | */ | |
175 | static void exynos4210_pwm_tick(void *opaque) | |
176 | { | |
177 | Exynos4210PWM *s = (Exynos4210PWM *)opaque; | |
178 | Exynos4210PWMState *p = (Exynos4210PWMState *)s->parent; | |
179 | uint32_t id = s->id; | |
180 | bool cmp; | |
181 | ||
182 | DPRINTF("timer %d tick\n", id); | |
183 | ||
184 | /* set irq status */ | |
185 | p->reg_tint_cstat |= TINT_CSTAT_STATUS(id); | |
186 | ||
187 | /* raise IRQ */ | |
188 | if (p->reg_tint_cstat & TINT_CSTAT_ENABLE(id)) { | |
189 | DPRINTF("timer %d IRQ\n", id); | |
190 | qemu_irq_raise(p->timer[id].irq); | |
191 | } | |
192 | ||
193 | /* reload timer */ | |
194 | if (id != 4) { | |
195 | cmp = p->reg_tcon & TCON_TIMER_AUTO_RELOAD(id); | |
196 | } else { | |
197 | cmp = p->reg_tcon & TCON_TIMER4_AUTO_RELOAD; | |
198 | } | |
199 | ||
200 | if (cmp) { | |
201 | DPRINTF("auto reload timer %d count to %x\n", id, | |
202 | p->timer[id].reg_tcntb); | |
203 | ptimer_set_count(p->timer[id].ptimer, p->timer[id].reg_tcntb); | |
204 | ptimer_run(p->timer[id].ptimer, 1); | |
205 | } else { | |
206 | /* stop timer, set status to STOP, see Basic Timer Operation */ | |
b631bc37 | 207 | p->reg_tcon &= ~TCON_TIMER_START(id); |
62db8bf3 EV |
208 | ptimer_stop(p->timer[id].ptimer); |
209 | } | |
210 | } | |
211 | ||
212 | /* | |
213 | * PWM Read | |
214 | */ | |
a8170e5e | 215 | static uint64_t exynos4210_pwm_read(void *opaque, hwaddr offset, |
62db8bf3 EV |
216 | unsigned size) |
217 | { | |
218 | Exynos4210PWMState *s = (Exynos4210PWMState *)opaque; | |
219 | uint32_t value = 0; | |
220 | int index; | |
221 | ||
222 | switch (offset) { | |
223 | case TCFG0: case TCFG1: | |
224 | index = (offset - TCFG0) >> 2; | |
225 | value = s->reg_tcfg[index]; | |
226 | break; | |
227 | ||
228 | case TCON: | |
229 | value = s->reg_tcon; | |
230 | break; | |
231 | ||
232 | case TCNTB0: case TCNTB1: | |
233 | case TCNTB2: case TCNTB3: case TCNTB4: | |
234 | index = (offset - TCNTB0) / 0xC; | |
235 | value = s->timer[index].reg_tcntb; | |
236 | break; | |
237 | ||
238 | case TCMPB0: case TCMPB1: | |
239 | case TCMPB2: case TCMPB3: | |
240 | index = (offset - TCMPB0) / 0xC; | |
241 | value = s->timer[index].reg_tcmpb; | |
242 | break; | |
243 | ||
244 | case TCNTO0: case TCNTO1: | |
245 | case TCNTO2: case TCNTO3: case TCNTO4: | |
246 | index = (offset == TCNTO4) ? 4 : (offset - TCNTO0) / 0xC; | |
247 | value = ptimer_get_count(s->timer[index].ptimer); | |
248 | break; | |
249 | ||
250 | case TINT_CSTAT: | |
251 | value = s->reg_tint_cstat; | |
252 | break; | |
253 | ||
254 | default: | |
255 | fprintf(stderr, | |
256 | "[exynos4210.pwm: bad read offset " TARGET_FMT_plx "]\n", | |
257 | offset); | |
258 | break; | |
259 | } | |
260 | return value; | |
261 | } | |
262 | ||
263 | /* | |
264 | * PWM Write | |
265 | */ | |
a8170e5e | 266 | static void exynos4210_pwm_write(void *opaque, hwaddr offset, |
62db8bf3 EV |
267 | uint64_t value, unsigned size) |
268 | { | |
269 | Exynos4210PWMState *s = (Exynos4210PWMState *)opaque; | |
270 | int index; | |
271 | uint32_t new_val; | |
272 | int i; | |
273 | ||
274 | switch (offset) { | |
275 | case TCFG0: case TCFG1: | |
276 | index = (offset - TCFG0) >> 2; | |
277 | s->reg_tcfg[index] = value; | |
278 | ||
279 | /* update timers frequencies */ | |
280 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | |
281 | exynos4210_pwm_update_freq(s, s->timer[i].id); | |
282 | } | |
283 | break; | |
284 | ||
285 | case TCON: | |
286 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | |
287 | if ((value & TCON_TIMER_MANUAL_UPD(i)) > | |
288 | (s->reg_tcon & TCON_TIMER_MANUAL_UPD(i))) { | |
289 | /* | |
290 | * TCNTB and TCMPB are loaded into TCNT and TCMP. | |
291 | * Update timers. | |
292 | */ | |
293 | ||
294 | /* this will start timer to run, this ok, because | |
295 | * during processing start bit timer will be stopped | |
296 | * if needed */ | |
297 | ptimer_set_count(s->timer[i].ptimer, s->timer[i].reg_tcntb); | |
298 | DPRINTF("set timer %d count to %x\n", i, | |
299 | s->timer[i].reg_tcntb); | |
300 | } | |
301 | ||
302 | if ((value & TCON_TIMER_START(i)) > | |
303 | (s->reg_tcon & TCON_TIMER_START(i))) { | |
304 | /* changed to start */ | |
305 | ptimer_run(s->timer[i].ptimer, 1); | |
306 | DPRINTF("run timer %d\n", i); | |
307 | } | |
308 | ||
309 | if ((value & TCON_TIMER_START(i)) < | |
310 | (s->reg_tcon & TCON_TIMER_START(i))) { | |
311 | /* changed to stop */ | |
312 | ptimer_stop(s->timer[i].ptimer); | |
313 | DPRINTF("stop timer %d\n", i); | |
314 | } | |
315 | } | |
316 | s->reg_tcon = value; | |
317 | break; | |
318 | ||
319 | case TCNTB0: case TCNTB1: | |
320 | case TCNTB2: case TCNTB3: case TCNTB4: | |
321 | index = (offset - TCNTB0) / 0xC; | |
322 | s->timer[index].reg_tcntb = value; | |
323 | break; | |
324 | ||
325 | case TCMPB0: case TCMPB1: | |
326 | case TCMPB2: case TCMPB3: | |
327 | index = (offset - TCMPB0) / 0xC; | |
328 | s->timer[index].reg_tcmpb = value; | |
329 | break; | |
330 | ||
331 | case TINT_CSTAT: | |
332 | new_val = (s->reg_tint_cstat & 0x3E0) + (0x1F & value); | |
333 | new_val &= ~(0x3E0 & value); | |
334 | ||
335 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | |
336 | if ((new_val & TINT_CSTAT_STATUS(i)) < | |
337 | (s->reg_tint_cstat & TINT_CSTAT_STATUS(i))) { | |
338 | qemu_irq_lower(s->timer[i].irq); | |
339 | } | |
340 | } | |
341 | ||
342 | s->reg_tint_cstat = new_val; | |
343 | break; | |
344 | ||
345 | default: | |
346 | fprintf(stderr, | |
347 | "[exynos4210.pwm: bad write offset " TARGET_FMT_plx "]\n", | |
348 | offset); | |
349 | break; | |
350 | ||
351 | } | |
352 | } | |
353 | ||
354 | /* | |
355 | * Set default values to timer fields and registers | |
356 | */ | |
357 | static void exynos4210_pwm_reset(DeviceState *d) | |
358 | { | |
25fce9ad | 359 | Exynos4210PWMState *s = EXYNOS4210_PWM(d); |
62db8bf3 EV |
360 | int i; |
361 | s->reg_tcfg[0] = 0x0101; | |
362 | s->reg_tcfg[1] = 0x0; | |
363 | s->reg_tcon = 0; | |
364 | s->reg_tint_cstat = 0; | |
365 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | |
366 | s->timer[i].reg_tcmpb = 0; | |
367 | s->timer[i].reg_tcntb = 0; | |
368 | ||
369 | exynos4210_pwm_update_freq(s, s->timer[i].id); | |
370 | ptimer_stop(s->timer[i].ptimer); | |
371 | } | |
372 | } | |
373 | ||
374 | static const MemoryRegionOps exynos4210_pwm_ops = { | |
375 | .read = exynos4210_pwm_read, | |
376 | .write = exynos4210_pwm_write, | |
377 | .endianness = DEVICE_NATIVE_ENDIAN, | |
378 | }; | |
379 | ||
380 | /* | |
381 | * PWM timer initialization | |
382 | */ | |
ff6ee495 | 383 | static void exynos4210_pwm_init(Object *obj) |
62db8bf3 | 384 | { |
ff6ee495 XZ |
385 | Exynos4210PWMState *s = EXYNOS4210_PWM(obj); |
386 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
62db8bf3 EV |
387 | int i; |
388 | QEMUBH *bh; | |
389 | ||
390 | for (i = 0; i < EXYNOS4210_PWM_TIMERS_NUM; i++) { | |
391 | bh = qemu_bh_new(exynos4210_pwm_tick, &s->timer[i]); | |
392 | sysbus_init_irq(dev, &s->timer[i].irq); | |
e7ea81c3 | 393 | s->timer[i].ptimer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); |
62db8bf3 EV |
394 | s->timer[i].id = i; |
395 | s->timer[i].parent = s; | |
396 | } | |
397 | ||
ff6ee495 | 398 | memory_region_init_io(&s->iomem, obj, &exynos4210_pwm_ops, s, |
853dca12 | 399 | "exynos4210-pwm", EXYNOS4210_PWM_REG_MEM_SIZE); |
62db8bf3 | 400 | sysbus_init_mmio(dev, &s->iomem); |
62db8bf3 EV |
401 | } |
402 | ||
403 | static void exynos4210_pwm_class_init(ObjectClass *klass, void *data) | |
404 | { | |
405 | DeviceClass *dc = DEVICE_CLASS(klass); | |
62db8bf3 | 406 | |
62db8bf3 EV |
407 | dc->reset = exynos4210_pwm_reset; |
408 | dc->vmsd = &vmstate_exynos4210_pwm_state; | |
409 | } | |
410 | ||
8c43a6f0 | 411 | static const TypeInfo exynos4210_pwm_info = { |
25fce9ad | 412 | .name = TYPE_EXYNOS4210_PWM, |
62db8bf3 EV |
413 | .parent = TYPE_SYS_BUS_DEVICE, |
414 | .instance_size = sizeof(Exynos4210PWMState), | |
ff6ee495 | 415 | .instance_init = exynos4210_pwm_init, |
62db8bf3 EV |
416 | .class_init = exynos4210_pwm_class_init, |
417 | }; | |
418 | ||
419 | static void exynos4210_pwm_register_types(void) | |
420 | { | |
421 | type_register_static(&exynos4210_pwm_info); | |
422 | } | |
423 | ||
424 | type_init(exynos4210_pwm_register_types) |