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7bdf43a7 OO |
1 | /* |
2 | * Samsung exynos4210 Real Time Clock | |
3 | * | |
4 | * Copyright (c) 2012 Samsung Electronics Co., Ltd. | |
5 | * Ogurtsov Oleg <o.ogurtsov@samsung.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, but WITHOUT | |
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License | |
15 | * for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | * | |
20 | */ | |
21 | ||
22 | /* Description: | |
23 | * Register RTCCON: | |
24 | * CLKSEL Bit[1] not used | |
25 | * CLKOUTEN Bit[9] not used | |
26 | */ | |
27 | ||
8ef94f0b | 28 | #include "qemu/osdep.h" |
83c9f4ca | 29 | #include "hw/sysbus.h" |
1de7afc9 | 30 | #include "qemu/timer.h" |
7bdf43a7 | 31 | #include "qemu-common.h" |
83c9f4ca | 32 | #include "hw/ptimer.h" |
7bdf43a7 | 33 | |
83c9f4ca | 34 | #include "hw/hw.h" |
9c17d615 | 35 | #include "sysemu/sysemu.h" |
7bdf43a7 | 36 | |
0d09e41a | 37 | #include "hw/arm/exynos4210.h" |
7bdf43a7 OO |
38 | |
39 | #define DEBUG_RTC 0 | |
40 | ||
41 | #if DEBUG_RTC | |
42 | #define DPRINTF(fmt, ...) \ | |
43 | do { fprintf(stdout, "RTC: [%24s:%5d] " fmt, __func__, __LINE__, \ | |
44 | ## __VA_ARGS__); } while (0) | |
45 | #else | |
46 | #define DPRINTF(fmt, ...) do {} while (0) | |
47 | #endif | |
48 | ||
49 | #define EXYNOS4210_RTC_REG_MEM_SIZE 0x0100 | |
50 | ||
51 | #define INTP 0x0030 | |
52 | #define RTCCON 0x0040 | |
53 | #define TICCNT 0x0044 | |
54 | #define RTCALM 0x0050 | |
55 | #define ALMSEC 0x0054 | |
56 | #define ALMMIN 0x0058 | |
57 | #define ALMHOUR 0x005C | |
58 | #define ALMDAY 0x0060 | |
59 | #define ALMMON 0x0064 | |
60 | #define ALMYEAR 0x0068 | |
61 | #define BCDSEC 0x0070 | |
62 | #define BCDMIN 0x0074 | |
63 | #define BCDHOUR 0x0078 | |
64 | #define BCDDAY 0x007C | |
65 | #define BCDDAYWEEK 0x0080 | |
66 | #define BCDMON 0x0084 | |
67 | #define BCDYEAR 0x0088 | |
68 | #define CURTICNT 0x0090 | |
69 | ||
70 | #define TICK_TIMER_ENABLE 0x0100 | |
4c293dc6 | 71 | #define TICNT_THRESHOLD 2 |
7bdf43a7 OO |
72 | |
73 | ||
74 | #define RTC_ENABLE 0x0001 | |
75 | ||
76 | #define INTP_TICK_ENABLE 0x0001 | |
77 | #define INTP_ALM_ENABLE 0x0002 | |
78 | ||
79 | #define ALARM_INT_ENABLE 0x0040 | |
80 | ||
81 | #define RTC_BASE_FREQ 32768 | |
82 | ||
3ddacf27 AF |
83 | #define TYPE_EXYNOS4210_RTC "exynos4210.rtc" |
84 | #define EXYNOS4210_RTC(obj) \ | |
85 | OBJECT_CHECK(Exynos4210RTCState, (obj), TYPE_EXYNOS4210_RTC) | |
86 | ||
7bdf43a7 | 87 | typedef struct Exynos4210RTCState { |
3ddacf27 AF |
88 | SysBusDevice parent_obj; |
89 | ||
7bdf43a7 OO |
90 | MemoryRegion iomem; |
91 | ||
92 | /* registers */ | |
93 | uint32_t reg_intp; | |
94 | uint32_t reg_rtccon; | |
95 | uint32_t reg_ticcnt; | |
96 | uint32_t reg_rtcalm; | |
97 | uint32_t reg_almsec; | |
98 | uint32_t reg_almmin; | |
99 | uint32_t reg_almhour; | |
100 | uint32_t reg_almday; | |
101 | uint32_t reg_almmon; | |
102 | uint32_t reg_almyear; | |
103 | uint32_t reg_curticcnt; | |
104 | ||
105 | ptimer_state *ptimer; /* tick timer */ | |
106 | ptimer_state *ptimer_1Hz; /* clock timer */ | |
107 | uint32_t freq; | |
108 | ||
109 | qemu_irq tick_irq; /* Time Tick Generator irq */ | |
110 | qemu_irq alm_irq; /* alarm irq */ | |
111 | ||
112 | struct tm current_tm; /* current time */ | |
113 | } Exynos4210RTCState; | |
114 | ||
115 | #define TICCKSEL(value) ((value & (0x0F << 4)) >> 4) | |
116 | ||
117 | /*** VMState ***/ | |
118 | static const VMStateDescription vmstate_exynos4210_rtc_state = { | |
119 | .name = "exynos4210.rtc", | |
120 | .version_id = 1, | |
121 | .minimum_version_id = 1, | |
7bdf43a7 OO |
122 | .fields = (VMStateField[]) { |
123 | VMSTATE_UINT32(reg_intp, Exynos4210RTCState), | |
124 | VMSTATE_UINT32(reg_rtccon, Exynos4210RTCState), | |
125 | VMSTATE_UINT32(reg_ticcnt, Exynos4210RTCState), | |
126 | VMSTATE_UINT32(reg_rtcalm, Exynos4210RTCState), | |
127 | VMSTATE_UINT32(reg_almsec, Exynos4210RTCState), | |
128 | VMSTATE_UINT32(reg_almmin, Exynos4210RTCState), | |
129 | VMSTATE_UINT32(reg_almhour, Exynos4210RTCState), | |
130 | VMSTATE_UINT32(reg_almday, Exynos4210RTCState), | |
131 | VMSTATE_UINT32(reg_almmon, Exynos4210RTCState), | |
132 | VMSTATE_UINT32(reg_almyear, Exynos4210RTCState), | |
133 | VMSTATE_UINT32(reg_curticcnt, Exynos4210RTCState), | |
134 | VMSTATE_PTIMER(ptimer, Exynos4210RTCState), | |
135 | VMSTATE_PTIMER(ptimer_1Hz, Exynos4210RTCState), | |
136 | VMSTATE_UINT32(freq, Exynos4210RTCState), | |
137 | VMSTATE_INT32(current_tm.tm_sec, Exynos4210RTCState), | |
138 | VMSTATE_INT32(current_tm.tm_min, Exynos4210RTCState), | |
139 | VMSTATE_INT32(current_tm.tm_hour, Exynos4210RTCState), | |
140 | VMSTATE_INT32(current_tm.tm_wday, Exynos4210RTCState), | |
141 | VMSTATE_INT32(current_tm.tm_mday, Exynos4210RTCState), | |
142 | VMSTATE_INT32(current_tm.tm_mon, Exynos4210RTCState), | |
143 | VMSTATE_INT32(current_tm.tm_year, Exynos4210RTCState), | |
144 | VMSTATE_END_OF_LIST() | |
145 | } | |
146 | }; | |
147 | ||
148 | #define BCD3DIGITS(x) \ | |
64de1ecf | 149 | ((uint32_t)to_bcd((uint8_t)(x % 100)) + \ |
7bdf43a7 OO |
150 | ((uint32_t)to_bcd((uint8_t)((x % 1000) / 100)) << 8)) |
151 | ||
152 | static void check_alarm_raise(Exynos4210RTCState *s) | |
153 | { | |
154 | unsigned int alarm_raise = 0; | |
155 | struct tm stm = s->current_tm; | |
156 | ||
157 | if ((s->reg_rtcalm & 0x01) && | |
158 | (to_bcd((uint8_t)stm.tm_sec) == (uint8_t)s->reg_almsec)) { | |
159 | alarm_raise = 1; | |
160 | } | |
161 | if ((s->reg_rtcalm & 0x02) && | |
162 | (to_bcd((uint8_t)stm.tm_min) == (uint8_t)s->reg_almmin)) { | |
163 | alarm_raise = 1; | |
164 | } | |
165 | if ((s->reg_rtcalm & 0x04) && | |
166 | (to_bcd((uint8_t)stm.tm_hour) == (uint8_t)s->reg_almhour)) { | |
167 | alarm_raise = 1; | |
168 | } | |
169 | if ((s->reg_rtcalm & 0x08) && | |
170 | (to_bcd((uint8_t)stm.tm_mday) == (uint8_t)s->reg_almday)) { | |
171 | alarm_raise = 1; | |
172 | } | |
173 | if ((s->reg_rtcalm & 0x10) && | |
174 | (to_bcd((uint8_t)stm.tm_mon) == (uint8_t)s->reg_almmon)) { | |
175 | alarm_raise = 1; | |
176 | } | |
177 | if ((s->reg_rtcalm & 0x20) && | |
178 | (BCD3DIGITS(stm.tm_year) == s->reg_almyear)) { | |
179 | alarm_raise = 1; | |
180 | } | |
181 | ||
182 | if (alarm_raise) { | |
183 | DPRINTF("ALARM IRQ\n"); | |
184 | /* set irq status */ | |
185 | s->reg_intp |= INTP_ALM_ENABLE; | |
186 | qemu_irq_raise(s->alm_irq); | |
187 | } | |
188 | } | |
189 | ||
190 | /* | |
191 | * RTC update frequency | |
192 | * Parameters: | |
193 | * reg_value - current RTCCON register or his new value | |
194 | */ | |
195 | static void exynos4210_rtc_update_freq(Exynos4210RTCState *s, | |
196 | uint32_t reg_value) | |
197 | { | |
198 | uint32_t freq; | |
199 | ||
200 | freq = s->freq; | |
201 | /* set frequncy for time generator */ | |
202 | s->freq = RTC_BASE_FREQ / (1 << TICCKSEL(reg_value)); | |
203 | ||
204 | if (freq != s->freq) { | |
205 | ptimer_set_freq(s->ptimer, s->freq); | |
206 | DPRINTF("freq=%dHz\n", s->freq); | |
207 | } | |
208 | } | |
209 | ||
210 | /* month is between 0 and 11. */ | |
211 | static int get_days_in_month(int month, int year) | |
212 | { | |
213 | static const int days_tab[12] = { | |
214 | 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 | |
215 | }; | |
216 | int d; | |
217 | if ((unsigned)month >= 12) { | |
218 | return 31; | |
219 | } | |
220 | d = days_tab[month]; | |
221 | if (month == 1) { | |
222 | if ((year % 4) == 0 && ((year % 100) != 0 || (year % 400) == 0)) { | |
223 | d++; | |
224 | } | |
225 | } | |
226 | return d; | |
227 | } | |
228 | ||
229 | /* update 'tm' to the next second */ | |
230 | static void rtc_next_second(struct tm *tm) | |
231 | { | |
232 | int days_in_month; | |
233 | ||
234 | tm->tm_sec++; | |
235 | if ((unsigned)tm->tm_sec >= 60) { | |
236 | tm->tm_sec = 0; | |
237 | tm->tm_min++; | |
238 | if ((unsigned)tm->tm_min >= 60) { | |
239 | tm->tm_min = 0; | |
240 | tm->tm_hour++; | |
241 | if ((unsigned)tm->tm_hour >= 24) { | |
242 | tm->tm_hour = 0; | |
243 | /* next day */ | |
244 | tm->tm_wday++; | |
245 | if ((unsigned)tm->tm_wday >= 7) { | |
246 | tm->tm_wday = 0; | |
247 | } | |
248 | days_in_month = get_days_in_month(tm->tm_mon, | |
249 | tm->tm_year + 1900); | |
250 | tm->tm_mday++; | |
251 | if (tm->tm_mday < 1) { | |
252 | tm->tm_mday = 1; | |
253 | } else if (tm->tm_mday > days_in_month) { | |
254 | tm->tm_mday = 1; | |
255 | tm->tm_mon++; | |
256 | if (tm->tm_mon >= 12) { | |
257 | tm->tm_mon = 0; | |
258 | tm->tm_year++; | |
259 | } | |
260 | } | |
261 | } | |
262 | } | |
263 | } | |
264 | } | |
265 | ||
266 | /* | |
267 | * tick handler | |
268 | */ | |
269 | static void exynos4210_rtc_tick(void *opaque) | |
270 | { | |
271 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; | |
272 | ||
273 | DPRINTF("TICK IRQ\n"); | |
274 | /* set irq status */ | |
275 | s->reg_intp |= INTP_TICK_ENABLE; | |
276 | /* raise IRQ */ | |
277 | qemu_irq_raise(s->tick_irq); | |
278 | ||
279 | /* restart timer */ | |
280 | ptimer_set_count(s->ptimer, s->reg_ticcnt); | |
281 | ptimer_run(s->ptimer, 1); | |
282 | } | |
283 | ||
284 | /* | |
285 | * 1Hz clock handler | |
286 | */ | |
287 | static void exynos4210_rtc_1Hz_tick(void *opaque) | |
288 | { | |
289 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; | |
290 | ||
291 | rtc_next_second(&s->current_tm); | |
292 | /* DPRINTF("1Hz tick\n"); */ | |
293 | ||
294 | /* raise IRQ */ | |
295 | if (s->reg_rtcalm & ALARM_INT_ENABLE) { | |
296 | check_alarm_raise(s); | |
297 | } | |
298 | ||
299 | ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ); | |
300 | ptimer_run(s->ptimer_1Hz, 1); | |
301 | } | |
302 | ||
303 | /* | |
304 | * RTC Read | |
305 | */ | |
a8170e5e | 306 | static uint64_t exynos4210_rtc_read(void *opaque, hwaddr offset, |
7bdf43a7 OO |
307 | unsigned size) |
308 | { | |
309 | uint32_t value = 0; | |
310 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; | |
311 | ||
312 | switch (offset) { | |
313 | case INTP: | |
314 | value = s->reg_intp; | |
315 | break; | |
316 | case RTCCON: | |
317 | value = s->reg_rtccon; | |
318 | break; | |
319 | case TICCNT: | |
320 | value = s->reg_ticcnt; | |
321 | break; | |
322 | case RTCALM: | |
323 | value = s->reg_rtcalm; | |
324 | break; | |
325 | case ALMSEC: | |
326 | value = s->reg_almsec; | |
327 | break; | |
328 | case ALMMIN: | |
329 | value = s->reg_almmin; | |
330 | break; | |
331 | case ALMHOUR: | |
332 | value = s->reg_almhour; | |
333 | break; | |
334 | case ALMDAY: | |
335 | value = s->reg_almday; | |
336 | break; | |
337 | case ALMMON: | |
338 | value = s->reg_almmon; | |
339 | break; | |
340 | case ALMYEAR: | |
341 | value = s->reg_almyear; | |
342 | break; | |
343 | ||
344 | case BCDSEC: | |
345 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_sec); | |
346 | break; | |
347 | case BCDMIN: | |
348 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_min); | |
349 | break; | |
350 | case BCDHOUR: | |
351 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_hour); | |
352 | break; | |
353 | case BCDDAYWEEK: | |
354 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_wday); | |
355 | break; | |
356 | case BCDDAY: | |
357 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mday); | |
358 | break; | |
359 | case BCDMON: | |
360 | value = (uint32_t)to_bcd((uint8_t)s->current_tm.tm_mon + 1); | |
361 | break; | |
362 | case BCDYEAR: | |
363 | value = BCD3DIGITS(s->current_tm.tm_year); | |
364 | break; | |
365 | ||
366 | case CURTICNT: | |
367 | s->reg_curticcnt = ptimer_get_count(s->ptimer); | |
368 | value = s->reg_curticcnt; | |
369 | break; | |
370 | ||
371 | default: | |
372 | fprintf(stderr, | |
373 | "[exynos4210.rtc: bad read offset " TARGET_FMT_plx "]\n", | |
374 | offset); | |
375 | break; | |
376 | } | |
377 | return value; | |
378 | } | |
379 | ||
380 | /* | |
381 | * RTC Write | |
382 | */ | |
a8170e5e | 383 | static void exynos4210_rtc_write(void *opaque, hwaddr offset, |
7bdf43a7 OO |
384 | uint64_t value, unsigned size) |
385 | { | |
386 | Exynos4210RTCState *s = (Exynos4210RTCState *)opaque; | |
387 | ||
388 | switch (offset) { | |
389 | case INTP: | |
390 | if (value & INTP_ALM_ENABLE) { | |
391 | qemu_irq_lower(s->alm_irq); | |
392 | s->reg_intp &= (~INTP_ALM_ENABLE); | |
393 | } | |
394 | if (value & INTP_TICK_ENABLE) { | |
395 | qemu_irq_lower(s->tick_irq); | |
396 | s->reg_intp &= (~INTP_TICK_ENABLE); | |
397 | } | |
398 | break; | |
399 | case RTCCON: | |
400 | if (value & RTC_ENABLE) { | |
401 | exynos4210_rtc_update_freq(s, value); | |
402 | } | |
403 | if ((value & RTC_ENABLE) > (s->reg_rtccon & RTC_ENABLE)) { | |
404 | /* clock timer */ | |
405 | ptimer_set_count(s->ptimer_1Hz, RTC_BASE_FREQ); | |
406 | ptimer_run(s->ptimer_1Hz, 1); | |
407 | DPRINTF("run clock timer\n"); | |
408 | } | |
409 | if ((value & RTC_ENABLE) < (s->reg_rtccon & RTC_ENABLE)) { | |
410 | /* tick timer */ | |
411 | ptimer_stop(s->ptimer); | |
412 | /* clock timer */ | |
413 | ptimer_stop(s->ptimer_1Hz); | |
414 | DPRINTF("stop all timers\n"); | |
415 | } | |
416 | if (value & RTC_ENABLE) { | |
417 | if ((value & TICK_TIMER_ENABLE) > | |
418 | (s->reg_rtccon & TICK_TIMER_ENABLE) && | |
419 | (s->reg_ticcnt)) { | |
420 | ptimer_set_count(s->ptimer, s->reg_ticcnt); | |
421 | ptimer_run(s->ptimer, 1); | |
422 | DPRINTF("run tick timer\n"); | |
423 | } | |
424 | if ((value & TICK_TIMER_ENABLE) < | |
425 | (s->reg_rtccon & TICK_TIMER_ENABLE)) { | |
426 | ptimer_stop(s->ptimer); | |
427 | } | |
428 | } | |
429 | s->reg_rtccon = value; | |
430 | break; | |
431 | case TICCNT: | |
4c293dc6 | 432 | if (value > TICNT_THRESHOLD) { |
7bdf43a7 OO |
433 | s->reg_ticcnt = value; |
434 | } else { | |
435 | fprintf(stderr, | |
436 | "[exynos4210.rtc: bad TICNT value %u ]\n", | |
437 | (uint32_t)value); | |
438 | } | |
439 | break; | |
440 | ||
441 | case RTCALM: | |
442 | s->reg_rtcalm = value; | |
443 | break; | |
444 | case ALMSEC: | |
445 | s->reg_almsec = (value & 0x7f); | |
446 | break; | |
447 | case ALMMIN: | |
448 | s->reg_almmin = (value & 0x7f); | |
449 | break; | |
450 | case ALMHOUR: | |
451 | s->reg_almhour = (value & 0x3f); | |
452 | break; | |
453 | case ALMDAY: | |
454 | s->reg_almday = (value & 0x3f); | |
455 | break; | |
456 | case ALMMON: | |
457 | s->reg_almmon = (value & 0x1f); | |
458 | break; | |
459 | case ALMYEAR: | |
460 | s->reg_almyear = (value & 0x0fff); | |
461 | break; | |
462 | ||
463 | case BCDSEC: | |
464 | if (s->reg_rtccon & RTC_ENABLE) { | |
465 | s->current_tm.tm_sec = (int)from_bcd((uint8_t)value); | |
466 | } | |
467 | break; | |
468 | case BCDMIN: | |
469 | if (s->reg_rtccon & RTC_ENABLE) { | |
470 | s->current_tm.tm_min = (int)from_bcd((uint8_t)value); | |
471 | } | |
472 | break; | |
473 | case BCDHOUR: | |
474 | if (s->reg_rtccon & RTC_ENABLE) { | |
475 | s->current_tm.tm_hour = (int)from_bcd((uint8_t)value); | |
476 | } | |
477 | break; | |
478 | case BCDDAYWEEK: | |
479 | if (s->reg_rtccon & RTC_ENABLE) { | |
480 | s->current_tm.tm_wday = (int)from_bcd((uint8_t)value); | |
481 | } | |
482 | break; | |
483 | case BCDDAY: | |
484 | if (s->reg_rtccon & RTC_ENABLE) { | |
485 | s->current_tm.tm_mday = (int)from_bcd((uint8_t)value); | |
486 | } | |
487 | break; | |
488 | case BCDMON: | |
489 | if (s->reg_rtccon & RTC_ENABLE) { | |
490 | s->current_tm.tm_mon = (int)from_bcd((uint8_t)value) - 1; | |
491 | } | |
492 | break; | |
493 | case BCDYEAR: | |
494 | if (s->reg_rtccon & RTC_ENABLE) { | |
495 | /* 3 digits */ | |
496 | s->current_tm.tm_year = (int)from_bcd((uint8_t)value) + | |
497 | (int)from_bcd((uint8_t)((value >> 8) & 0x0f)) * 100; | |
498 | } | |
499 | break; | |
500 | ||
501 | default: | |
502 | fprintf(stderr, | |
503 | "[exynos4210.rtc: bad write offset " TARGET_FMT_plx "]\n", | |
504 | offset); | |
505 | break; | |
506 | ||
507 | } | |
508 | } | |
509 | ||
510 | /* | |
511 | * Set default values to timer fields and registers | |
512 | */ | |
513 | static void exynos4210_rtc_reset(DeviceState *d) | |
514 | { | |
3ddacf27 | 515 | Exynos4210RTCState *s = EXYNOS4210_RTC(d); |
7bdf43a7 | 516 | |
4688870d | 517 | qemu_get_timedate(&s->current_tm, 0); |
7bdf43a7 OO |
518 | |
519 | DPRINTF("Get time from host: %d-%d-%d %2d:%02d:%02d\n", | |
520 | s->current_tm.tm_year, s->current_tm.tm_mon, s->current_tm.tm_mday, | |
521 | s->current_tm.tm_hour, s->current_tm.tm_min, s->current_tm.tm_sec); | |
522 | ||
523 | s->reg_intp = 0; | |
524 | s->reg_rtccon = 0; | |
525 | s->reg_ticcnt = 0; | |
526 | s->reg_rtcalm = 0; | |
527 | s->reg_almsec = 0; | |
528 | s->reg_almmin = 0; | |
529 | s->reg_almhour = 0; | |
530 | s->reg_almday = 0; | |
531 | s->reg_almmon = 0; | |
532 | s->reg_almyear = 0; | |
533 | ||
534 | s->reg_curticcnt = 0; | |
535 | ||
536 | exynos4210_rtc_update_freq(s, s->reg_rtccon); | |
537 | ptimer_stop(s->ptimer); | |
538 | ptimer_stop(s->ptimer_1Hz); | |
539 | } | |
540 | ||
541 | static const MemoryRegionOps exynos4210_rtc_ops = { | |
542 | .read = exynos4210_rtc_read, | |
543 | .write = exynos4210_rtc_write, | |
544 | .endianness = DEVICE_NATIVE_ENDIAN, | |
545 | }; | |
546 | ||
547 | /* | |
548 | * RTC timer initialization | |
549 | */ | |
550 | static int exynos4210_rtc_init(SysBusDevice *dev) | |
551 | { | |
3ddacf27 | 552 | Exynos4210RTCState *s = EXYNOS4210_RTC(dev); |
7bdf43a7 OO |
553 | QEMUBH *bh; |
554 | ||
555 | bh = qemu_bh_new(exynos4210_rtc_tick, s); | |
556 | s->ptimer = ptimer_init(bh); | |
557 | ptimer_set_freq(s->ptimer, RTC_BASE_FREQ); | |
558 | exynos4210_rtc_update_freq(s, 0); | |
559 | ||
560 | bh = qemu_bh_new(exynos4210_rtc_1Hz_tick, s); | |
561 | s->ptimer_1Hz = ptimer_init(bh); | |
562 | ptimer_set_freq(s->ptimer_1Hz, RTC_BASE_FREQ); | |
563 | ||
564 | sysbus_init_irq(dev, &s->alm_irq); | |
565 | sysbus_init_irq(dev, &s->tick_irq); | |
566 | ||
853dca12 PB |
567 | memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_rtc_ops, s, |
568 | "exynos4210-rtc", EXYNOS4210_RTC_REG_MEM_SIZE); | |
7bdf43a7 OO |
569 | sysbus_init_mmio(dev, &s->iomem); |
570 | ||
571 | return 0; | |
572 | } | |
573 | ||
574 | static void exynos4210_rtc_class_init(ObjectClass *klass, void *data) | |
575 | { | |
576 | DeviceClass *dc = DEVICE_CLASS(klass); | |
577 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); | |
578 | ||
579 | k->init = exynos4210_rtc_init; | |
580 | dc->reset = exynos4210_rtc_reset; | |
581 | dc->vmsd = &vmstate_exynos4210_rtc_state; | |
582 | } | |
583 | ||
584 | static const TypeInfo exynos4210_rtc_info = { | |
3ddacf27 | 585 | .name = TYPE_EXYNOS4210_RTC, |
7bdf43a7 OO |
586 | .parent = TYPE_SYS_BUS_DEVICE, |
587 | .instance_size = sizeof(Exynos4210RTCState), | |
588 | .class_init = exynos4210_rtc_class_init, | |
589 | }; | |
590 | ||
591 | static void exynos4210_rtc_register_types(void) | |
592 | { | |
593 | type_register_static(&exynos4210_rtc_info); | |
594 | } | |
595 | ||
596 | type_init(exynos4210_rtc_register_types) |