[mirror_qemu.git] / hw / timer / grlib_gptimer.c

/*
 * QEMU GRLIB GPTimer Emulator
 *
 * Copyright (c) 2010-2019 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sparc/grlib.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/irq.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "qemu/module.h"

#include "trace.h"
#include "qom/object.h"

#define UNIT_REG_SIZE    16     /* Size of memory mapped regs for the unit */
#define GPTIMER_REG_SIZE 16     /* Size of memory mapped regs for a GPTimer */

#define GPTIMER_MAX_TIMERS 8

/* GPTimer Config register fields */
#define GPTIMER_ENABLE      (1 << 0)
#define GPTIMER_RESTART     (1 << 1)
#define GPTIMER_LOAD        (1 << 2)
#define GPTIMER_INT_ENABLE  (1 << 3)
#define GPTIMER_INT_PENDING (1 << 4)
#define GPTIMER_CHAIN       (1 << 5) /* Not supported */
#define GPTIMER_DEBUG_HALT  (1 << 6) /* Not supported */

/* Memory mapped register offsets */
#define SCALER_OFFSET         0x00
#define SCALER_RELOAD_OFFSET  0x04
#define CONFIG_OFFSET         0x08
#define COUNTER_OFFSET        0x00
#define COUNTER_RELOAD_OFFSET 0x04
#define TIMER_BASE            0x10

OBJECT_DECLARE_SIMPLE_TYPE(GPTimerUnit, GRLIB_GPTIMER)

typedef struct GPTimer     GPTimer;

struct GPTimer {
    struct ptimer_state *ptimer;

    qemu_irq     irq;
    int          id;
    GPTimerUnit *unit;

    /* registers */
    uint32_t counter;
    uint32_t reload;
    uint32_t config;
};

struct GPTimerUnit {
    SysBusDevice  parent_obj;

    MemoryRegion iomem;

    uint32_t nr_timers;         /* Number of timers available */
    uint32_t freq_hz;           /* System frequency */
    uint32_t irq_line;          /* Base irq line */

    GPTimer *timers;

    /* registers */
    uint32_t scaler;
    uint32_t reload;
    uint32_t config;
};

static void grlib_gptimer_tx_begin(GPTimer *timer)
{
    ptimer_transaction_begin(timer->ptimer);
}

static void grlib_gptimer_tx_commit(GPTimer *timer)
{
    ptimer_transaction_commit(timer->ptimer);
}

/* Must be called within grlib_gptimer_tx_begin/commit block */
static void grlib_gptimer_enable(GPTimer *timer)
{
    assert(timer != NULL);


    ptimer_stop(timer->ptimer);

    if (!(timer->config & GPTIMER_ENABLE)) {
        /* Timer disabled */
        trace_grlib_gptimer_disabled(timer->id, timer->config);
        return;
    }

    /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
       underflow. Set count + 1 to simulate the GPTimer behavior. */

    trace_grlib_gptimer_enable(timer->id, timer->counter);

    ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
    ptimer_run(timer->ptimer, 1);
}

/* Must be called within grlib_gptimer_tx_begin/commit block */
static void grlib_gptimer_restart(GPTimer *timer)
{
    assert(timer != NULL);

    trace_grlib_gptimer_restart(timer->id, timer->reload);

    timer->counter = timer->reload;
    grlib_gptimer_enable(timer);
}

static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
{
    int i = 0;
    uint32_t value = 0;

    assert(unit != NULL);

    if (scaler > 0) {
        value = unit->freq_hz / (scaler + 1);
    } else {
        value = unit->freq_hz;
    }

    trace_grlib_gptimer_set_scaler(scaler, value);

    for (i = 0; i < unit->nr_timers; i++) {
        ptimer_transaction_begin(unit->timers[i].ptimer);
        ptimer_set_freq(unit->timers[i].ptimer, value);
        ptimer_transaction_commit(unit->timers[i].ptimer);
    }
}

static void grlib_gptimer_hit(void *opaque)
{
    GPTimer *timer = opaque;
    assert(timer != NULL);

    trace_grlib_gptimer_hit(timer->id);

    /* Timer expired */

    if (timer->config & GPTIMER_INT_ENABLE) {
        /* Set the pending bit (only unset by write in the config register) */
        timer->config |= GPTIMER_INT_PENDING;
        qemu_irq_pulse(timer->irq);
    }

    if (timer->config & GPTIMER_RESTART) {
        grlib_gptimer_restart(timer);
    }
}

static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
                                   unsigned size)
{
    GPTimerUnit        *unit  = opaque;
    hwaddr  timer_addr;
    int                 id;
    uint32_t            value = 0;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->scaler);
        return unit->scaler;

    case SCALER_RELOAD_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->reload);
        return unit->reload;

    case CONFIG_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->config);
        return unit->config;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            value = ptimer_get_count(unit->timers[id].ptimer);
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case COUNTER_RELOAD_OFFSET:
            value = unit->timers[id].reload;
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
            return unit->timers[id].config;

        default:
            break;
        }

    }

    trace_grlib_gptimer_readl(-1, addr, 0);
    return 0;
}

static void grlib_gptimer_write(void *opaque, hwaddr addr,
                                uint64_t value, unsigned size)
{
    GPTimerUnit        *unit = opaque;
    hwaddr  timer_addr;
    int                 id;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->scaler = value;
        trace_grlib_gptimer_writel(-1, addr, unit->scaler);
        return;

    case SCALER_RELOAD_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->reload = value;
        trace_grlib_gptimer_writel(-1, addr, unit->reload);
        grlib_gptimer_set_scaler(unit, value);
        return;

    case CONFIG_OFFSET:
        /* Read Only (disable timer freeze not supported) */
        trace_grlib_gptimer_writel(-1, addr, 0);
        return;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            grlib_gptimer_tx_begin(&unit->timers[id]);
            unit->timers[id].counter = value;
            grlib_gptimer_enable(&unit->timers[id]);
            grlib_gptimer_tx_commit(&unit->timers[id]);
            return;

        case COUNTER_RELOAD_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            unit->timers[id].reload = value;
            return;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);

            if (value & GPTIMER_INT_PENDING) {
                /* clear pending bit */
                value &= ~GPTIMER_INT_PENDING;
            } else {
                /* keep pending bit */
                value |= unit->timers[id].config & GPTIMER_INT_PENDING;
            }

            unit->timers[id].config = value;

            /* gptimer_restart calls gptimer_enable, so if "enable" and "load"
               bits are present, we just have to call restart. */

            grlib_gptimer_tx_begin(&unit->timers[id]);
            if (value & GPTIMER_LOAD) {
                grlib_gptimer_restart(&unit->timers[id]);
            } else if (value & GPTIMER_ENABLE) {
                grlib_gptimer_enable(&unit->timers[id]);
            }

            /* These fields must always be read as 0 */
            value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);

            unit->timers[id].config = value;
            grlib_gptimer_tx_commit(&unit->timers[id]);
            return;

        default:
            break;
        }

    }

    trace_grlib_gptimer_writel(-1, addr, value);
}

static const MemoryRegionOps grlib_gptimer_ops = {
    .read = grlib_gptimer_read,
    .write = grlib_gptimer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void grlib_gptimer_reset(DeviceState *d)
{
    GPTimerUnit *unit = GRLIB_GPTIMER(d);
    int          i    = 0;

    assert(unit != NULL);

    unit->scaler = 0;
    unit->reload = 0;

    unit->config  = unit->nr_timers;
    unit->config |= unit->irq_line << 3;
    unit->config |= 1 << 8;     /* separate interrupt */
    unit->config |= 1 << 9;     /* Disable timer freeze */


    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->counter = 0;
        timer->reload = 0;
        timer->config = 0;
        ptimer_transaction_begin(timer->ptimer);
        ptimer_stop(timer->ptimer);
        ptimer_set_count(timer->ptimer, 0);
        ptimer_set_freq(timer->ptimer, unit->freq_hz);
        ptimer_transaction_commit(timer->ptimer);
    }
}

static void grlib_gptimer_realize(DeviceState *dev, Error **errp)
{
    GPTimerUnit  *unit = GRLIB_GPTIMER(dev);
    unsigned int  i;
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);

    assert(unit->nr_timers > 0);
    assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);

    unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);

    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->unit   = unit;
        timer->ptimer = ptimer_init(grlib_gptimer_hit, timer,
                                    PTIMER_POLICY_DEFAULT);
        timer->id     = i;

        /* One IRQ line for each timer */
        sysbus_init_irq(sbd, &timer->irq);

        ptimer_transaction_begin(timer->ptimer);
        ptimer_set_freq(timer->ptimer, unit->freq_hz);
        ptimer_transaction_commit(timer->ptimer);
    }

    memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
                          unit, "gptimer",
                          UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);

    sysbus_init_mmio(sbd, &unit->iomem);
}

static Property grlib_gptimer_properties[] = {
    DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz,   40000000),
    DEFINE_PROP_UINT32("irq-line",  GPTimerUnit, irq_line,  8),
    DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
    DEFINE_PROP_END_OF_LIST(),
};

static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = grlib_gptimer_realize;
    dc->reset = grlib_gptimer_reset;
    device_class_set_props(dc, grlib_gptimer_properties);
}

static const TypeInfo grlib_gptimer_info = {
    .name          = TYPE_GRLIB_GPTIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(GPTimerUnit),
    .class_init    = grlib_gptimer_class_init,
};

static void grlib_gptimer_register_types(void)
{
    type_register_static(&grlib_gptimer_info);
}

type_init(grlib_gptimer_register_types)
Commit	Line	Data
0f3a4a01 FC	1	/*
	2	* QEMU GRLIB GPTimer Emulator
	3	*
948caec8	4	* Copyright (c) 2010-2019 AdaCore
0f3a4a01 FC	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
db5ebe5f	25	#include "qemu/osdep.h"
948caec8	26	#include "hw/sparc/grlib.h"
83c9f4ca	27	#include "hw/sysbus.h"
1de7afc9	28	#include "qemu/timer.h"
64552b6b	29	#include "hw/irq.h"
83c9f4ca	30	#include "hw/ptimer.h"
a27bd6c7	31	#include "hw/qdev-properties.h"
0b8fa32f	32	#include "qemu/module.h"
0f3a4a01 FC	33
0f3a4a01 FC	34	#include "trace.h"
db1015e9	35	#include "qom/object.h"
0f3a4a01 FC	36
	37	#define UNIT_REG_SIZE 16 /* Size of memory mapped regs for the unit */
	38	#define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */
	39
	40	#define GPTIMER_MAX_TIMERS 8
	41
	42	/* GPTimer Config register fields */
	43	#define GPTIMER_ENABLE (1 << 0)
	44	#define GPTIMER_RESTART (1 << 1)
	45	#define GPTIMER_LOAD (1 << 2)
	46	#define GPTIMER_INT_ENABLE (1 << 3)
	47	#define GPTIMER_INT_PENDING (1 << 4)
	48	#define GPTIMER_CHAIN (1 << 5) /* Not supported */
	49	#define GPTIMER_DEBUG_HALT (1 << 6) /* Not supported */
	50
	51	/* Memory mapped register offsets */
	52	#define SCALER_OFFSET 0x00
	53	#define SCALER_RELOAD_OFFSET 0x04
	54	#define CONFIG_OFFSET 0x08
	55	#define COUNTER_OFFSET 0x00
	56	#define COUNTER_RELOAD_OFFSET 0x04
	57	#define TIMER_BASE 0x10
	58
8063396b	59	OBJECT_DECLARE_SIMPLE_TYPE(GPTimerUnit, GRLIB_GPTIMER)
541ab55f	60
0f3a4a01	61	typedef struct GPTimer GPTimer;
0f3a4a01 FC	62
0f3a4a01 FC	63	struct GPTimer {
0f3a4a01 FC	64	struct ptimer_state *ptimer;
	65
	66	qemu_irq irq;
	67	int id;
	68	GPTimerUnit *unit;
	69
	70	/* registers */
	71	uint32_t counter;
	72	uint32_t reload;
	73	uint32_t config;
	74	};
	75
	76	struct GPTimerUnit {
541ab55f AF	77	SysBusDevice parent_obj;
541ab55f AF	78
cde844fa	79	MemoryRegion iomem;
0f3a4a01 FC	80
	81	uint32_t nr_timers; /* Number of timers available */
	82	uint32_t freq_hz; /* System frequency */
	83	uint32_t irq_line; /* Base irq line */
	84
	85	GPTimer *timers;
	86
	87	/* registers */
	88	uint32_t scaler;
	89	uint32_t reload;
	90	uint32_t config;
	91	};
	92
663e475f PM	93	static void grlib_gptimer_tx_begin(GPTimer *timer)
	94	{
	95	ptimer_transaction_begin(timer->ptimer);
	96	}
	97
	98	static void grlib_gptimer_tx_commit(GPTimer *timer)
	99	{
	100	ptimer_transaction_commit(timer->ptimer);
	101	}
	102
	103	/* Must be called within grlib_gptimer_tx_begin/commit block */
0f3a4a01 FC	104	static void grlib_gptimer_enable(GPTimer *timer)
	105	{
	106	assert(timer != NULL);
	107
	108
	109	ptimer_stop(timer->ptimer);
	110
	111	if (!(timer->config & GPTIMER_ENABLE)) {
	112	/* Timer disabled */
	113	trace_grlib_gptimer_disabled(timer->id, timer->config);
	114	return;
	115	}
	116
	117	/* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
	118	underflow. Set count + 1 to simulate the GPTimer behavior. */
	119
9d5614d5	120	trace_grlib_gptimer_enable(timer->id, timer->counter);
0f3a4a01	121
9d5614d5	122	ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
0f3a4a01 FC	123	ptimer_run(timer->ptimer, 1);
	124	}
	125
663e475f	126	/* Must be called within grlib_gptimer_tx_begin/commit block */
0f3a4a01 FC	127	static void grlib_gptimer_restart(GPTimer *timer)
	128	{
	129	assert(timer != NULL);
	130
	131	trace_grlib_gptimer_restart(timer->id, timer->reload);
	132
	133	timer->counter = timer->reload;
	134	grlib_gptimer_enable(timer);
	135	}
	136
	137	static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
	138	{
	139	int i = 0;
	140	uint32_t value = 0;
	141
	142	assert(unit != NULL);
	143
	144	if (scaler > 0) {
	145	value = unit->freq_hz / (scaler + 1);
	146	} else {
	147	value = unit->freq_hz;
	148	}
	149
	150	trace_grlib_gptimer_set_scaler(scaler, value);
	151
	152	for (i = 0; i < unit->nr_timers; i++) {
663e475f	153	ptimer_transaction_begin(unit->timers[i].ptimer);
0f3a4a01	154	ptimer_set_freq(unit->timers[i].ptimer, value);
663e475f	155	ptimer_transaction_commit(unit->timers[i].ptimer);
0f3a4a01 FC	156	}
	157	}
	158
	159	static void grlib_gptimer_hit(void *opaque)
	160	{
	161	GPTimer *timer = opaque;
	162	assert(timer != NULL);
	163
	164	trace_grlib_gptimer_hit(timer->id);
	165
	166	/* Timer expired */
	167
	168	if (timer->config & GPTIMER_INT_ENABLE) {
	169	/* Set the pending bit (only unset by write in the config register) */
	170	timer->config \|= GPTIMER_INT_PENDING;
	171	qemu_irq_pulse(timer->irq);
	172	}
	173
	174	if (timer->config & GPTIMER_RESTART) {
	175	grlib_gptimer_restart(timer);
	176	}
	177	}
	178
a8170e5e	179	static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
cde844fa	180	unsigned size)
0f3a4a01 FC	181	{
0f3a4a01 FC	182	GPTimerUnit *unit = opaque;
a8170e5e	183	hwaddr timer_addr;
0f3a4a01 FC	184	int id;
	185	uint32_t value = 0;
	186
	187	addr &= 0xff;
	188
	189	/* Unit registers */
	190	switch (addr) {
	191	case SCALER_OFFSET:
b4548fcc	192	trace_grlib_gptimer_readl(-1, addr, unit->scaler);
0f3a4a01 FC	193	return unit->scaler;
	194
	195	case SCALER_RELOAD_OFFSET:
b4548fcc	196	trace_grlib_gptimer_readl(-1, addr, unit->reload);
0f3a4a01 FC	197	return unit->reload;
	198
	199	case CONFIG_OFFSET:
b4548fcc	200	trace_grlib_gptimer_readl(-1, addr, unit->config);
0f3a4a01 FC	201	return unit->config;
	202
	203	default:
	204	break;
	205	}
	206
	207	timer_addr = (addr % TIMER_BASE);
	208	id = (addr - TIMER_BASE) / TIMER_BASE;
	209
	210	if (id >= 0 && id < unit->nr_timers) {
	211
	212	/* GPTimer registers */
	213	switch (timer_addr) {
	214	case COUNTER_OFFSET:
	215	value = ptimer_get_count(unit->timers[id].ptimer);
b4548fcc	216	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	217	return value;
	218
	219	case COUNTER_RELOAD_OFFSET:
	220	value = unit->timers[id].reload;
b4548fcc	221	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	222	return value;
	223
	224	case CONFIG_OFFSET:
b4548fcc	225	trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
0f3a4a01 FC	226	return unit->timers[id].config;
	227
	228	default:
	229	break;
	230	}
	231
	232	}
	233
b4548fcc	234	trace_grlib_gptimer_readl(-1, addr, 0);
0f3a4a01 FC	235	return 0;
	236	}
	237
a8170e5e	238	static void grlib_gptimer_write(void *opaque, hwaddr addr,
cde844fa	239	uint64_t value, unsigned size)
0f3a4a01 FC	240	{
0f3a4a01 FC	241	GPTimerUnit *unit = opaque;
a8170e5e	242	hwaddr timer_addr;
0f3a4a01 FC	243	int id;
	244
	245	addr &= 0xff;
	246
	247	/* Unit registers */
	248	switch (addr) {
	249	case SCALER_OFFSET:
	250	value &= 0xFFFF; /* clean up the value */
	251	unit->scaler = value;
b4548fcc	252	trace_grlib_gptimer_writel(-1, addr, unit->scaler);
0f3a4a01 FC	253	return;
	254
	255	case SCALER_RELOAD_OFFSET:
	256	value &= 0xFFFF; /* clean up the value */
	257	unit->reload = value;
b4548fcc	258	trace_grlib_gptimer_writel(-1, addr, unit->reload);
0f3a4a01 FC	259	grlib_gptimer_set_scaler(unit, value);
	260	return;
	261
	262	case CONFIG_OFFSET:
	263	/* Read Only (disable timer freeze not supported) */
b4548fcc	264	trace_grlib_gptimer_writel(-1, addr, 0);
0f3a4a01 FC	265	return;
	266
	267	default:
	268	break;
	269	}
	270
	271	timer_addr = (addr % TIMER_BASE);
	272	id = (addr - TIMER_BASE) / TIMER_BASE;
	273
	274	if (id >= 0 && id < unit->nr_timers) {
	275
	276	/* GPTimer registers */
	277	switch (timer_addr) {
	278	case COUNTER_OFFSET:
b4548fcc	279	trace_grlib_gptimer_writel(id, addr, value);
663e475f	280	grlib_gptimer_tx_begin(&unit->timers[id]);
0f3a4a01 FC	281	unit->timers[id].counter = value;
0f3a4a01 FC	282	grlib_gptimer_enable(&unit->timers[id]);
663e475f	283	grlib_gptimer_tx_commit(&unit->timers[id]);
0f3a4a01 FC	284	return;
	285
	286	case COUNTER_RELOAD_OFFSET:
b4548fcc	287	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	288	unit->timers[id].reload = value;
	289	return;
	290
	291	case CONFIG_OFFSET:
b4548fcc	292	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	293
	294	if (value & GPTIMER_INT_PENDING) {
	295	/* clear pending bit */
	296	value &= ~GPTIMER_INT_PENDING;
	297	} else {
	298	/* keep pending bit */
	299	value \|= unit->timers[id].config & GPTIMER_INT_PENDING;
	300	}
	301
	302	unit->timers[id].config = value;
	303
	304	/* gptimer_restart calls gptimer_enable, so if "enable" and "load"
	305	bits are present, we just have to call restart. */
	306
663e475f	307	grlib_gptimer_tx_begin(&unit->timers[id]);
0f3a4a01 FC	308	if (value & GPTIMER_LOAD) {
	309	grlib_gptimer_restart(&unit->timers[id]);
	310	} else if (value & GPTIMER_ENABLE) {
	311	grlib_gptimer_enable(&unit->timers[id]);
	312	}
	313
	314	/* These fields must always be read as 0 */
	315	value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);
	316
	317	unit->timers[id].config = value;
663e475f	318	grlib_gptimer_tx_commit(&unit->timers[id]);
0f3a4a01 FC	319	return;
	320
	321	default:
	322	break;
	323	}
	324
	325	}
	326
b4548fcc	327	trace_grlib_gptimer_writel(-1, addr, value);
0f3a4a01 FC	328	}
0f3a4a01 FC	329
cde844fa AK	330	static const MemoryRegionOps grlib_gptimer_ops = {
	331	.read = grlib_gptimer_read,
	332	.write = grlib_gptimer_write,
	333	.endianness = DEVICE_NATIVE_ENDIAN,
	334	.valid = {
	335	.min_access_size = 4,
	336	.max_access_size = 4,
	337	},
0f3a4a01 FC	338	};
	339
	340	static void grlib_gptimer_reset(DeviceState *d)
	341	{
541ab55f	342	GPTimerUnit *unit = GRLIB_GPTIMER(d);
0f3a4a01 FC	343	int i = 0;
	344
	345	assert(unit != NULL);
	346
	347	unit->scaler = 0;
	348	unit->reload = 0;
0f3a4a01 FC	349
	350	unit->config = unit->nr_timers;
	351	unit->config \|= unit->irq_line << 3;
	352	unit->config \|= 1 << 8; /* separate interrupt */
	353	unit->config \|= 1 << 9; /* Disable timer freeze */
	354
	355
	356	for (i = 0; i < unit->nr_timers; i++) {
	357	GPTimer *timer = &unit->timers[i];
	358
	359	timer->counter = 0;
	360	timer->reload = 0;
	361	timer->config = 0;
663e475f	362	ptimer_transaction_begin(timer->ptimer);
0f3a4a01 FC	363	ptimer_stop(timer->ptimer);
	364	ptimer_set_count(timer->ptimer, 0);
	365	ptimer_set_freq(timer->ptimer, unit->freq_hz);
663e475f	366	ptimer_transaction_commit(timer->ptimer);
0f3a4a01 FC	367	}
	368	}
	369
23251fb8	370	static void grlib_gptimer_realize(DeviceState dev, Error *errp)
0f3a4a01	371	{
541ab55f	372	GPTimerUnit *unit = GRLIB_GPTIMER(dev);
0f3a4a01	373	unsigned int i;
23251fb8	374	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
0f3a4a01 FC	375
	376	assert(unit->nr_timers > 0);
	377	assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
	378
7267c094	379	unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);
0f3a4a01 FC	380
	381	for (i = 0; i < unit->nr_timers; i++) {
	382	GPTimer *timer = &unit->timers[i];
	383
	384	timer->unit = unit;
663e475f PM	385	timer->ptimer = ptimer_init(grlib_gptimer_hit, timer,
663e475f PM	386	PTIMER_POLICY_DEFAULT);
0f3a4a01 FC	387	timer->id = i;
	388
	389	/* One IRQ line for each timer */
23251fb8	390	sysbus_init_irq(sbd, &timer->irq);
0f3a4a01	391
663e475f	392	ptimer_transaction_begin(timer->ptimer);
0f3a4a01	393	ptimer_set_freq(timer->ptimer, unit->freq_hz);
663e475f	394	ptimer_transaction_commit(timer->ptimer);
0f3a4a01 FC	395	}
0f3a4a01 FC	396
853dca12 PB	397	memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
853dca12 PB	398	unit, "gptimer",
cde844fa	399	UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
0f3a4a01	400
23251fb8	401	sysbus_init_mmio(sbd, &unit->iomem);
0f3a4a01 FC	402	}
0f3a4a01 FC	403
999e12bb AL	404	static Property grlib_gptimer_properties[] = {
	405	DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000),
	406	DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8),
	407	DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
	408	DEFINE_PROP_END_OF_LIST(),
	409	};
	410
	411	static void grlib_gptimer_class_init(ObjectClass klass, void data)
	412	{
39bffca2	413	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	414
23251fb8	415	dc->realize = grlib_gptimer_realize;
39bffca2	416	dc->reset = grlib_gptimer_reset;
4f67d30b	417	device_class_set_props(dc, grlib_gptimer_properties);
999e12bb AL	418	}
999e12bb AL	419
8c43a6f0	420	static const TypeInfo grlib_gptimer_info = {
541ab55f	421	.name = TYPE_GRLIB_GPTIMER,
39bffca2 AL	422	.parent = TYPE_SYS_BUS_DEVICE,
	423	.instance_size = sizeof(GPTimerUnit),
	424	.class_init = grlib_gptimer_class_init,
0f3a4a01 FC	425	};
0f3a4a01 FC	426
83f7d43a	427	static void grlib_gptimer_register_types(void)
0f3a4a01	428	{
39bffca2	429	type_register_static(&grlib_gptimer_info);
0f3a4a01 FC	430	}
0f3a4a01 FC	431
83f7d43a	432	type_init(grlib_gptimer_register_types)