[mirror_qemu.git] / hw / timer / grlib_gptimer.c

/*
 * QEMU GRLIB GPTimer Emulator
 *
 * Copyright (c) 2010-2011 AdaCore
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "qemu/osdep.h"
#include "hw/sysbus.h"
#include "qemu/timer.h"
#include "hw/ptimer.h"
#include "qemu/timer.h"
#include "qemu/main-loop.h"

#include "trace.h"

#define UNIT_REG_SIZE    16     /* Size of memory mapped regs for the unit */
#define GPTIMER_REG_SIZE 16     /* Size of memory mapped regs for a GPTimer */

#define GPTIMER_MAX_TIMERS 8

/* GPTimer Config register fields */
#define GPTIMER_ENABLE      (1 << 0)
#define GPTIMER_RESTART     (1 << 1)
#define GPTIMER_LOAD        (1 << 2)
#define GPTIMER_INT_ENABLE  (1 << 3)
#define GPTIMER_INT_PENDING (1 << 4)
#define GPTIMER_CHAIN       (1 << 5) /* Not supported */
#define GPTIMER_DEBUG_HALT  (1 << 6) /* Not supported */

/* Memory mapped register offsets */
#define SCALER_OFFSET         0x00
#define SCALER_RELOAD_OFFSET  0x04
#define CONFIG_OFFSET         0x08
#define COUNTER_OFFSET        0x00
#define COUNTER_RELOAD_OFFSET 0x04
#define TIMER_BASE            0x10

#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
#define GRLIB_GPTIMER(obj) \
    OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)

typedef struct GPTimer     GPTimer;
typedef struct GPTimerUnit GPTimerUnit;

struct GPTimer {
    QEMUBH *bh;
    struct ptimer_state *ptimer;

    qemu_irq     irq;
    int          id;
    GPTimerUnit *unit;

    /* registers */
    uint32_t counter;
    uint32_t reload;
    uint32_t config;
};

struct GPTimerUnit {
    SysBusDevice  parent_obj;

    MemoryRegion iomem;

    uint32_t nr_timers;         /* Number of timers available */
    uint32_t freq_hz;           /* System frequency */
    uint32_t irq_line;          /* Base irq line */

    GPTimer *timers;

    /* registers */
    uint32_t scaler;
    uint32_t reload;
    uint32_t config;
};

static void grlib_gptimer_enable(GPTimer *timer)
{
    assert(timer != NULL);


    ptimer_stop(timer->ptimer);

    if (!(timer->config & GPTIMER_ENABLE)) {
        /* Timer disabled */
        trace_grlib_gptimer_disabled(timer->id, timer->config);
        return;
    }

    /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
       underflow. Set count + 1 to simulate the GPTimer behavior. */

    trace_grlib_gptimer_enable(timer->id, timer->counter);

    ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
    ptimer_run(timer->ptimer, 1);
}

static void grlib_gptimer_restart(GPTimer *timer)
{
    assert(timer != NULL);

    trace_grlib_gptimer_restart(timer->id, timer->reload);

    timer->counter = timer->reload;
    grlib_gptimer_enable(timer);
}

static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
{
    int i = 0;
    uint32_t value = 0;

    assert(unit != NULL);

    if (scaler > 0) {
        value = unit->freq_hz / (scaler + 1);
    } else {
        value = unit->freq_hz;
    }

    trace_grlib_gptimer_set_scaler(scaler, value);

    for (i = 0; i < unit->nr_timers; i++) {
        ptimer_set_freq(unit->timers[i].ptimer, value);
    }
}

static void grlib_gptimer_hit(void *opaque)
{
    GPTimer *timer = opaque;
    assert(timer != NULL);

    trace_grlib_gptimer_hit(timer->id);

    /* Timer expired */

    if (timer->config & GPTIMER_INT_ENABLE) {
        /* Set the pending bit (only unset by write in the config register) */
        timer->config |= GPTIMER_INT_PENDING;
        qemu_irq_pulse(timer->irq);
    }

    if (timer->config & GPTIMER_RESTART) {
        grlib_gptimer_restart(timer);
    }
}

static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
                                   unsigned size)
{
    GPTimerUnit        *unit  = opaque;
    hwaddr  timer_addr;
    int                 id;
    uint32_t            value = 0;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->scaler);
        return unit->scaler;

    case SCALER_RELOAD_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->reload);
        return unit->reload;

    case CONFIG_OFFSET:
        trace_grlib_gptimer_readl(-1, addr, unit->config);
        return unit->config;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            value = ptimer_get_count(unit->timers[id].ptimer);
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case COUNTER_RELOAD_OFFSET:
            value = unit->timers[id].reload;
            trace_grlib_gptimer_readl(id, addr, value);
            return value;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
            return unit->timers[id].config;

        default:
            break;
        }

    }

    trace_grlib_gptimer_readl(-1, addr, 0);
    return 0;
}

static void grlib_gptimer_write(void *opaque, hwaddr addr,
                                uint64_t value, unsigned size)
{
    GPTimerUnit        *unit = opaque;
    hwaddr  timer_addr;
    int                 id;

    addr &= 0xff;

    /* Unit registers */
    switch (addr) {
    case SCALER_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->scaler = value;
        trace_grlib_gptimer_writel(-1, addr, unit->scaler);
        return;

    case SCALER_RELOAD_OFFSET:
        value &= 0xFFFF; /* clean up the value */
        unit->reload = value;
        trace_grlib_gptimer_writel(-1, addr, unit->reload);
        grlib_gptimer_set_scaler(unit, value);
        return;

    case CONFIG_OFFSET:
        /* Read Only (disable timer freeze not supported) */
        trace_grlib_gptimer_writel(-1, addr, 0);
        return;

    default:
        break;
    }

    timer_addr = (addr % TIMER_BASE);
    id         = (addr - TIMER_BASE) / TIMER_BASE;

    if (id >= 0 && id < unit->nr_timers) {

        /* GPTimer registers */
        switch (timer_addr) {
        case COUNTER_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            unit->timers[id].counter = value;
            grlib_gptimer_enable(&unit->timers[id]);
            return;

        case COUNTER_RELOAD_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);
            unit->timers[id].reload = value;
            return;

        case CONFIG_OFFSET:
            trace_grlib_gptimer_writel(id, addr, value);

            if (value & GPTIMER_INT_PENDING) {
                /* clear pending bit */
                value &= ~GPTIMER_INT_PENDING;
            } else {
                /* keep pending bit */
                value |= unit->timers[id].config & GPTIMER_INT_PENDING;
            }

            unit->timers[id].config = value;

            /* gptimer_restart calls gptimer_enable, so if "enable" and "load"
               bits are present, we just have to call restart. */

            if (value & GPTIMER_LOAD) {
                grlib_gptimer_restart(&unit->timers[id]);
            } else if (value & GPTIMER_ENABLE) {
                grlib_gptimer_enable(&unit->timers[id]);
            }

            /* These fields must always be read as 0 */
            value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);

            unit->timers[id].config = value;
            return;

        default:
            break;
        }

    }

    trace_grlib_gptimer_writel(-1, addr, value);
}

static const MemoryRegionOps grlib_gptimer_ops = {
    .read = grlib_gptimer_read,
    .write = grlib_gptimer_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
};

static void grlib_gptimer_reset(DeviceState *d)
{
    GPTimerUnit *unit = GRLIB_GPTIMER(d);
    int          i    = 0;

    assert(unit != NULL);

    unit->scaler = 0;
    unit->reload = 0;

    unit->config  = unit->nr_timers;
    unit->config |= unit->irq_line << 3;
    unit->config |= 1 << 8;     /* separate interrupt */
    unit->config |= 1 << 9;     /* Disable timer freeze */


    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->counter = 0;
        timer->reload = 0;
        timer->config = 0;
        ptimer_stop(timer->ptimer);
        ptimer_set_count(timer->ptimer, 0);
        ptimer_set_freq(timer->ptimer, unit->freq_hz);
    }
}

static int grlib_gptimer_init(SysBusDevice *dev)
{
    GPTimerUnit  *unit = GRLIB_GPTIMER(dev);
    unsigned int  i;

    assert(unit->nr_timers > 0);
    assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);

    unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);

    for (i = 0; i < unit->nr_timers; i++) {
        GPTimer *timer = &unit->timers[i];

        timer->unit   = unit;
        timer->bh     = qemu_bh_new(grlib_gptimer_hit, timer);
        timer->ptimer = ptimer_init(timer->bh);
        timer->id     = i;

        /* One IRQ line for each timer */
        sysbus_init_irq(dev, &timer->irq);

        ptimer_set_freq(timer->ptimer, unit->freq_hz);
    }

    memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
                          unit, "gptimer",
                          UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);

    sysbus_init_mmio(dev, &unit->iomem);
    return 0;
}

static Property grlib_gptimer_properties[] = {
    DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz,   40000000),
    DEFINE_PROP_UINT32("irq-line",  GPTimerUnit, irq_line,  8),
    DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
    DEFINE_PROP_END_OF_LIST(),
};

static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = grlib_gptimer_init;
    dc->reset = grlib_gptimer_reset;
    dc->props = grlib_gptimer_properties;
}

static const TypeInfo grlib_gptimer_info = {
    .name          = TYPE_GRLIB_GPTIMER,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(GPTimerUnit),
    .class_init    = grlib_gptimer_class_init,
};

static void grlib_gptimer_register_types(void)
{
    type_register_static(&grlib_gptimer_info);
}

type_init(grlib_gptimer_register_types)
Commit	Line	Data
0f3a4a01 FC	1	/*
	2	* QEMU GRLIB GPTimer Emulator
	3	*
	4	* Copyright (c) 2010-2011 AdaCore
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
db5ebe5f	25	#include "qemu/osdep.h"
83c9f4ca	26	#include "hw/sysbus.h"
1de7afc9	27	#include "qemu/timer.h"
83c9f4ca	28	#include "hw/ptimer.h"
6a1751b7 AB	29	#include "qemu/timer.h"
6a1751b7 AB	30	#include "qemu/main-loop.h"
0f3a4a01 FC	31
	32	#include "trace.h"
	33
	34	#define UNIT_REG_SIZE 16 /* Size of memory mapped regs for the unit */
	35	#define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */
	36
	37	#define GPTIMER_MAX_TIMERS 8
	38
	39	/* GPTimer Config register fields */
	40	#define GPTIMER_ENABLE (1 << 0)
	41	#define GPTIMER_RESTART (1 << 1)
	42	#define GPTIMER_LOAD (1 << 2)
	43	#define GPTIMER_INT_ENABLE (1 << 3)
	44	#define GPTIMER_INT_PENDING (1 << 4)
	45	#define GPTIMER_CHAIN (1 << 5) /* Not supported */
	46	#define GPTIMER_DEBUG_HALT (1 << 6) /* Not supported */
	47
	48	/* Memory mapped register offsets */
	49	#define SCALER_OFFSET 0x00
	50	#define SCALER_RELOAD_OFFSET 0x04
	51	#define CONFIG_OFFSET 0x08
	52	#define COUNTER_OFFSET 0x00
	53	#define COUNTER_RELOAD_OFFSET 0x04
	54	#define TIMER_BASE 0x10
	55
541ab55f AF	56	#define TYPE_GRLIB_GPTIMER "grlib,gptimer"
	57	#define GRLIB_GPTIMER(obj) \
	58	OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER)
	59
0f3a4a01 FC	60	typedef struct GPTimer GPTimer;
	61	typedef struct GPTimerUnit GPTimerUnit;
	62
	63	struct GPTimer {
	64	QEMUBH *bh;
	65	struct ptimer_state *ptimer;
	66
	67	qemu_irq irq;
	68	int id;
	69	GPTimerUnit *unit;
	70
	71	/* registers */
	72	uint32_t counter;
	73	uint32_t reload;
	74	uint32_t config;
	75	};
	76
	77	struct GPTimerUnit {
541ab55f AF	78	SysBusDevice parent_obj;
541ab55f AF	79
cde844fa	80	MemoryRegion iomem;
0f3a4a01 FC	81
	82	uint32_t nr_timers; /* Number of timers available */
	83	uint32_t freq_hz; /* System frequency */
	84	uint32_t irq_line; /* Base irq line */
	85
	86	GPTimer *timers;
	87
	88	/* registers */
	89	uint32_t scaler;
	90	uint32_t reload;
	91	uint32_t config;
	92	};
	93
	94	static void grlib_gptimer_enable(GPTimer *timer)
	95	{
	96	assert(timer != NULL);
	97
	98
	99	ptimer_stop(timer->ptimer);
	100
	101	if (!(timer->config & GPTIMER_ENABLE)) {
	102	/* Timer disabled */
	103	trace_grlib_gptimer_disabled(timer->id, timer->config);
	104	return;
	105	}
	106
	107	/* ptimer is triggered when the counter reach 0 but GPTimer is triggered at
	108	underflow. Set count + 1 to simulate the GPTimer behavior. */
	109
9d5614d5	110	trace_grlib_gptimer_enable(timer->id, timer->counter);
0f3a4a01	111
9d5614d5	112	ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1);
0f3a4a01 FC	113	ptimer_run(timer->ptimer, 1);
	114	}
	115
	116	static void grlib_gptimer_restart(GPTimer *timer)
	117	{
	118	assert(timer != NULL);
	119
	120	trace_grlib_gptimer_restart(timer->id, timer->reload);
	121
	122	timer->counter = timer->reload;
	123	grlib_gptimer_enable(timer);
	124	}
	125
	126	static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler)
	127	{
	128	int i = 0;
	129	uint32_t value = 0;
	130
	131	assert(unit != NULL);
	132
	133	if (scaler > 0) {
	134	value = unit->freq_hz / (scaler + 1);
	135	} else {
	136	value = unit->freq_hz;
	137	}
	138
	139	trace_grlib_gptimer_set_scaler(scaler, value);
	140
	141	for (i = 0; i < unit->nr_timers; i++) {
	142	ptimer_set_freq(unit->timers[i].ptimer, value);
	143	}
	144	}
	145
	146	static void grlib_gptimer_hit(void *opaque)
	147	{
	148	GPTimer *timer = opaque;
	149	assert(timer != NULL);
	150
	151	trace_grlib_gptimer_hit(timer->id);
	152
	153	/* Timer expired */
	154
	155	if (timer->config & GPTIMER_INT_ENABLE) {
	156	/* Set the pending bit (only unset by write in the config register) */
	157	timer->config \|= GPTIMER_INT_PENDING;
	158	qemu_irq_pulse(timer->irq);
	159	}
	160
	161	if (timer->config & GPTIMER_RESTART) {
	162	grlib_gptimer_restart(timer);
	163	}
	164	}
	165
a8170e5e	166	static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr,
cde844fa	167	unsigned size)
0f3a4a01 FC	168	{
0f3a4a01 FC	169	GPTimerUnit *unit = opaque;
a8170e5e	170	hwaddr timer_addr;
0f3a4a01 FC	171	int id;
	172	uint32_t value = 0;
	173
	174	addr &= 0xff;
	175
	176	/* Unit registers */
	177	switch (addr) {
	178	case SCALER_OFFSET:
b4548fcc	179	trace_grlib_gptimer_readl(-1, addr, unit->scaler);
0f3a4a01 FC	180	return unit->scaler;
	181
	182	case SCALER_RELOAD_OFFSET:
b4548fcc	183	trace_grlib_gptimer_readl(-1, addr, unit->reload);
0f3a4a01 FC	184	return unit->reload;
	185
	186	case CONFIG_OFFSET:
b4548fcc	187	trace_grlib_gptimer_readl(-1, addr, unit->config);
0f3a4a01 FC	188	return unit->config;
	189
	190	default:
	191	break;
	192	}
	193
	194	timer_addr = (addr % TIMER_BASE);
	195	id = (addr - TIMER_BASE) / TIMER_BASE;
	196
	197	if (id >= 0 && id < unit->nr_timers) {
	198
	199	/* GPTimer registers */
	200	switch (timer_addr) {
	201	case COUNTER_OFFSET:
	202	value = ptimer_get_count(unit->timers[id].ptimer);
b4548fcc	203	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	204	return value;
	205
	206	case COUNTER_RELOAD_OFFSET:
	207	value = unit->timers[id].reload;
b4548fcc	208	trace_grlib_gptimer_readl(id, addr, value);
0f3a4a01 FC	209	return value;
	210
	211	case CONFIG_OFFSET:
b4548fcc	212	trace_grlib_gptimer_readl(id, addr, unit->timers[id].config);
0f3a4a01 FC	213	return unit->timers[id].config;
	214
	215	default:
	216	break;
	217	}
	218
	219	}
	220
b4548fcc	221	trace_grlib_gptimer_readl(-1, addr, 0);
0f3a4a01 FC	222	return 0;
	223	}
	224
a8170e5e	225	static void grlib_gptimer_write(void *opaque, hwaddr addr,
cde844fa	226	uint64_t value, unsigned size)
0f3a4a01 FC	227	{
0f3a4a01 FC	228	GPTimerUnit *unit = opaque;
a8170e5e	229	hwaddr timer_addr;
0f3a4a01 FC	230	int id;
	231
	232	addr &= 0xff;
	233
	234	/* Unit registers */
	235	switch (addr) {
	236	case SCALER_OFFSET:
	237	value &= 0xFFFF; /* clean up the value */
	238	unit->scaler = value;
b4548fcc	239	trace_grlib_gptimer_writel(-1, addr, unit->scaler);
0f3a4a01 FC	240	return;
	241
	242	case SCALER_RELOAD_OFFSET:
	243	value &= 0xFFFF; /* clean up the value */
	244	unit->reload = value;
b4548fcc	245	trace_grlib_gptimer_writel(-1, addr, unit->reload);
0f3a4a01 FC	246	grlib_gptimer_set_scaler(unit, value);
	247	return;
	248
	249	case CONFIG_OFFSET:
	250	/* Read Only (disable timer freeze not supported) */
b4548fcc	251	trace_grlib_gptimer_writel(-1, addr, 0);
0f3a4a01 FC	252	return;
	253
	254	default:
	255	break;
	256	}
	257
	258	timer_addr = (addr % TIMER_BASE);
	259	id = (addr - TIMER_BASE) / TIMER_BASE;
	260
	261	if (id >= 0 && id < unit->nr_timers) {
	262
	263	/* GPTimer registers */
	264	switch (timer_addr) {
	265	case COUNTER_OFFSET:
b4548fcc	266	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	267	unit->timers[id].counter = value;
	268	grlib_gptimer_enable(&unit->timers[id]);
	269	return;
	270
	271	case COUNTER_RELOAD_OFFSET:
b4548fcc	272	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	273	unit->timers[id].reload = value;
	274	return;
	275
	276	case CONFIG_OFFSET:
b4548fcc	277	trace_grlib_gptimer_writel(id, addr, value);
0f3a4a01 FC	278
	279	if (value & GPTIMER_INT_PENDING) {
	280	/* clear pending bit */
	281	value &= ~GPTIMER_INT_PENDING;
	282	} else {
	283	/* keep pending bit */
	284	value \|= unit->timers[id].config & GPTIMER_INT_PENDING;
	285	}
	286
	287	unit->timers[id].config = value;
	288
	289	/* gptimer_restart calls gptimer_enable, so if "enable" and "load"
	290	bits are present, we just have to call restart. */
	291
	292	if (value & GPTIMER_LOAD) {
	293	grlib_gptimer_restart(&unit->timers[id]);
	294	} else if (value & GPTIMER_ENABLE) {
	295	grlib_gptimer_enable(&unit->timers[id]);
	296	}
	297
	298	/* These fields must always be read as 0 */
	299	value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT);
	300
	301	unit->timers[id].config = value;
	302	return;
	303
	304	default:
	305	break;
	306	}
	307
	308	}
	309
b4548fcc	310	trace_grlib_gptimer_writel(-1, addr, value);
0f3a4a01 FC	311	}
0f3a4a01 FC	312
cde844fa AK	313	static const MemoryRegionOps grlib_gptimer_ops = {
	314	.read = grlib_gptimer_read,
	315	.write = grlib_gptimer_write,
	316	.endianness = DEVICE_NATIVE_ENDIAN,
	317	.valid = {
	318	.min_access_size = 4,
	319	.max_access_size = 4,
	320	},
0f3a4a01 FC	321	};
	322
	323	static void grlib_gptimer_reset(DeviceState *d)
	324	{
541ab55f	325	GPTimerUnit *unit = GRLIB_GPTIMER(d);
0f3a4a01 FC	326	int i = 0;
	327
	328	assert(unit != NULL);
	329
	330	unit->scaler = 0;
	331	unit->reload = 0;
0f3a4a01 FC	332
	333	unit->config = unit->nr_timers;
	334	unit->config \|= unit->irq_line << 3;
	335	unit->config \|= 1 << 8; /* separate interrupt */
	336	unit->config \|= 1 << 9; /* Disable timer freeze */
	337
	338
	339	for (i = 0; i < unit->nr_timers; i++) {
	340	GPTimer *timer = &unit->timers[i];
	341
	342	timer->counter = 0;
	343	timer->reload = 0;
	344	timer->config = 0;
	345	ptimer_stop(timer->ptimer);
	346	ptimer_set_count(timer->ptimer, 0);
	347	ptimer_set_freq(timer->ptimer, unit->freq_hz);
	348	}
	349	}
	350
	351	static int grlib_gptimer_init(SysBusDevice *dev)
	352	{
541ab55f	353	GPTimerUnit *unit = GRLIB_GPTIMER(dev);
0f3a4a01	354	unsigned int i;
0f3a4a01 FC	355
	356	assert(unit->nr_timers > 0);
	357	assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
	358
7267c094	359	unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers);
0f3a4a01 FC	360
	361	for (i = 0; i < unit->nr_timers; i++) {
	362	GPTimer *timer = &unit->timers[i];
	363
	364	timer->unit = unit;
	365	timer->bh = qemu_bh_new(grlib_gptimer_hit, timer);
	366	timer->ptimer = ptimer_init(timer->bh);
	367	timer->id = i;
	368
	369	/* One IRQ line for each timer */
	370	sysbus_init_irq(dev, &timer->irq);
	371
	372	ptimer_set_freq(timer->ptimer, unit->freq_hz);
	373	}
	374
853dca12 PB	375	memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops,
853dca12 PB	376	unit, "gptimer",
cde844fa	377	UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
0f3a4a01	378
750ecd44	379	sysbus_init_mmio(dev, &unit->iomem);
0f3a4a01 FC	380	return 0;
	381	}
	382
999e12bb AL	383	static Property grlib_gptimer_properties[] = {
	384	DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000),
	385	DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8),
	386	DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2),
	387	DEFINE_PROP_END_OF_LIST(),
	388	};
	389
	390	static void grlib_gptimer_class_init(ObjectClass klass, void data)
	391	{
39bffca2	392	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	393	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	394
	395	k->init = grlib_gptimer_init;
39bffca2 AL	396	dc->reset = grlib_gptimer_reset;
39bffca2 AL	397	dc->props = grlib_gptimer_properties;
999e12bb AL	398	}
999e12bb AL	399
8c43a6f0	400	static const TypeInfo grlib_gptimer_info = {
541ab55f	401	.name = TYPE_GRLIB_GPTIMER,
39bffca2 AL	402	.parent = TYPE_SYS_BUS_DEVICE,
	403	.instance_size = sizeof(GPTimerUnit),
	404	.class_init = grlib_gptimer_class_init,
0f3a4a01 FC	405	};
0f3a4a01 FC	406
83f7d43a	407	static void grlib_gptimer_register_types(void)
0f3a4a01	408	{
39bffca2	409	type_register_static(&grlib_gptimer_info);
0f3a4a01 FC	410	}
0f3a4a01 FC	411
83f7d43a	412	type_init(grlib_gptimer_register_types)