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Commit | Line | Data |
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16b29ae1 | 1 | /* |
97c61fb7 | 2 | * High Precision Event Timer emulation |
16b29ae1 AL |
3 | * |
4 | * Copyright (c) 2007 Alexander Graf | |
5 | * Copyright (c) 2008 IBM Corporation | |
6 | * | |
7 | * Authors: Beth Kon <bkon@us.ibm.com> | |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
8167ee88 | 20 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
16b29ae1 AL |
21 | * |
22 | * ***************************************************************** | |
23 | * | |
24 | * This driver attempts to emulate an HPET device in software. | |
25 | */ | |
26 | ||
b6a0aa05 | 27 | #include "qemu/osdep.h" |
83c9f4ca | 28 | #include "hw/hw.h" |
0d09e41a | 29 | #include "hw/i386/pc.h" |
28ecbaee | 30 | #include "ui/console.h" |
da34e65c | 31 | #include "qapi/error.h" |
d49b6836 | 32 | #include "qemu/error-report.h" |
1de7afc9 | 33 | #include "qemu/timer.h" |
0d09e41a | 34 | #include "hw/timer/hpet.h" |
83c9f4ca | 35 | #include "hw/sysbus.h" |
0d09e41a PB |
36 | #include "hw/timer/mc146818rtc.h" |
37 | #include "hw/timer/i8254.h" | |
16b29ae1 | 38 | |
16b29ae1 AL |
39 | //#define HPET_DEBUG |
40 | #ifdef HPET_DEBUG | |
d0f2c4c6 | 41 | #define DPRINTF printf |
16b29ae1 | 42 | #else |
d0f2c4c6 | 43 | #define DPRINTF(...) |
16b29ae1 AL |
44 | #endif |
45 | ||
8caa0065 JK |
46 | #define HPET_MSI_SUPPORT 0 |
47 | ||
02f9a6f5 HT |
48 | #define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET) |
49 | ||
27bb0b2d JK |
50 | struct HPETState; |
51 | typedef struct HPETTimer { /* timers */ | |
52 | uint8_t tn; /*timer number*/ | |
53 | QEMUTimer *qemu_timer; | |
54 | struct HPETState *state; | |
55 | /* Memory-mapped, software visible timer registers */ | |
56 | uint64_t config; /* configuration/cap */ | |
57 | uint64_t cmp; /* comparator */ | |
8caa0065 | 58 | uint64_t fsb; /* FSB route */ |
27bb0b2d JK |
59 | /* Hidden register state */ |
60 | uint64_t period; /* Last value written to comparator */ | |
61 | uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit | |
62 | * mode. Next pop will be actual timer expiration. | |
63 | */ | |
64 | } HPETTimer; | |
65 | ||
66 | typedef struct HPETState { | |
02f9a6f5 HT |
67 | /*< private >*/ |
68 | SysBusDevice parent_obj; | |
69 | /*< public >*/ | |
70 | ||
e977aa37 | 71 | MemoryRegion iomem; |
27bb0b2d | 72 | uint64_t hpet_offset; |
822557eb | 73 | qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; |
8caa0065 | 74 | uint32_t flags; |
7d932dfd | 75 | uint8_t rtc_irq_level; |
ce967e2f | 76 | qemu_irq pit_enabled; |
be4b44c5 | 77 | uint8_t num_timers; |
7a10ef51 | 78 | uint32_t intcap; |
be4b44c5 | 79 | HPETTimer timer[HPET_MAX_TIMERS]; |
27bb0b2d JK |
80 | |
81 | /* Memory-mapped, software visible registers */ | |
82 | uint64_t capability; /* capabilities */ | |
83 | uint64_t config; /* configuration */ | |
84 | uint64_t isr; /* interrupt status reg */ | |
85 | uint64_t hpet_counter; /* main counter */ | |
40ac17cd | 86 | uint8_t hpet_id; /* instance id */ |
27bb0b2d JK |
87 | } HPETState; |
88 | ||
7d932dfd | 89 | static uint32_t hpet_in_legacy_mode(HPETState *s) |
16b29ae1 | 90 | { |
7d932dfd | 91 | return s->config & HPET_CFG_LEGACY; |
16b29ae1 AL |
92 | } |
93 | ||
c50c2d68 | 94 | static uint32_t timer_int_route(struct HPETTimer *timer) |
16b29ae1 | 95 | { |
27bb0b2d | 96 | return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; |
16b29ae1 AL |
97 | } |
98 | ||
8caa0065 JK |
99 | static uint32_t timer_fsb_route(HPETTimer *t) |
100 | { | |
101 | return t->config & HPET_TN_FSB_ENABLE; | |
102 | } | |
103 | ||
b7eaa6c7 | 104 | static uint32_t hpet_enabled(HPETState *s) |
16b29ae1 | 105 | { |
b7eaa6c7 | 106 | return s->config & HPET_CFG_ENABLE; |
16b29ae1 AL |
107 | } |
108 | ||
109 | static uint32_t timer_is_periodic(HPETTimer *t) | |
110 | { | |
111 | return t->config & HPET_TN_PERIODIC; | |
112 | } | |
113 | ||
114 | static uint32_t timer_enabled(HPETTimer *t) | |
115 | { | |
116 | return t->config & HPET_TN_ENABLE; | |
117 | } | |
118 | ||
119 | static uint32_t hpet_time_after(uint64_t a, uint64_t b) | |
120 | { | |
d17008bc | 121 | return ((int32_t)(b - a) < 0); |
16b29ae1 AL |
122 | } |
123 | ||
124 | static uint32_t hpet_time_after64(uint64_t a, uint64_t b) | |
125 | { | |
d17008bc | 126 | return ((int64_t)(b - a) < 0); |
16b29ae1 AL |
127 | } |
128 | ||
c50c2d68 | 129 | static uint64_t ticks_to_ns(uint64_t value) |
16b29ae1 | 130 | { |
0a4f9240 | 131 | return value * HPET_CLK_PERIOD; |
16b29ae1 AL |
132 | } |
133 | ||
c50c2d68 | 134 | static uint64_t ns_to_ticks(uint64_t value) |
16b29ae1 | 135 | { |
0a4f9240 | 136 | return value / HPET_CLK_PERIOD; |
16b29ae1 AL |
137 | } |
138 | ||
139 | static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask) | |
140 | { | |
141 | new &= mask; | |
142 | new |= old & ~mask; | |
143 | return new; | |
144 | } | |
145 | ||
146 | static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
147 | { | |
c50c2d68 | 148 | return (!(old & mask) && (new & mask)); |
16b29ae1 AL |
149 | } |
150 | ||
151 | static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) | |
152 | { | |
c50c2d68 | 153 | return ((old & mask) && !(new & mask)); |
16b29ae1 AL |
154 | } |
155 | ||
b7eaa6c7 | 156 | static uint64_t hpet_get_ticks(HPETState *s) |
16b29ae1 | 157 | { |
bc72ad67 | 158 | return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset); |
16b29ae1 AL |
159 | } |
160 | ||
c50c2d68 AJ |
161 | /* |
162 | * calculate diff between comparator value and current ticks | |
16b29ae1 AL |
163 | */ |
164 | static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) | |
165 | { | |
c50c2d68 | 166 | |
16b29ae1 AL |
167 | if (t->config & HPET_TN_32BIT) { |
168 | uint32_t diff, cmp; | |
27bb0b2d | 169 | |
16b29ae1 AL |
170 | cmp = (uint32_t)t->cmp; |
171 | diff = cmp - (uint32_t)current; | |
4f61927a | 172 | diff = (int32_t)diff > 0 ? diff : (uint32_t)1; |
16b29ae1 AL |
173 | return (uint64_t)diff; |
174 | } else { | |
175 | uint64_t diff, cmp; | |
27bb0b2d | 176 | |
16b29ae1 AL |
177 | cmp = t->cmp; |
178 | diff = cmp - current; | |
4f61927a | 179 | diff = (int64_t)diff > 0 ? diff : (uint64_t)1; |
16b29ae1 AL |
180 | return diff; |
181 | } | |
182 | } | |
183 | ||
22a9fe38 | 184 | static void update_irq(struct HPETTimer *timer, int set) |
16b29ae1 | 185 | { |
22a9fe38 JK |
186 | uint64_t mask; |
187 | HPETState *s; | |
16b29ae1 AL |
188 | int route; |
189 | ||
7d932dfd | 190 | if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { |
16b29ae1 AL |
191 | /* if LegacyReplacementRoute bit is set, HPET specification requires |
192 | * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, | |
c50c2d68 | 193 | * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. |
16b29ae1 | 194 | */ |
7d932dfd | 195 | route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; |
16b29ae1 | 196 | } else { |
27bb0b2d | 197 | route = timer_int_route(timer); |
16b29ae1 | 198 | } |
22a9fe38 JK |
199 | s = timer->state; |
200 | mask = 1 << timer->tn; | |
201 | if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) { | |
202 | s->isr &= ~mask; | |
8caa0065 | 203 | if (!timer_fsb_route(timer)) { |
0d63b2dd LPF |
204 | /* fold the ICH PIRQ# pin's internal inversion logic into hpet */ |
205 | if (route >= ISA_NUM_IRQS) { | |
206 | qemu_irq_raise(s->irqs[route]); | |
207 | } else { | |
208 | qemu_irq_lower(s->irqs[route]); | |
209 | } | |
8caa0065 JK |
210 | } |
211 | } else if (timer_fsb_route(timer)) { | |
42874d3a PM |
212 | address_space_stl_le(&address_space_memory, timer->fsb >> 32, |
213 | timer->fsb & 0xffffffff, MEMTXATTRS_UNSPECIFIED, | |
214 | NULL); | |
22a9fe38 JK |
215 | } else if (timer->config & HPET_TN_TYPE_LEVEL) { |
216 | s->isr |= mask; | |
0d63b2dd LPF |
217 | /* fold the ICH PIRQ# pin's internal inversion logic into hpet */ |
218 | if (route >= ISA_NUM_IRQS) { | |
219 | qemu_irq_lower(s->irqs[route]); | |
220 | } else { | |
221 | qemu_irq_raise(s->irqs[route]); | |
222 | } | |
22a9fe38 JK |
223 | } else { |
224 | s->isr &= ~mask; | |
225 | qemu_irq_pulse(s->irqs[route]); | |
16b29ae1 AL |
226 | } |
227 | } | |
228 | ||
d4bfa4d7 | 229 | static void hpet_pre_save(void *opaque) |
16b29ae1 | 230 | { |
d4bfa4d7 | 231 | HPETState *s = opaque; |
27bb0b2d | 232 | |
16b29ae1 | 233 | /* save current counter value */ |
b7eaa6c7 | 234 | s->hpet_counter = hpet_get_ticks(s); |
16b29ae1 AL |
235 | } |
236 | ||
be4b44c5 JK |
237 | static int hpet_pre_load(void *opaque) |
238 | { | |
239 | HPETState *s = opaque; | |
240 | ||
241 | /* version 1 only supports 3, later versions will load the actual value */ | |
242 | s->num_timers = HPET_MIN_TIMERS; | |
243 | return 0; | |
244 | } | |
245 | ||
3f1c49e2 MT |
246 | static bool hpet_validate_num_timers(void *opaque, int version_id) |
247 | { | |
248 | HPETState *s = opaque; | |
249 | ||
250 | if (s->num_timers < HPET_MIN_TIMERS) { | |
251 | return false; | |
252 | } else if (s->num_timers > HPET_MAX_TIMERS) { | |
253 | return false; | |
254 | } | |
255 | return true; | |
256 | } | |
257 | ||
e59fb374 | 258 | static int hpet_post_load(void *opaque, int version_id) |
16b29ae1 AL |
259 | { |
260 | HPETState *s = opaque; | |
c50c2d68 | 261 | |
16b29ae1 | 262 | /* Recalculate the offset between the main counter and guest time */ |
bc72ad67 | 263 | s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
be4b44c5 JK |
264 | |
265 | /* Push number of timers into capability returned via HPET_ID */ | |
266 | s->capability &= ~HPET_ID_NUM_TIM_MASK; | |
267 | s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; | |
40ac17cd | 268 | hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
8caa0065 JK |
269 | |
270 | /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */ | |
271 | s->flags &= ~(1 << HPET_MSI_SUPPORT); | |
272 | if (s->timer[0].config & HPET_TN_FSB_CAP) { | |
273 | s->flags |= 1 << HPET_MSI_SUPPORT; | |
274 | } | |
16b29ae1 AL |
275 | return 0; |
276 | } | |
277 | ||
5904ae4e JK |
278 | static bool hpet_rtc_irq_level_needed(void *opaque) |
279 | { | |
280 | HPETState *s = opaque; | |
281 | ||
282 | return s->rtc_irq_level != 0; | |
283 | } | |
284 | ||
285 | static const VMStateDescription vmstate_hpet_rtc_irq_level = { | |
286 | .name = "hpet/rtc_irq_level", | |
287 | .version_id = 1, | |
288 | .minimum_version_id = 1, | |
5cd8cada | 289 | .needed = hpet_rtc_irq_level_needed, |
d49805ae | 290 | .fields = (VMStateField[]) { |
5904ae4e JK |
291 | VMSTATE_UINT8(rtc_irq_level, HPETState), |
292 | VMSTATE_END_OF_LIST() | |
293 | } | |
294 | }; | |
295 | ||
e6cb4d45 JQ |
296 | static const VMStateDescription vmstate_hpet_timer = { |
297 | .name = "hpet_timer", | |
298 | .version_id = 1, | |
299 | .minimum_version_id = 1, | |
d49805ae | 300 | .fields = (VMStateField[]) { |
e6cb4d45 JQ |
301 | VMSTATE_UINT8(tn, HPETTimer), |
302 | VMSTATE_UINT64(config, HPETTimer), | |
303 | VMSTATE_UINT64(cmp, HPETTimer), | |
304 | VMSTATE_UINT64(fsb, HPETTimer), | |
305 | VMSTATE_UINT64(period, HPETTimer), | |
306 | VMSTATE_UINT8(wrap_flag, HPETTimer), | |
e720677e | 307 | VMSTATE_TIMER_PTR(qemu_timer, HPETTimer), |
e6cb4d45 JQ |
308 | VMSTATE_END_OF_LIST() |
309 | } | |
310 | }; | |
311 | ||
312 | static const VMStateDescription vmstate_hpet = { | |
313 | .name = "hpet", | |
be4b44c5 | 314 | .version_id = 2, |
e6cb4d45 | 315 | .minimum_version_id = 1, |
e6cb4d45 | 316 | .pre_save = hpet_pre_save, |
be4b44c5 | 317 | .pre_load = hpet_pre_load, |
e6cb4d45 | 318 | .post_load = hpet_post_load, |
d49805ae | 319 | .fields = (VMStateField[]) { |
e6cb4d45 JQ |
320 | VMSTATE_UINT64(config, HPETState), |
321 | VMSTATE_UINT64(isr, HPETState), | |
322 | VMSTATE_UINT64(hpet_counter, HPETState), | |
be4b44c5 | 323 | VMSTATE_UINT8_V(num_timers, HPETState, 2), |
3f1c49e2 | 324 | VMSTATE_VALIDATE("num_timers in range", hpet_validate_num_timers), |
be4b44c5 JK |
325 | VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0, |
326 | vmstate_hpet_timer, HPETTimer), | |
e6cb4d45 | 327 | VMSTATE_END_OF_LIST() |
5904ae4e | 328 | }, |
5cd8cada JQ |
329 | .subsections = (const VMStateDescription*[]) { |
330 | &vmstate_hpet_rtc_irq_level, | |
331 | NULL | |
e6cb4d45 JQ |
332 | } |
333 | }; | |
334 | ||
c50c2d68 | 335 | /* |
16b29ae1 AL |
336 | * timer expiration callback |
337 | */ | |
338 | static void hpet_timer(void *opaque) | |
339 | { | |
27bb0b2d | 340 | HPETTimer *t = opaque; |
16b29ae1 AL |
341 | uint64_t diff; |
342 | ||
343 | uint64_t period = t->period; | |
b7eaa6c7 | 344 | uint64_t cur_tick = hpet_get_ticks(t->state); |
16b29ae1 AL |
345 | |
346 | if (timer_is_periodic(t) && period != 0) { | |
347 | if (t->config & HPET_TN_32BIT) { | |
27bb0b2d | 348 | while (hpet_time_after(cur_tick, t->cmp)) { |
16b29ae1 | 349 | t->cmp = (uint32_t)(t->cmp + t->period); |
27bb0b2d JK |
350 | } |
351 | } else { | |
352 | while (hpet_time_after64(cur_tick, t->cmp)) { | |
16b29ae1 | 353 | t->cmp += period; |
27bb0b2d JK |
354 | } |
355 | } | |
16b29ae1 | 356 | diff = hpet_calculate_diff(t, cur_tick); |
bc72ad67 AB |
357 | timer_mod(t->qemu_timer, |
358 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
359 | } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
360 | if (t->wrap_flag) { | |
361 | diff = hpet_calculate_diff(t, cur_tick); | |
bc72ad67 | 362 | timer_mod(t->qemu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + |
27bb0b2d | 363 | (int64_t)ticks_to_ns(diff)); |
16b29ae1 AL |
364 | t->wrap_flag = 0; |
365 | } | |
366 | } | |
22a9fe38 | 367 | update_irq(t, 1); |
16b29ae1 AL |
368 | } |
369 | ||
370 | static void hpet_set_timer(HPETTimer *t) | |
371 | { | |
372 | uint64_t diff; | |
373 | uint32_t wrap_diff; /* how many ticks until we wrap? */ | |
b7eaa6c7 | 374 | uint64_t cur_tick = hpet_get_ticks(t->state); |
c50c2d68 | 375 | |
16b29ae1 AL |
376 | /* whenever new timer is being set up, make sure wrap_flag is 0 */ |
377 | t->wrap_flag = 0; | |
378 | diff = hpet_calculate_diff(t, cur_tick); | |
379 | ||
c50c2d68 | 380 | /* hpet spec says in one-shot 32-bit mode, generate an interrupt when |
16b29ae1 | 381 | * counter wraps in addition to an interrupt with comparator match. |
c50c2d68 | 382 | */ |
16b29ae1 AL |
383 | if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { |
384 | wrap_diff = 0xffffffff - (uint32_t)cur_tick; | |
385 | if (wrap_diff < (uint32_t)diff) { | |
386 | diff = wrap_diff; | |
c50c2d68 | 387 | t->wrap_flag = 1; |
16b29ae1 AL |
388 | } |
389 | } | |
bc72ad67 AB |
390 | timer_mod(t->qemu_timer, |
391 | qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff)); | |
16b29ae1 AL |
392 | } |
393 | ||
394 | static void hpet_del_timer(HPETTimer *t) | |
395 | { | |
bc72ad67 | 396 | timer_del(t->qemu_timer); |
22a9fe38 | 397 | update_irq(t, 0); |
16b29ae1 AL |
398 | } |
399 | ||
400 | #ifdef HPET_DEBUG | |
a8170e5e | 401 | static uint32_t hpet_ram_readb(void *opaque, hwaddr addr) |
16b29ae1 AL |
402 | { |
403 | printf("qemu: hpet_read b at %" PRIx64 "\n", addr); | |
404 | return 0; | |
405 | } | |
406 | ||
a8170e5e | 407 | static uint32_t hpet_ram_readw(void *opaque, hwaddr addr) |
16b29ae1 AL |
408 | { |
409 | printf("qemu: hpet_read w at %" PRIx64 "\n", addr); | |
410 | return 0; | |
411 | } | |
412 | #endif | |
413 | ||
a8170e5e | 414 | static uint64_t hpet_ram_read(void *opaque, hwaddr addr, |
e977aa37 | 415 | unsigned size) |
16b29ae1 | 416 | { |
27bb0b2d | 417 | HPETState *s = opaque; |
16b29ae1 AL |
418 | uint64_t cur_tick, index; |
419 | ||
d0f2c4c6 | 420 | DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); |
16b29ae1 AL |
421 | index = addr; |
422 | /*address range of all TN regs*/ | |
423 | if (index >= 0x100 && index <= 0x3ff) { | |
424 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
27bb0b2d JK |
425 | HPETTimer *timer = &s->timer[timer_id]; |
426 | ||
be4b44c5 | 427 | if (timer_id > s->num_timers) { |
6982d664 | 428 | DPRINTF("qemu: timer id out of range\n"); |
16b29ae1 AL |
429 | return 0; |
430 | } | |
16b29ae1 AL |
431 | |
432 | switch ((addr - 0x100) % 0x20) { | |
27bb0b2d JK |
433 | case HPET_TN_CFG: |
434 | return timer->config; | |
435 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
436 | return timer->config >> 32; | |
437 | case HPET_TN_CMP: // comparator register | |
438 | return timer->cmp; | |
439 | case HPET_TN_CMP + 4: | |
440 | return timer->cmp >> 32; | |
441 | case HPET_TN_ROUTE: | |
8caa0065 JK |
442 | return timer->fsb; |
443 | case HPET_TN_ROUTE + 4: | |
27bb0b2d JK |
444 | return timer->fsb >> 32; |
445 | default: | |
446 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
447 | break; | |
16b29ae1 AL |
448 | } |
449 | } else { | |
450 | switch (index) { | |
27bb0b2d JK |
451 | case HPET_ID: |
452 | return s->capability; | |
453 | case HPET_PERIOD: | |
454 | return s->capability >> 32; | |
455 | case HPET_CFG: | |
456 | return s->config; | |
457 | case HPET_CFG + 4: | |
b2bedb21 | 458 | DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n"); |
27bb0b2d JK |
459 | return 0; |
460 | case HPET_COUNTER: | |
b7eaa6c7 JK |
461 | if (hpet_enabled(s)) { |
462 | cur_tick = hpet_get_ticks(s); | |
27bb0b2d JK |
463 | } else { |
464 | cur_tick = s->hpet_counter; | |
465 | } | |
466 | DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); | |
467 | return cur_tick; | |
468 | case HPET_COUNTER + 4: | |
b7eaa6c7 JK |
469 | if (hpet_enabled(s)) { |
470 | cur_tick = hpet_get_ticks(s); | |
27bb0b2d JK |
471 | } else { |
472 | cur_tick = s->hpet_counter; | |
473 | } | |
474 | DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); | |
475 | return cur_tick >> 32; | |
476 | case HPET_STATUS: | |
477 | return s->isr; | |
478 | default: | |
479 | DPRINTF("qemu: invalid hpet_ram_readl\n"); | |
480 | break; | |
16b29ae1 AL |
481 | } |
482 | } | |
483 | return 0; | |
484 | } | |
485 | ||
a8170e5e | 486 | static void hpet_ram_write(void *opaque, hwaddr addr, |
e977aa37 | 487 | uint64_t value, unsigned size) |
16b29ae1 AL |
488 | { |
489 | int i; | |
27bb0b2d | 490 | HPETState *s = opaque; |
ce536cfd | 491 | uint64_t old_val, new_val, val, index; |
16b29ae1 | 492 | |
d0f2c4c6 | 493 | DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); |
16b29ae1 | 494 | index = addr; |
e977aa37 | 495 | old_val = hpet_ram_read(opaque, addr, 4); |
16b29ae1 AL |
496 | new_val = value; |
497 | ||
498 | /*address range of all TN regs*/ | |
499 | if (index >= 0x100 && index <= 0x3ff) { | |
500 | uint8_t timer_id = (addr - 0x100) / 0x20; | |
16b29ae1 | 501 | HPETTimer *timer = &s->timer[timer_id]; |
c50c2d68 | 502 | |
b2bedb21 | 503 | DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id); |
be4b44c5 | 504 | if (timer_id > s->num_timers) { |
6982d664 JK |
505 | DPRINTF("qemu: timer id out of range\n"); |
506 | return; | |
507 | } | |
16b29ae1 | 508 | switch ((addr - 0x100) % 0x20) { |
27bb0b2d JK |
509 | case HPET_TN_CFG: |
510 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n"); | |
8caa0065 JK |
511 | if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) { |
512 | update_irq(timer, 0); | |
513 | } | |
27bb0b2d JK |
514 | val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); |
515 | timer->config = (timer->config & 0xffffffff00000000ULL) | val; | |
516 | if (new_val & HPET_TN_32BIT) { | |
517 | timer->cmp = (uint32_t)timer->cmp; | |
518 | timer->period = (uint32_t)timer->period; | |
519 | } | |
c36ad13f ML |
520 | if (activating_bit(old_val, new_val, HPET_TN_ENABLE) && |
521 | hpet_enabled(s)) { | |
9cec89e8 JK |
522 | hpet_set_timer(timer); |
523 | } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) { | |
524 | hpet_del_timer(timer); | |
525 | } | |
27bb0b2d JK |
526 | break; |
527 | case HPET_TN_CFG + 4: // Interrupt capabilities | |
528 | DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n"); | |
529 | break; | |
530 | case HPET_TN_CMP: // comparator register | |
b2bedb21 | 531 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n"); |
27bb0b2d JK |
532 | if (timer->config & HPET_TN_32BIT) { |
533 | new_val = (uint32_t)new_val; | |
534 | } | |
535 | if (!timer_is_periodic(timer) | |
536 | || (timer->config & HPET_TN_SETVAL)) { | |
537 | timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val; | |
538 | } | |
539 | if (timer_is_periodic(timer)) { | |
540 | /* | |
541 | * FIXME: Clamp period to reasonable min value? | |
542 | * Clamp period to reasonable max value | |
543 | */ | |
544 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
545 | timer->period = | |
546 | (timer->period & 0xffffffff00000000ULL) | new_val; | |
547 | } | |
548 | timer->config &= ~HPET_TN_SETVAL; | |
b7eaa6c7 | 549 | if (hpet_enabled(s)) { |
27bb0b2d JK |
550 | hpet_set_timer(timer); |
551 | } | |
552 | break; | |
553 | case HPET_TN_CMP + 4: // comparator register high order | |
554 | DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n"); | |
555 | if (!timer_is_periodic(timer) | |
556 | || (timer->config & HPET_TN_SETVAL)) { | |
557 | timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; | |
558 | } else { | |
559 | /* | |
560 | * FIXME: Clamp period to reasonable min value? | |
561 | * Clamp period to reasonable max value | |
562 | */ | |
563 | new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; | |
564 | timer->period = | |
565 | (timer->period & 0xffffffffULL) | new_val << 32; | |
16b29ae1 AL |
566 | } |
567 | timer->config &= ~HPET_TN_SETVAL; | |
b7eaa6c7 | 568 | if (hpet_enabled(s)) { |
16b29ae1 | 569 | hpet_set_timer(timer); |
16b29ae1 | 570 | } |
16b29ae1 | 571 | break; |
8caa0065 JK |
572 | case HPET_TN_ROUTE: |
573 | timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val; | |
574 | break; | |
27bb0b2d | 575 | case HPET_TN_ROUTE + 4: |
8caa0065 | 576 | timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff); |
27bb0b2d JK |
577 | break; |
578 | default: | |
579 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
580 | break; | |
16b29ae1 AL |
581 | } |
582 | return; | |
583 | } else { | |
584 | switch (index) { | |
27bb0b2d JK |
585 | case HPET_ID: |
586 | return; | |
587 | case HPET_CFG: | |
588 | val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); | |
589 | s->config = (s->config & 0xffffffff00000000ULL) | val; | |
590 | if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { | |
591 | /* Enable main counter and interrupt generation. */ | |
592 | s->hpet_offset = | |
bc72ad67 | 593 | ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); |
be4b44c5 | 594 | for (i = 0; i < s->num_timers; i++) { |
27bb0b2d JK |
595 | if ((&s->timer[i])->cmp != ~0ULL) { |
596 | hpet_set_timer(&s->timer[i]); | |
597 | } | |
16b29ae1 | 598 | } |
27bb0b2d JK |
599 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { |
600 | /* Halt main counter and disable interrupt generation. */ | |
b7eaa6c7 | 601 | s->hpet_counter = hpet_get_ticks(s); |
be4b44c5 | 602 | for (i = 0; i < s->num_timers; i++) { |
27bb0b2d | 603 | hpet_del_timer(&s->timer[i]); |
16b29ae1 | 604 | } |
27bb0b2d | 605 | } |
ce967e2f JK |
606 | /* i8254 and RTC output pins are disabled |
607 | * when HPET is in legacy mode */ | |
27bb0b2d | 608 | if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
ce967e2f JK |
609 | qemu_set_irq(s->pit_enabled, 0); |
610 | qemu_irq_lower(s->irqs[0]); | |
7d932dfd | 611 | qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); |
27bb0b2d | 612 | } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { |
ce967e2f JK |
613 | qemu_irq_lower(s->irqs[0]); |
614 | qemu_set_irq(s->pit_enabled, 1); | |
7d932dfd | 615 | qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); |
27bb0b2d JK |
616 | } |
617 | break; | |
618 | case HPET_CFG + 4: | |
b2bedb21 | 619 | DPRINTF("qemu: invalid HPET_CFG+4 write\n"); |
27bb0b2d JK |
620 | break; |
621 | case HPET_STATUS: | |
22a9fe38 | 622 | val = new_val & s->isr; |
be4b44c5 | 623 | for (i = 0; i < s->num_timers; i++) { |
22a9fe38 JK |
624 | if (val & (1 << i)) { |
625 | update_irq(&s->timer[i], 0); | |
626 | } | |
627 | } | |
27bb0b2d JK |
628 | break; |
629 | case HPET_COUNTER: | |
b7eaa6c7 | 630 | if (hpet_enabled(s)) { |
ad0a6551 | 631 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
632 | } |
633 | s->hpet_counter = | |
634 | (s->hpet_counter & 0xffffffff00000000ULL) | value; | |
635 | DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", | |
636 | value, s->hpet_counter); | |
637 | break; | |
638 | case HPET_COUNTER + 4: | |
b7eaa6c7 | 639 | if (hpet_enabled(s)) { |
ad0a6551 | 640 | DPRINTF("qemu: Writing counter while HPET enabled!\n"); |
27bb0b2d JK |
641 | } |
642 | s->hpet_counter = | |
643 | (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); | |
644 | DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", | |
645 | value, s->hpet_counter); | |
646 | break; | |
647 | default: | |
648 | DPRINTF("qemu: invalid hpet_ram_writel\n"); | |
649 | break; | |
16b29ae1 AL |
650 | } |
651 | } | |
652 | } | |
653 | ||
e977aa37 AK |
654 | static const MemoryRegionOps hpet_ram_ops = { |
655 | .read = hpet_ram_read, | |
656 | .write = hpet_ram_write, | |
657 | .valid = { | |
658 | .min_access_size = 4, | |
659 | .max_access_size = 4, | |
660 | }, | |
661 | .endianness = DEVICE_NATIVE_ENDIAN, | |
16b29ae1 AL |
662 | }; |
663 | ||
822557eb | 664 | static void hpet_reset(DeviceState *d) |
27bb0b2d | 665 | { |
02f9a6f5 HT |
666 | HPETState *s = HPET(d); |
667 | SysBusDevice *sbd = SYS_BUS_DEVICE(d); | |
16b29ae1 | 668 | int i; |
16b29ae1 | 669 | |
be4b44c5 | 670 | for (i = 0; i < s->num_timers; i++) { |
16b29ae1 | 671 | HPETTimer *timer = &s->timer[i]; |
27bb0b2d | 672 | |
16b29ae1 | 673 | hpet_del_timer(timer); |
16b29ae1 | 674 | timer->cmp = ~0ULL; |
8caa0065 JK |
675 | timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; |
676 | if (s->flags & (1 << HPET_MSI_SUPPORT)) { | |
677 | timer->config |= HPET_TN_FSB_CAP; | |
678 | } | |
7a10ef51 LPF |
679 | /* advertise availability of ioapic int */ |
680 | timer->config |= (uint64_t)s->intcap << 32; | |
16b29ae1 AL |
681 | timer->period = 0ULL; |
682 | timer->wrap_flag = 0; | |
683 | } | |
684 | ||
ce967e2f | 685 | qemu_set_irq(s->pit_enabled, 1); |
16b29ae1 AL |
686 | s->hpet_counter = 0ULL; |
687 | s->hpet_offset = 0ULL; | |
7d93b1fa | 688 | s->config = 0ULL; |
40ac17cd | 689 | hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; |
02f9a6f5 | 690 | hpet_cfg.hpet[s->hpet_id].address = sbd->mmio[0].addr; |
5904ae4e JK |
691 | |
692 | /* to document that the RTC lowers its output on reset as well */ | |
693 | s->rtc_irq_level = 0; | |
16b29ae1 AL |
694 | } |
695 | ||
ce967e2f | 696 | static void hpet_handle_legacy_irq(void *opaque, int n, int level) |
7d932dfd | 697 | { |
02f9a6f5 | 698 | HPETState *s = HPET(opaque); |
7d932dfd | 699 | |
ce967e2f JK |
700 | if (n == HPET_LEGACY_PIT_INT) { |
701 | if (!hpet_in_legacy_mode(s)) { | |
702 | qemu_set_irq(s->irqs[0], level); | |
703 | } | |
704 | } else { | |
705 | s->rtc_irq_level = level; | |
706 | if (!hpet_in_legacy_mode(s)) { | |
707 | qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); | |
708 | } | |
7d932dfd JK |
709 | } |
710 | } | |
711 | ||
726887ef | 712 | static void hpet_init(Object *obj) |
27bb0b2d | 713 | { |
726887ef HT |
714 | SysBusDevice *sbd = SYS_BUS_DEVICE(obj); |
715 | HPETState *s = HPET(obj); | |
716 | ||
717 | /* HPET Area */ | |
a57d708d | 718 | memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_LEN); |
726887ef HT |
719 | sysbus_init_mmio(sbd, &s->iomem); |
720 | } | |
721 | ||
722 | static void hpet_realize(DeviceState *dev, Error **errp) | |
723 | { | |
724 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
02f9a6f5 | 725 | HPETState *s = HPET(dev); |
e977aa37 | 726 | int i; |
27bb0b2d | 727 | HPETTimer *timer; |
16b29ae1 | 728 | |
7a10ef51 LPF |
729 | if (!s->intcap) { |
730 | error_printf("Hpet's intcap not initialized.\n"); | |
731 | } | |
d2c5efd8 SW |
732 | if (hpet_cfg.count == UINT8_MAX) { |
733 | /* first instance */ | |
40ac17cd | 734 | hpet_cfg.count = 0; |
d2c5efd8 | 735 | } |
40ac17cd GN |
736 | |
737 | if (hpet_cfg.count == 8) { | |
726887ef HT |
738 | error_setg(errp, "Only 8 instances of HPET is allowed"); |
739 | return; | |
40ac17cd GN |
740 | } |
741 | ||
742 | s->hpet_id = hpet_cfg.count++; | |
743 | ||
822557eb | 744 | for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { |
726887ef | 745 | sysbus_init_irq(sbd, &s->irqs[i]); |
822557eb | 746 | } |
be4b44c5 JK |
747 | |
748 | if (s->num_timers < HPET_MIN_TIMERS) { | |
749 | s->num_timers = HPET_MIN_TIMERS; | |
750 | } else if (s->num_timers > HPET_MAX_TIMERS) { | |
751 | s->num_timers = HPET_MAX_TIMERS; | |
752 | } | |
753 | for (i = 0; i < HPET_MAX_TIMERS; i++) { | |
27bb0b2d | 754 | timer = &s->timer[i]; |
bc72ad67 | 755 | timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer); |
7afbecc9 JK |
756 | timer->tn = i; |
757 | timer->state = s; | |
16b29ae1 | 758 | } |
822557eb | 759 | |
072c2c31 JK |
760 | /* 64-bit main counter; LegacyReplacementRoute. */ |
761 | s->capability = 0x8086a001ULL; | |
762 | s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; | |
0a4f9240 | 763 | s->capability |= ((uint64_t)(HPET_CLK_PERIOD * FS_PER_NS) << 32); |
072c2c31 | 764 | |
726887ef HT |
765 | qdev_init_gpio_in(dev, hpet_handle_legacy_irq, 2); |
766 | qdev_init_gpio_out(dev, &s->pit_enabled, 1); | |
16b29ae1 | 767 | } |
822557eb | 768 | |
999e12bb AL |
769 | static Property hpet_device_properties[] = { |
770 | DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS), | |
771 | DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false), | |
7a10ef51 | 772 | DEFINE_PROP_UINT32(HPET_INTCAP, HPETState, intcap, 0), |
999e12bb AL |
773 | DEFINE_PROP_END_OF_LIST(), |
774 | }; | |
775 | ||
776 | static void hpet_device_class_init(ObjectClass *klass, void *data) | |
777 | { | |
39bffca2 | 778 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 779 | |
726887ef | 780 | dc->realize = hpet_realize; |
39bffca2 AL |
781 | dc->reset = hpet_reset; |
782 | dc->vmsd = &vmstate_hpet; | |
783 | dc->props = hpet_device_properties; | |
999e12bb AL |
784 | } |
785 | ||
8c43a6f0 | 786 | static const TypeInfo hpet_device_info = { |
02f9a6f5 | 787 | .name = TYPE_HPET, |
39bffca2 AL |
788 | .parent = TYPE_SYS_BUS_DEVICE, |
789 | .instance_size = sizeof(HPETState), | |
726887ef | 790 | .instance_init = hpet_init, |
39bffca2 | 791 | .class_init = hpet_device_class_init, |
822557eb JK |
792 | }; |
793 | ||
83f7d43a | 794 | static void hpet_register_types(void) |
822557eb | 795 | { |
39bffca2 | 796 | type_register_static(&hpet_device_info); |
822557eb JK |
797 | } |
798 | ||
83f7d43a | 799 | type_init(hpet_register_types) |