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Commit | Line | Data |
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a50c0d6f JCD |
1 | /* |
2 | * IMX EPIT Timer | |
3 | * | |
4 | * Copyright (c) 2008 OK Labs | |
5 | * Copyright (c) 2011 NICTA Pty Ltd | |
6 | * Originally written by Hans Jiang | |
7 | * Updated by Peter Chubb | |
951cd00e | 8 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
a50c0d6f JCD |
9 | * |
10 | * This code is licensed under GPL version 2 or later. See | |
11 | * the COPYING file in the top-level directory. | |
12 | * | |
13 | */ | |
14 | ||
8ef94f0b | 15 | #include "qemu/osdep.h" |
951cd00e JCD |
16 | #include "hw/timer/imx_epit.h" |
17 | #include "hw/misc/imx_ccm.h" | |
6a1751b7 | 18 | #include "qemu/main-loop.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
03dd024f | 20 | #include "qemu/log.h" |
a50c0d6f | 21 | |
4929f656 JCD |
22 | #ifndef DEBUG_IMX_EPIT |
23 | #define DEBUG_IMX_EPIT 0 | |
24 | #endif | |
25 | ||
26 | #define DPRINTF(fmt, args...) \ | |
27 | do { \ | |
28 | if (DEBUG_IMX_EPIT) { \ | |
29 | fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_EPIT, \ | |
30 | __func__, ##args); \ | |
31 | } \ | |
32 | } while (0) | |
95669e69 | 33 | |
d675765a | 34 | static const char *imx_epit_reg_name(uint32_t reg) |
95669e69 JCD |
35 | { |
36 | switch (reg) { | |
37 | case 0: | |
38 | return "CR"; | |
39 | case 1: | |
40 | return "SR"; | |
41 | case 2: | |
42 | return "LR"; | |
43 | case 3: | |
44 | return "CMP"; | |
45 | case 4: | |
46 | return "CNT"; | |
47 | default: | |
48 | return "[?]"; | |
49 | } | |
50 | } | |
51 | ||
a50c0d6f JCD |
52 | /* |
53 | * Exact clock frequencies vary from board to board. | |
54 | * These are typical. | |
55 | */ | |
95669e69 | 56 | static const IMXClk imx_epit_clocks[] = { |
d552f675 JCD |
57 | CLK_NONE, /* 00 disabled */ |
58 | CLK_IPG, /* 01 ipg_clk, ~532MHz */ | |
59 | CLK_IPG_HIGH, /* 10 ipg_clk_highfreq */ | |
60 | CLK_32k, /* 11 ipg_clk_32k -- ~32kHz */ | |
a50c0d6f JCD |
61 | }; |
62 | ||
a50c0d6f JCD |
63 | /* |
64 | * Update interrupt status | |
65 | */ | |
95669e69 | 66 | static void imx_epit_update_int(IMXEPITState *s) |
a50c0d6f | 67 | { |
95669e69 | 68 | if (s->sr && (s->cr & CR_OCIEN) && (s->cr & CR_EN)) { |
a50c0d6f JCD |
69 | qemu_irq_raise(s->irq); |
70 | } else { | |
71 | qemu_irq_lower(s->irq); | |
72 | } | |
73 | } | |
74 | ||
95669e69 | 75 | static void imx_epit_set_freq(IMXEPITState *s) |
a50c0d6f | 76 | { |
95669e69 JCD |
77 | uint32_t clksrc; |
78 | uint32_t prescaler; | |
a50c0d6f JCD |
79 | |
80 | clksrc = extract32(s->cr, CR_CLKSRC_SHIFT, 2); | |
81 | prescaler = 1 + extract32(s->cr, CR_PRESCALE_SHIFT, 12); | |
82 | ||
aaa9ec3b JCD |
83 | s->freq = imx_ccm_get_clock_frequency(s->ccm, |
84 | imx_epit_clocks[clksrc]) / prescaler; | |
a50c0d6f | 85 | |
aaa9ec3b | 86 | DPRINTF("Setting ptimer frequency to %u\n", s->freq); |
95669e69 | 87 | |
aaa9ec3b JCD |
88 | if (s->freq) { |
89 | ptimer_set_freq(s->timer_reload, s->freq); | |
90 | ptimer_set_freq(s->timer_cmp, s->freq); | |
a50c0d6f JCD |
91 | } |
92 | } | |
93 | ||
95669e69 | 94 | static void imx_epit_reset(DeviceState *dev) |
a50c0d6f | 95 | { |
95669e69 | 96 | IMXEPITState *s = IMX_EPIT(dev); |
a50c0d6f JCD |
97 | |
98 | /* | |
99 | * Soft reset doesn't touch some bits; hard reset clears them | |
100 | */ | |
23005810 | 101 | s->cr &= (CR_EN|CR_ENMOD|CR_STOPEN|CR_DOZEN|CR_WAITEN|CR_DBGEN); |
a50c0d6f | 102 | s->sr = 0; |
203d65a4 | 103 | s->lr = EPIT_TIMER_MAX; |
a50c0d6f JCD |
104 | s->cmp = 0; |
105 | s->cnt = 0; | |
106 | /* stop both timers */ | |
107 | ptimer_stop(s->timer_cmp); | |
108 | ptimer_stop(s->timer_reload); | |
109 | /* compute new frequency */ | |
95669e69 | 110 | imx_epit_set_freq(s); |
203d65a4 MT |
111 | /* init both timers to EPIT_TIMER_MAX */ |
112 | ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); | |
113 | ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); | |
a50c0d6f JCD |
114 | if (s->freq && (s->cr & CR_EN)) { |
115 | /* if the timer is still enabled, restart it */ | |
23005810 | 116 | ptimer_run(s->timer_reload, 0); |
a50c0d6f JCD |
117 | } |
118 | } | |
119 | ||
95669e69 | 120 | static uint32_t imx_epit_update_count(IMXEPITState *s) |
a50c0d6f | 121 | { |
565328fc | 122 | s->cnt = ptimer_get_count(s->timer_reload); |
a50c0d6f | 123 | |
565328fc | 124 | return s->cnt; |
a50c0d6f JCD |
125 | } |
126 | ||
95669e69 | 127 | static uint64_t imx_epit_read(void *opaque, hwaddr offset, unsigned size) |
a50c0d6f | 128 | { |
95669e69 JCD |
129 | IMXEPITState *s = IMX_EPIT(opaque); |
130 | uint32_t reg_value = 0; | |
a50c0d6f | 131 | |
4929f656 | 132 | switch (offset >> 2) { |
a50c0d6f | 133 | case 0: /* Control Register */ |
95669e69 JCD |
134 | reg_value = s->cr; |
135 | break; | |
a50c0d6f JCD |
136 | |
137 | case 1: /* Status Register */ | |
95669e69 JCD |
138 | reg_value = s->sr; |
139 | break; | |
a50c0d6f JCD |
140 | |
141 | case 2: /* LR - ticks*/ | |
95669e69 JCD |
142 | reg_value = s->lr; |
143 | break; | |
a50c0d6f JCD |
144 | |
145 | case 3: /* CMP */ | |
95669e69 JCD |
146 | reg_value = s->cmp; |
147 | break; | |
a50c0d6f JCD |
148 | |
149 | case 4: /* CNT */ | |
95669e69 JCD |
150 | imx_epit_update_count(s); |
151 | reg_value = s->cnt; | |
152 | break; | |
153 | ||
154 | default: | |
4929f656 JCD |
155 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
156 | HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); | |
95669e69 | 157 | break; |
a50c0d6f JCD |
158 | } |
159 | ||
4929f656 | 160 | DPRINTF("(%s) = 0x%08x\n", imx_epit_reg_name(offset >> 2), reg_value); |
95669e69 JCD |
161 | |
162 | return reg_value; | |
a50c0d6f JCD |
163 | } |
164 | ||
95669e69 | 165 | static void imx_epit_reload_compare_timer(IMXEPITState *s) |
a50c0d6f | 166 | { |
23005810 PC |
167 | if ((s->cr & (CR_EN | CR_OCIEN)) == (CR_EN | CR_OCIEN)) { |
168 | /* if the compare feature is on and timers are running */ | |
95669e69 | 169 | uint32_t tmp = imx_epit_update_count(s); |
23005810 | 170 | uint64_t next; |
a50c0d6f | 171 | if (tmp > s->cmp) { |
23005810 PC |
172 | /* It'll fire in this round of the timer */ |
173 | next = tmp - s->cmp; | |
174 | } else { /* catch it next time around */ | |
203d65a4 | 175 | next = tmp - s->cmp + ((s->cr & CR_RLD) ? EPIT_TIMER_MAX : s->lr); |
a50c0d6f | 176 | } |
23005810 | 177 | ptimer_set_count(s->timer_cmp, next); |
a50c0d6f JCD |
178 | } |
179 | } | |
180 | ||
95669e69 JCD |
181 | static void imx_epit_write(void *opaque, hwaddr offset, uint64_t value, |
182 | unsigned size) | |
a50c0d6f | 183 | { |
95669e69 | 184 | IMXEPITState *s = IMX_EPIT(opaque); |
23005810 | 185 | uint64_t oldcr; |
95669e69 | 186 | |
4929f656 JCD |
187 | DPRINTF("(%s, value = 0x%08x)\n", imx_epit_reg_name(offset >> 2), |
188 | (uint32_t)value); | |
a50c0d6f | 189 | |
4929f656 | 190 | switch (offset >> 2) { |
a50c0d6f | 191 | case 0: /* CR */ |
23005810 PC |
192 | |
193 | oldcr = s->cr; | |
a50c0d6f JCD |
194 | s->cr = value & 0x03ffffff; |
195 | if (s->cr & CR_SWR) { | |
196 | /* handle the reset */ | |
95669e69 | 197 | imx_epit_reset(DEVICE(s)); |
a50c0d6f | 198 | } else { |
95669e69 | 199 | imx_epit_set_freq(s); |
a50c0d6f JCD |
200 | } |
201 | ||
23005810 | 202 | if (s->freq && (s->cr & CR_EN) && !(oldcr & CR_EN)) { |
a50c0d6f JCD |
203 | if (s->cr & CR_ENMOD) { |
204 | if (s->cr & CR_RLD) { | |
205 | ptimer_set_limit(s->timer_reload, s->lr, 1); | |
23005810 | 206 | ptimer_set_limit(s->timer_cmp, s->lr, 1); |
a50c0d6f | 207 | } else { |
203d65a4 MT |
208 | ptimer_set_limit(s->timer_reload, EPIT_TIMER_MAX, 1); |
209 | ptimer_set_limit(s->timer_cmp, EPIT_TIMER_MAX, 1); | |
a50c0d6f JCD |
210 | } |
211 | } | |
212 | ||
95669e69 | 213 | imx_epit_reload_compare_timer(s); |
23005810 PC |
214 | ptimer_run(s->timer_reload, 0); |
215 | if (s->cr & CR_OCIEN) { | |
216 | ptimer_run(s->timer_cmp, 0); | |
217 | } else { | |
218 | ptimer_stop(s->timer_cmp); | |
219 | } | |
220 | } else if (!(s->cr & CR_EN)) { | |
a50c0d6f JCD |
221 | /* stop both timers */ |
222 | ptimer_stop(s->timer_reload); | |
223 | ptimer_stop(s->timer_cmp); | |
23005810 PC |
224 | } else if (s->cr & CR_OCIEN) { |
225 | if (!(oldcr & CR_OCIEN)) { | |
226 | imx_epit_reload_compare_timer(s); | |
227 | ptimer_run(s->timer_cmp, 0); | |
228 | } | |
229 | } else { | |
230 | ptimer_stop(s->timer_cmp); | |
a50c0d6f JCD |
231 | } |
232 | break; | |
233 | ||
234 | case 1: /* SR - ACK*/ | |
235 | /* writing 1 to OCIF clear the OCIF bit */ | |
236 | if (value & 0x01) { | |
237 | s->sr = 0; | |
95669e69 | 238 | imx_epit_update_int(s); |
a50c0d6f JCD |
239 | } |
240 | break; | |
241 | ||
242 | case 2: /* LR - set ticks */ | |
243 | s->lr = value; | |
244 | ||
245 | if (s->cr & CR_RLD) { | |
246 | /* Also set the limit if the LRD bit is set */ | |
247 | /* If IOVW bit is set then set the timer value */ | |
248 | ptimer_set_limit(s->timer_reload, s->lr, s->cr & CR_IOVW); | |
23005810 | 249 | ptimer_set_limit(s->timer_cmp, s->lr, 0); |
a50c0d6f JCD |
250 | } else if (s->cr & CR_IOVW) { |
251 | /* If IOVW bit is set then set the timer value */ | |
252 | ptimer_set_count(s->timer_reload, s->lr); | |
253 | } | |
254 | ||
95669e69 | 255 | imx_epit_reload_compare_timer(s); |
a50c0d6f JCD |
256 | break; |
257 | ||
258 | case 3: /* CMP */ | |
259 | s->cmp = value; | |
260 | ||
95669e69 | 261 | imx_epit_reload_compare_timer(s); |
a50c0d6f JCD |
262 | |
263 | break; | |
264 | ||
265 | default: | |
4929f656 JCD |
266 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
267 | HWADDR_PRIx "\n", TYPE_IMX_EPIT, __func__, offset); | |
95669e69 JCD |
268 | |
269 | break; | |
a50c0d6f JCD |
270 | } |
271 | } | |
95669e69 | 272 | static void imx_epit_cmp(void *opaque) |
a50c0d6f | 273 | { |
95669e69 | 274 | IMXEPITState *s = IMX_EPIT(opaque); |
a50c0d6f | 275 | |
23005810 | 276 | DPRINTF("sr was %d\n", s->sr); |
a50c0d6f | 277 | |
23005810 PC |
278 | s->sr = 1; |
279 | imx_epit_update_int(s); | |
a50c0d6f JCD |
280 | } |
281 | ||
95669e69 | 282 | static const MemoryRegionOps imx_epit_ops = { |
565328fc JCD |
283 | .read = imx_epit_read, |
284 | .write = imx_epit_write, | |
285 | .endianness = DEVICE_NATIVE_ENDIAN, | |
a50c0d6f JCD |
286 | }; |
287 | ||
95669e69 | 288 | static const VMStateDescription vmstate_imx_timer_epit = { |
565328fc | 289 | .name = TYPE_IMX_EPIT, |
a50c0d6f JCD |
290 | .version_id = 2, |
291 | .minimum_version_id = 2, | |
8f1e884b | 292 | .fields = (VMStateField[]) { |
95669e69 JCD |
293 | VMSTATE_UINT32(cr, IMXEPITState), |
294 | VMSTATE_UINT32(sr, IMXEPITState), | |
295 | VMSTATE_UINT32(lr, IMXEPITState), | |
296 | VMSTATE_UINT32(cmp, IMXEPITState), | |
297 | VMSTATE_UINT32(cnt, IMXEPITState), | |
298 | VMSTATE_UINT32(freq, IMXEPITState), | |
299 | VMSTATE_PTIMER(timer_reload, IMXEPITState), | |
300 | VMSTATE_PTIMER(timer_cmp, IMXEPITState), | |
a50c0d6f JCD |
301 | VMSTATE_END_OF_LIST() |
302 | } | |
303 | }; | |
304 | ||
95669e69 | 305 | static void imx_epit_realize(DeviceState *dev, Error **errp) |
a50c0d6f | 306 | { |
95669e69 JCD |
307 | IMXEPITState *s = IMX_EPIT(dev); |
308 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
a50c0d6f JCD |
309 | QEMUBH *bh; |
310 | ||
95669e69 JCD |
311 | DPRINTF("\n"); |
312 | ||
313 | sysbus_init_irq(sbd, &s->irq); | |
853dca12 | 314 | memory_region_init_io(&s->iomem, OBJECT(s), &imx_epit_ops, s, TYPE_IMX_EPIT, |
a50c0d6f | 315 | 0x00001000); |
95669e69 | 316 | sysbus_init_mmio(sbd, &s->iomem); |
a50c0d6f | 317 | |
e7ea81c3 | 318 | s->timer_reload = ptimer_init(NULL, PTIMER_POLICY_DEFAULT); |
a50c0d6f | 319 | |
95669e69 | 320 | bh = qemu_bh_new(imx_epit_cmp, s); |
e7ea81c3 | 321 | s->timer_cmp = ptimer_init(bh, PTIMER_POLICY_DEFAULT); |
a50c0d6f JCD |
322 | } |
323 | ||
95669e69 | 324 | static void imx_epit_class_init(ObjectClass *klass, void *data) |
a50c0d6f JCD |
325 | { |
326 | DeviceClass *dc = DEVICE_CLASS(klass); | |
95669e69 JCD |
327 | |
328 | dc->realize = imx_epit_realize; | |
329 | dc->reset = imx_epit_reset; | |
330 | dc->vmsd = &vmstate_imx_timer_epit; | |
a50c0d6f JCD |
331 | dc->desc = "i.MX periodic timer"; |
332 | } | |
333 | ||
95669e69 JCD |
334 | static const TypeInfo imx_epit_info = { |
335 | .name = TYPE_IMX_EPIT, | |
a50c0d6f | 336 | .parent = TYPE_SYS_BUS_DEVICE, |
95669e69 JCD |
337 | .instance_size = sizeof(IMXEPITState), |
338 | .class_init = imx_epit_class_init, | |
a50c0d6f JCD |
339 | }; |
340 | ||
95669e69 | 341 | static void imx_epit_register_types(void) |
a50c0d6f | 342 | { |
95669e69 | 343 | type_register_static(&imx_epit_info); |
a50c0d6f JCD |
344 | } |
345 | ||
95669e69 | 346 | type_init(imx_epit_register_types) |