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Commit | Line | Data |
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78d1404d | 1 | /* |
a50c0d6f | 2 | * IMX GPT Timer |
78d1404d PC |
3 | * |
4 | * Copyright (c) 2008 OK Labs | |
5 | * Copyright (c) 2011 NICTA Pty Ltd | |
aade7b91 | 6 | * Originally written by Hans Jiang |
78d1404d | 7 | * Updated by Peter Chubb |
d647b26d | 8 | * Updated by Jean-Christophe Dubois <jcd@tribudubois.net> |
78d1404d | 9 | * |
aade7b91 | 10 | * This code is licensed under GPL version 2 or later. See |
78d1404d PC |
11 | * the COPYING file in the top-level directory. |
12 | * | |
13 | */ | |
14 | ||
8ef94f0b | 15 | #include "qemu/osdep.h" |
64552b6b | 16 | #include "hw/irq.h" |
d647b26d | 17 | #include "hw/timer/imx_gpt.h" |
d6454270 | 18 | #include "migration/vmstate.h" |
0b8fa32f | 19 | #include "qemu/module.h" |
03dd024f | 20 | #include "qemu/log.h" |
78d1404d | 21 | |
05453526 JCD |
22 | #ifndef DEBUG_IMX_GPT |
23 | #define DEBUG_IMX_GPT 0 | |
24 | #endif | |
25 | ||
26 | #define DPRINTF(fmt, args...) \ | |
27 | do { \ | |
28 | if (DEBUG_IMX_GPT) { \ | |
29 | fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \ | |
30 | __func__, ##args); \ | |
31 | } \ | |
32 | } while (0) | |
5ec694b5 | 33 | |
d675765a | 34 | static const char *imx_gpt_reg_name(uint32_t reg) |
5ec694b5 JCD |
35 | { |
36 | switch (reg) { | |
37 | case 0: | |
38 | return "CR"; | |
39 | case 1: | |
40 | return "PR"; | |
41 | case 2: | |
42 | return "SR"; | |
43 | case 3: | |
44 | return "IR"; | |
45 | case 4: | |
46 | return "OCR1"; | |
47 | case 5: | |
48 | return "OCR2"; | |
49 | case 6: | |
50 | return "OCR3"; | |
51 | case 7: | |
52 | return "ICR1"; | |
53 | case 8: | |
54 | return "ICR2"; | |
55 | case 9: | |
56 | return "CNT"; | |
57 | default: | |
58 | return "[?]"; | |
59 | } | |
60 | } | |
61 | ||
67110c3e | 62 | static const VMStateDescription vmstate_imx_timer_gpt = { |
68b85290 | 63 | .name = TYPE_IMX_GPT, |
5ec694b5 JCD |
64 | .version_id = 3, |
65 | .minimum_version_id = 3, | |
8f1e884b | 66 | .fields = (VMStateField[]) { |
67110c3e JCD |
67 | VMSTATE_UINT32(cr, IMXGPTState), |
68 | VMSTATE_UINT32(pr, IMXGPTState), | |
69 | VMSTATE_UINT32(sr, IMXGPTState), | |
70 | VMSTATE_UINT32(ir, IMXGPTState), | |
71 | VMSTATE_UINT32(ocr1, IMXGPTState), | |
72 | VMSTATE_UINT32(ocr2, IMXGPTState), | |
73 | VMSTATE_UINT32(ocr3, IMXGPTState), | |
74 | VMSTATE_UINT32(icr1, IMXGPTState), | |
75 | VMSTATE_UINT32(icr2, IMXGPTState), | |
76 | VMSTATE_UINT32(cnt, IMXGPTState), | |
77 | VMSTATE_UINT32(next_timeout, IMXGPTState), | |
78 | VMSTATE_UINT32(next_int, IMXGPTState), | |
79 | VMSTATE_UINT32(freq, IMXGPTState), | |
80 | VMSTATE_PTIMER(timer, IMXGPTState), | |
78d1404d PC |
81 | VMSTATE_END_OF_LIST() |
82 | } | |
83 | }; | |
84 | ||
66542f63 JCD |
85 | static const IMXClk imx25_gpt_clocks[] = { |
86 | CLK_NONE, /* 000 No clock source */ | |
87 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ | |
88 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ | |
89 | CLK_NONE, /* 011 not defined */ | |
90 | CLK_32k, /* 100 ipg_clk_32k */ | |
91 | CLK_32k, /* 101 ipg_clk_32k */ | |
92 | CLK_32k, /* 110 ipg_clk_32k */ | |
93 | CLK_32k, /* 111 ipg_clk_32k */ | |
94 | }; | |
95 | ||
96 | static const IMXClk imx31_gpt_clocks[] = { | |
d552f675 JCD |
97 | CLK_NONE, /* 000 No clock source */ |
98 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ | |
99 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ | |
100 | CLK_NONE, /* 011 not defined */ | |
101 | CLK_32k, /* 100 ipg_clk_32k */ | |
102 | CLK_NONE, /* 101 not defined */ | |
103 | CLK_NONE, /* 110 not defined */ | |
104 | CLK_NONE, /* 111 not defined */ | |
78d1404d PC |
105 | }; |
106 | ||
66542f63 JCD |
107 | static const IMXClk imx6_gpt_clocks[] = { |
108 | CLK_NONE, /* 000 No clock source */ | |
109 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ | |
110 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ | |
111 | CLK_EXT, /* 011 External clock */ | |
112 | CLK_32k, /* 100 ipg_clk_32k */ | |
113 | CLK_HIGH_DIV, /* 101 reference clock / 8 */ | |
114 | CLK_NONE, /* 110 not defined */ | |
115 | CLK_HIGH, /* 111 reference clock */ | |
116 | }; | |
117 | ||
a62bf59f AS |
118 | static const IMXClk imx7_gpt_clocks[] = { |
119 | CLK_NONE, /* 000 No clock source */ | |
120 | CLK_IPG, /* 001 ipg_clk, 532MHz*/ | |
121 | CLK_IPG_HIGH, /* 010 ipg_clk_highfreq */ | |
122 | CLK_EXT, /* 011 External clock */ | |
123 | CLK_32k, /* 100 ipg_clk_32k */ | |
124 | CLK_HIGH, /* 101 reference clock */ | |
125 | CLK_NONE, /* 110 not defined */ | |
126 | CLK_NONE, /* 111 not defined */ | |
127 | }; | |
128 | ||
1b914994 | 129 | /* Must be called from within ptimer_transaction_begin/commit block */ |
67110c3e | 130 | static void imx_gpt_set_freq(IMXGPTState *s) |
78d1404d | 131 | { |
5ec694b5 | 132 | uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3); |
78d1404d | 133 | |
aaa9ec3b | 134 | s->freq = imx_ccm_get_clock_frequency(s->ccm, |
66542f63 | 135 | s->clocks[clksrc]) / (1 + s->pr); |
a50c0d6f | 136 | |
aaa9ec3b JCD |
137 | DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq); |
138 | ||
139 | if (s->freq) { | |
140 | ptimer_set_freq(s->timer, s->freq); | |
78d1404d PC |
141 | } |
142 | } | |
143 | ||
67110c3e | 144 | static void imx_gpt_update_int(IMXGPTState *s) |
78d1404d | 145 | { |
5ec694b5 JCD |
146 | if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) { |
147 | qemu_irq_raise(s->irq); | |
148 | } else { | |
149 | qemu_irq_lower(s->irq); | |
150 | } | |
78d1404d PC |
151 | } |
152 | ||
67110c3e | 153 | static uint32_t imx_gpt_update_count(IMXGPTState *s) |
78d1404d | 154 | { |
5ec694b5 JCD |
155 | s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer); |
156 | ||
78d1404d PC |
157 | return s->cnt; |
158 | } | |
159 | ||
67110c3e | 160 | static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg, |
68b85290 | 161 | uint32_t timeout) |
78d1404d | 162 | { |
5ec694b5 JCD |
163 | if ((count < reg) && (timeout > reg)) { |
164 | timeout = reg; | |
165 | } | |
166 | ||
167 | return timeout; | |
168 | } | |
78d1404d | 169 | |
1b914994 | 170 | /* Must be called from within ptimer_transaction_begin/commit block */ |
67110c3e | 171 | static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event) |
5ec694b5 | 172 | { |
203d65a4 | 173 | uint32_t timeout = GPT_TIMER_MAX; |
4833e15f | 174 | uint32_t count; |
5ec694b5 JCD |
175 | long long limit; |
176 | ||
177 | if (!(s->cr & GPT_CR_EN)) { | |
178 | /* if not enabled just return */ | |
78d1404d PC |
179 | return; |
180 | } | |
181 | ||
4833e15f JCD |
182 | /* update the count */ |
183 | count = imx_gpt_update_count(s); | |
5ec694b5 | 184 | |
4833e15f JCD |
185 | if (event) { |
186 | /* | |
187 | * This is an event (the ptimer reached 0 and stopped), and the | |
188 | * timer counter is now equal to s->next_timeout. | |
189 | */ | |
190 | if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) { | |
191 | /* We are in restart mode and we crossed the compare channel 1 | |
192 | * value. We need to reset the counter to 0. | |
5ec694b5 | 193 | */ |
4833e15f JCD |
194 | count = s->cnt = s->next_timeout = 0; |
195 | } else if (count == GPT_TIMER_MAX) { | |
196 | /* We reached GPT_TIMER_MAX so we need to rollover */ | |
197 | count = s->cnt = s->next_timeout = 0; | |
5ec694b5 | 198 | } |
5ec694b5 JCD |
199 | } |
200 | ||
201 | /* now, find the next timeout related to count */ | |
202 | ||
203 | if (s->ir & GPT_IR_OF1IE) { | |
67110c3e | 204 | timeout = imx_gpt_find_limit(count, s->ocr1, timeout); |
5ec694b5 JCD |
205 | } |
206 | if (s->ir & GPT_IR_OF2IE) { | |
67110c3e | 207 | timeout = imx_gpt_find_limit(count, s->ocr2, timeout); |
5ec694b5 JCD |
208 | } |
209 | if (s->ir & GPT_IR_OF3IE) { | |
67110c3e | 210 | timeout = imx_gpt_find_limit(count, s->ocr3, timeout); |
5ec694b5 JCD |
211 | } |
212 | ||
213 | /* find the next set of interrupts to raise for next timer event */ | |
214 | ||
215 | s->next_int = 0; | |
216 | if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) { | |
217 | s->next_int |= GPT_SR_OF1; | |
218 | } | |
219 | if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) { | |
220 | s->next_int |= GPT_SR_OF2; | |
221 | } | |
222 | if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) { | |
223 | s->next_int |= GPT_SR_OF3; | |
224 | } | |
203d65a4 | 225 | if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) { |
5ec694b5 JCD |
226 | s->next_int |= GPT_SR_ROV; |
227 | } | |
228 | ||
229 | /* the new range to count down from */ | |
67110c3e | 230 | limit = timeout - imx_gpt_update_count(s); |
5ec694b5 JCD |
231 | |
232 | if (limit < 0) { | |
233 | /* | |
234 | * if we reach here, then QEMU is running too slow and we pass the | |
235 | * timeout limit while computing it. Let's deliver the interrupt | |
236 | * and compute a new limit. | |
237 | */ | |
238 | s->sr |= s->next_int; | |
239 | ||
67110c3e | 240 | imx_gpt_compute_next_timeout(s, event); |
5ec694b5 | 241 | |
67110c3e | 242 | imx_gpt_update_int(s); |
5ec694b5 JCD |
243 | } else { |
244 | /* New timeout value */ | |
245 | s->next_timeout = timeout; | |
246 | ||
247 | /* reset the limit to the computed range */ | |
248 | ptimer_set_limit(s->timer, limit, 1); | |
78d1404d | 249 | } |
78d1404d PC |
250 | } |
251 | ||
67110c3e | 252 | static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size) |
78d1404d | 253 | { |
67110c3e | 254 | IMXGPTState *s = IMX_GPT(opaque); |
5ec694b5 | 255 | uint32_t reg_value = 0; |
78d1404d | 256 | |
05453526 | 257 | switch (offset >> 2) { |
78d1404d | 258 | case 0: /* Control Register */ |
5ec694b5 JCD |
259 | reg_value = s->cr; |
260 | break; | |
78d1404d PC |
261 | |
262 | case 1: /* prescaler */ | |
5ec694b5 JCD |
263 | reg_value = s->pr; |
264 | break; | |
78d1404d PC |
265 | |
266 | case 2: /* Status Register */ | |
5ec694b5 JCD |
267 | reg_value = s->sr; |
268 | break; | |
78d1404d PC |
269 | |
270 | case 3: /* Interrupt Register */ | |
5ec694b5 JCD |
271 | reg_value = s->ir; |
272 | break; | |
78d1404d PC |
273 | |
274 | case 4: /* Output Compare Register 1 */ | |
5ec694b5 JCD |
275 | reg_value = s->ocr1; |
276 | break; | |
78d1404d | 277 | |
462566fc | 278 | case 5: /* Output Compare Register 2 */ |
5ec694b5 JCD |
279 | reg_value = s->ocr2; |
280 | break; | |
462566fc JCD |
281 | |
282 | case 6: /* Output Compare Register 3 */ | |
5ec694b5 JCD |
283 | reg_value = s->ocr3; |
284 | break; | |
462566fc JCD |
285 | |
286 | case 7: /* input Capture Register 1 */ | |
05453526 JCD |
287 | qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n", |
288 | TYPE_IMX_GPT, __func__); | |
5ec694b5 JCD |
289 | reg_value = s->icr1; |
290 | break; | |
462566fc JCD |
291 | |
292 | case 8: /* input Capture Register 2 */ | |
05453526 JCD |
293 | qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n", |
294 | TYPE_IMX_GPT, __func__); | |
5ec694b5 JCD |
295 | reg_value = s->icr2; |
296 | break; | |
78d1404d PC |
297 | |
298 | case 9: /* cnt */ | |
67110c3e | 299 | imx_gpt_update_count(s); |
5ec694b5 JCD |
300 | reg_value = s->cnt; |
301 | break; | |
302 | ||
303 | default: | |
05453526 JCD |
304 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
305 | HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); | |
5ec694b5 | 306 | break; |
78d1404d PC |
307 | } |
308 | ||
05453526 | 309 | DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value); |
462566fc | 310 | |
5ec694b5 | 311 | return reg_value; |
78d1404d PC |
312 | } |
313 | ||
78d1404d | 314 | |
c98c9eba KM |
315 | static void imx_gpt_reset_common(IMXGPTState *s, bool is_soft_reset) |
316 | { | |
1b914994 | 317 | ptimer_transaction_begin(s->timer); |
5ec694b5 JCD |
318 | /* stop timer */ |
319 | ptimer_stop(s->timer); | |
320 | ||
c98c9eba KM |
321 | /* Soft reset and hard reset differ only in their handling of the CR |
322 | * register -- soft reset preserves the values of some bits there. | |
78d1404d | 323 | */ |
c98c9eba KM |
324 | if (is_soft_reset) { |
325 | /* Clear all CR bits except those that are preserved by soft reset. */ | |
326 | s->cr &= GPT_CR_EN | GPT_CR_ENMOD | GPT_CR_STOPEN | GPT_CR_DOZEN | | |
327 | GPT_CR_WAITEN | GPT_CR_DBGEN | | |
328 | (GPT_CR_CLKSRC_MASK << GPT_CR_CLKSRC_SHIFT); | |
329 | } else { | |
330 | s->cr = 0; | |
331 | } | |
78d1404d PC |
332 | s->sr = 0; |
333 | s->pr = 0; | |
334 | s->ir = 0; | |
335 | s->cnt = 0; | |
203d65a4 MT |
336 | s->ocr1 = GPT_TIMER_MAX; |
337 | s->ocr2 = GPT_TIMER_MAX; | |
338 | s->ocr3 = GPT_TIMER_MAX; | |
462566fc JCD |
339 | s->icr1 = 0; |
340 | s->icr2 = 0; | |
5ec694b5 | 341 | |
203d65a4 | 342 | s->next_timeout = GPT_TIMER_MAX; |
5ec694b5 JCD |
343 | s->next_int = 0; |
344 | ||
345 | /* compute new freq */ | |
67110c3e | 346 | imx_gpt_set_freq(s); |
5ec694b5 | 347 | |
203d65a4 MT |
348 | /* reset the limit to GPT_TIMER_MAX */ |
349 | ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); | |
5ec694b5 JCD |
350 | |
351 | /* if the timer is still enabled, restart it */ | |
352 | if (s->freq && (s->cr & GPT_CR_EN)) { | |
353 | ptimer_run(s->timer, 1); | |
354 | } | |
1b914994 | 355 | ptimer_transaction_commit(s->timer); |
78d1404d PC |
356 | } |
357 | ||
c98c9eba KM |
358 | static void imx_gpt_soft_reset(DeviceState *dev) |
359 | { | |
360 | IMXGPTState *s = IMX_GPT(dev); | |
361 | imx_gpt_reset_common(s, true); | |
362 | } | |
363 | ||
364 | static void imx_gpt_reset(DeviceState *dev) | |
365 | { | |
366 | IMXGPTState *s = IMX_GPT(dev); | |
367 | imx_gpt_reset_common(s, false); | |
368 | } | |
369 | ||
67110c3e JCD |
370 | static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value, |
371 | unsigned size) | |
78d1404d | 372 | { |
67110c3e | 373 | IMXGPTState *s = IMX_GPT(opaque); |
5ec694b5 | 374 | uint32_t oldreg; |
5ec694b5 | 375 | |
05453526 | 376 | DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2), |
5ec694b5 JCD |
377 | (uint32_t)value); |
378 | ||
05453526 | 379 | switch (offset >> 2) { |
5ec694b5 JCD |
380 | case 0: |
381 | oldreg = s->cr; | |
382 | s->cr = value & ~0x7c14; | |
383 | if (s->cr & GPT_CR_SWR) { /* force reset */ | |
384 | /* handle the reset */ | |
c98c9eba | 385 | imx_gpt_soft_reset(DEVICE(s)); |
5ec694b5 JCD |
386 | } else { |
387 | /* set our freq, as the source might have changed */ | |
1b914994 | 388 | ptimer_transaction_begin(s->timer); |
67110c3e | 389 | imx_gpt_set_freq(s); |
5ec694b5 JCD |
390 | |
391 | if ((oldreg ^ s->cr) & GPT_CR_EN) { | |
392 | if (s->cr & GPT_CR_EN) { | |
393 | if (s->cr & GPT_CR_ENMOD) { | |
203d65a4 MT |
394 | s->next_timeout = GPT_TIMER_MAX; |
395 | ptimer_set_count(s->timer, GPT_TIMER_MAX); | |
67110c3e | 396 | imx_gpt_compute_next_timeout(s, false); |
5ec694b5 JCD |
397 | } |
398 | ptimer_run(s->timer, 1); | |
399 | } else { | |
400 | /* stop timer */ | |
401 | ptimer_stop(s->timer); | |
78d1404d | 402 | } |
5ec694b5 | 403 | } |
1b914994 | 404 | ptimer_transaction_commit(s->timer); |
78d1404d | 405 | } |
5ec694b5 | 406 | break; |
78d1404d PC |
407 | |
408 | case 1: /* Prescaler */ | |
409 | s->pr = value & 0xfff; | |
1b914994 | 410 | ptimer_transaction_begin(s->timer); |
67110c3e | 411 | imx_gpt_set_freq(s); |
1b914994 | 412 | ptimer_transaction_commit(s->timer); |
5ec694b5 | 413 | break; |
78d1404d PC |
414 | |
415 | case 2: /* SR */ | |
5ec694b5 | 416 | s->sr &= ~(value & 0x3f); |
67110c3e | 417 | imx_gpt_update_int(s); |
5ec694b5 | 418 | break; |
78d1404d PC |
419 | |
420 | case 3: /* IR -- interrupt register */ | |
421 | s->ir = value & 0x3f; | |
67110c3e | 422 | imx_gpt_update_int(s); |
5ec694b5 | 423 | |
1b914994 | 424 | ptimer_transaction_begin(s->timer); |
67110c3e | 425 | imx_gpt_compute_next_timeout(s, false); |
1b914994 | 426 | ptimer_transaction_commit(s->timer); |
5ec694b5 JCD |
427 | |
428 | break; | |
78d1404d PC |
429 | |
430 | case 4: /* OCR1 -- output compare register */ | |
5ec694b5 JCD |
431 | s->ocr1 = value; |
432 | ||
1b914994 | 433 | ptimer_transaction_begin(s->timer); |
78d1404d PC |
434 | /* In non-freerun mode, reset count when this register is written */ |
435 | if (!(s->cr & GPT_CR_FRR)) { | |
203d65a4 MT |
436 | s->next_timeout = GPT_TIMER_MAX; |
437 | ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1); | |
78d1404d | 438 | } |
5ec694b5 JCD |
439 | |
440 | /* compute the new timeout */ | |
67110c3e | 441 | imx_gpt_compute_next_timeout(s, false); |
1b914994 | 442 | ptimer_transaction_commit(s->timer); |
5ec694b5 JCD |
443 | |
444 | break; | |
78d1404d | 445 | |
462566fc | 446 | case 5: /* OCR2 -- output compare register */ |
5ec694b5 JCD |
447 | s->ocr2 = value; |
448 | ||
449 | /* compute the new timeout */ | |
1b914994 | 450 | ptimer_transaction_begin(s->timer); |
67110c3e | 451 | imx_gpt_compute_next_timeout(s, false); |
1b914994 | 452 | ptimer_transaction_commit(s->timer); |
5ec694b5 JCD |
453 | |
454 | break; | |
455 | ||
462566fc | 456 | case 6: /* OCR3 -- output compare register */ |
5ec694b5 JCD |
457 | s->ocr3 = value; |
458 | ||
459 | /* compute the new timeout */ | |
1b914994 | 460 | ptimer_transaction_begin(s->timer); |
67110c3e | 461 | imx_gpt_compute_next_timeout(s, false); |
1b914994 | 462 | ptimer_transaction_commit(s->timer); |
5ec694b5 JCD |
463 | |
464 | break; | |
465 | ||
78d1404d | 466 | default: |
05453526 JCD |
467 | qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%" |
468 | HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset); | |
5ec694b5 | 469 | break; |
78d1404d PC |
470 | } |
471 | } | |
472 | ||
67110c3e | 473 | static void imx_gpt_timeout(void *opaque) |
78d1404d | 474 | { |
67110c3e | 475 | IMXGPTState *s = IMX_GPT(opaque); |
78d1404d | 476 | |
5ec694b5 | 477 | DPRINTF("\n"); |
78d1404d | 478 | |
5ec694b5 JCD |
479 | s->sr |= s->next_int; |
480 | s->next_int = 0; | |
481 | ||
67110c3e | 482 | imx_gpt_compute_next_timeout(s, true); |
78d1404d | 483 | |
67110c3e | 484 | imx_gpt_update_int(s); |
5ec694b5 JCD |
485 | |
486 | if (s->freq && (s->cr & GPT_CR_EN)) { | |
487 | ptimer_run(s->timer, 1); | |
488 | } | |
78d1404d PC |
489 | } |
490 | ||
67110c3e JCD |
491 | static const MemoryRegionOps imx_gpt_ops = { |
492 | .read = imx_gpt_read, | |
493 | .write = imx_gpt_write, | |
78d1404d PC |
494 | .endianness = DEVICE_NATIVE_ENDIAN, |
495 | }; | |
496 | ||
497 | ||
67110c3e | 498 | static void imx_gpt_realize(DeviceState *dev, Error **errp) |
78d1404d | 499 | { |
67110c3e JCD |
500 | IMXGPTState *s = IMX_GPT(dev); |
501 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); | |
78d1404d | 502 | |
67110c3e | 503 | sysbus_init_irq(sbd, &s->irq); |
853dca12 | 504 | memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT, |
78d1404d | 505 | 0x00001000); |
67110c3e | 506 | sysbus_init_mmio(sbd, &s->iomem); |
78d1404d | 507 | |
1b914994 | 508 | s->timer = ptimer_init(imx_gpt_timeout, s, PTIMER_POLICY_DEFAULT); |
78d1404d PC |
509 | } |
510 | ||
67110c3e | 511 | static void imx_gpt_class_init(ObjectClass *klass, void *data) |
78d1404d | 512 | { |
67110c3e JCD |
513 | DeviceClass *dc = DEVICE_CLASS(klass); |
514 | ||
515 | dc->realize = imx_gpt_realize; | |
516 | dc->reset = imx_gpt_reset; | |
517 | dc->vmsd = &vmstate_imx_timer_gpt; | |
78d1404d PC |
518 | dc->desc = "i.MX general timer"; |
519 | } | |
520 | ||
66542f63 JCD |
521 | static void imx25_gpt_init(Object *obj) |
522 | { | |
523 | IMXGPTState *s = IMX_GPT(obj); | |
524 | ||
525 | s->clocks = imx25_gpt_clocks; | |
526 | } | |
527 | ||
528 | static void imx31_gpt_init(Object *obj) | |
529 | { | |
530 | IMXGPTState *s = IMX_GPT(obj); | |
531 | ||
532 | s->clocks = imx31_gpt_clocks; | |
533 | } | |
534 | ||
535 | static void imx6_gpt_init(Object *obj) | |
536 | { | |
537 | IMXGPTState *s = IMX_GPT(obj); | |
538 | ||
539 | s->clocks = imx6_gpt_clocks; | |
540 | } | |
541 | ||
a62bf59f AS |
542 | static void imx7_gpt_init(Object *obj) |
543 | { | |
544 | IMXGPTState *s = IMX_GPT(obj); | |
545 | ||
546 | s->clocks = imx7_gpt_clocks; | |
547 | } | |
548 | ||
66542f63 JCD |
549 | static const TypeInfo imx25_gpt_info = { |
550 | .name = TYPE_IMX25_GPT, | |
78d1404d | 551 | .parent = TYPE_SYS_BUS_DEVICE, |
67110c3e | 552 | .instance_size = sizeof(IMXGPTState), |
66542f63 | 553 | .instance_init = imx25_gpt_init, |
67110c3e | 554 | .class_init = imx_gpt_class_init, |
78d1404d PC |
555 | }; |
556 | ||
66542f63 JCD |
557 | static const TypeInfo imx31_gpt_info = { |
558 | .name = TYPE_IMX31_GPT, | |
559 | .parent = TYPE_IMX25_GPT, | |
560 | .instance_init = imx31_gpt_init, | |
561 | }; | |
562 | ||
563 | static const TypeInfo imx6_gpt_info = { | |
564 | .name = TYPE_IMX6_GPT, | |
565 | .parent = TYPE_IMX25_GPT, | |
566 | .instance_init = imx6_gpt_init, | |
567 | }; | |
568 | ||
a62bf59f AS |
569 | static const TypeInfo imx7_gpt_info = { |
570 | .name = TYPE_IMX7_GPT, | |
571 | .parent = TYPE_IMX25_GPT, | |
572 | .instance_init = imx7_gpt_init, | |
573 | }; | |
574 | ||
67110c3e | 575 | static void imx_gpt_register_types(void) |
78d1404d | 576 | { |
66542f63 JCD |
577 | type_register_static(&imx25_gpt_info); |
578 | type_register_static(&imx31_gpt_info); | |
579 | type_register_static(&imx6_gpt_info); | |
a62bf59f | 580 | type_register_static(&imx7_gpt_info); |
78d1404d PC |
581 | } |
582 | ||
67110c3e | 583 | type_init(imx_gpt_register_types) |