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ea7924dc MW |
1 | /* |
2 | * QEMU model of the LatticeMico32 timer block. | |
3 | * | |
4 | * Copyright (c) 2010 Michael Walle <michael@walle.cc> | |
5 | * | |
6 | * This library is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU Lesser General Public | |
8 | * License as published by the Free Software Foundation; either | |
61f3c91a | 9 | * version 2.1 of the License, or (at your option) any later version. |
ea7924dc MW |
10 | * |
11 | * This library is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
14 | * Lesser General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU Lesser General Public | |
17 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
18 | * | |
19 | * | |
20 | * Specification available at: | |
21 | * http://www.latticesemi.com/documents/mico32timer.pdf | |
22 | */ | |
23 | ||
ea99dde1 | 24 | #include "qemu/osdep.h" |
64552b6b | 25 | #include "hw/irq.h" |
83c9f4ca | 26 | #include "hw/sysbus.h" |
d6454270 | 27 | #include "migration/vmstate.h" |
ea7924dc | 28 | #include "trace.h" |
1de7afc9 | 29 | #include "qemu/timer.h" |
83c9f4ca | 30 | #include "hw/ptimer.h" |
a27bd6c7 | 31 | #include "hw/qdev-properties.h" |
1de7afc9 | 32 | #include "qemu/error-report.h" |
0b8fa32f | 33 | #include "qemu/module.h" |
db1015e9 | 34 | #include "qom/object.h" |
ea7924dc MW |
35 | |
36 | #define DEFAULT_FREQUENCY (50*1000000) | |
37 | ||
38 | enum { | |
39 | R_SR = 0, | |
40 | R_CR, | |
41 | R_PERIOD, | |
42 | R_SNAPSHOT, | |
43 | R_MAX | |
44 | }; | |
45 | ||
46 | enum { | |
47 | SR_TO = (1 << 0), | |
48 | SR_RUN = (1 << 1), | |
49 | }; | |
50 | ||
51 | enum { | |
52 | CR_ITO = (1 << 0), | |
53 | CR_CONT = (1 << 1), | |
54 | CR_START = (1 << 2), | |
55 | CR_STOP = (1 << 3), | |
56 | }; | |
57 | ||
fe54d857 | 58 | #define TYPE_LM32_TIMER "lm32-timer" |
8063396b | 59 | OBJECT_DECLARE_SIMPLE_TYPE(LM32TimerState, LM32_TIMER) |
fe54d857 | 60 | |
ea7924dc | 61 | struct LM32TimerState { |
fe54d857 AF |
62 | SysBusDevice parent_obj; |
63 | ||
d09510b2 | 64 | MemoryRegion iomem; |
ea7924dc | 65 | |
ea7924dc MW |
66 | ptimer_state *ptimer; |
67 | ||
68 | qemu_irq irq; | |
69 | uint32_t freq_hz; | |
70 | ||
71 | uint32_t regs[R_MAX]; | |
72 | }; | |
ea7924dc MW |
73 | |
74 | static void timer_update_irq(LM32TimerState *s) | |
75 | { | |
76 | int state = (s->regs[R_SR] & SR_TO) && (s->regs[R_CR] & CR_ITO); | |
77 | ||
78 | trace_lm32_timer_irq_state(state); | |
79 | qemu_set_irq(s->irq, state); | |
80 | } | |
81 | ||
a8170e5e | 82 | static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size) |
ea7924dc MW |
83 | { |
84 | LM32TimerState *s = opaque; | |
85 | uint32_t r = 0; | |
86 | ||
87 | addr >>= 2; | |
88 | switch (addr) { | |
89 | case R_SR: | |
90 | case R_CR: | |
91 | case R_PERIOD: | |
92 | r = s->regs[addr]; | |
93 | break; | |
94 | case R_SNAPSHOT: | |
95 | r = (uint32_t)ptimer_get_count(s->ptimer); | |
96 | break; | |
97 | default: | |
dd3d6775 | 98 | error_report("lm32_timer: read access to unknown register 0x" |
ea7924dc MW |
99 | TARGET_FMT_plx, addr << 2); |
100 | break; | |
101 | } | |
102 | ||
103 | trace_lm32_timer_memory_read(addr << 2, r); | |
104 | return r; | |
105 | } | |
106 | ||
a8170e5e | 107 | static void timer_write(void *opaque, hwaddr addr, |
d09510b2 | 108 | uint64_t value, unsigned size) |
ea7924dc MW |
109 | { |
110 | LM32TimerState *s = opaque; | |
111 | ||
112 | trace_lm32_timer_memory_write(addr, value); | |
113 | ||
114 | addr >>= 2; | |
115 | switch (addr) { | |
116 | case R_SR: | |
117 | s->regs[R_SR] &= ~SR_TO; | |
118 | break; | |
119 | case R_CR: | |
b360a65c | 120 | ptimer_transaction_begin(s->ptimer); |
ea7924dc MW |
121 | s->regs[R_CR] = value; |
122 | if (s->regs[R_CR] & CR_START) { | |
123 | ptimer_run(s->ptimer, 1); | |
124 | } | |
125 | if (s->regs[R_CR] & CR_STOP) { | |
126 | ptimer_stop(s->ptimer); | |
127 | } | |
b360a65c | 128 | ptimer_transaction_commit(s->ptimer); |
ea7924dc MW |
129 | break; |
130 | case R_PERIOD: | |
131 | s->regs[R_PERIOD] = value; | |
b360a65c | 132 | ptimer_transaction_begin(s->ptimer); |
ea7924dc | 133 | ptimer_set_count(s->ptimer, value); |
b360a65c | 134 | ptimer_transaction_commit(s->ptimer); |
ea7924dc MW |
135 | break; |
136 | case R_SNAPSHOT: | |
137 | error_report("lm32_timer: write access to read only register 0x" | |
138 | TARGET_FMT_plx, addr << 2); | |
139 | break; | |
140 | default: | |
dd3d6775 | 141 | error_report("lm32_timer: write access to unknown register 0x" |
ea7924dc MW |
142 | TARGET_FMT_plx, addr << 2); |
143 | break; | |
144 | } | |
145 | timer_update_irq(s); | |
146 | } | |
147 | ||
d09510b2 AK |
148 | static const MemoryRegionOps timer_ops = { |
149 | .read = timer_read, | |
150 | .write = timer_write, | |
151 | .endianness = DEVICE_NATIVE_ENDIAN, | |
152 | .valid = { | |
153 | .min_access_size = 4, | |
154 | .max_access_size = 4, | |
155 | }, | |
ea7924dc MW |
156 | }; |
157 | ||
158 | static void timer_hit(void *opaque) | |
159 | { | |
160 | LM32TimerState *s = opaque; | |
161 | ||
162 | trace_lm32_timer_hit(); | |
163 | ||
164 | s->regs[R_SR] |= SR_TO; | |
165 | ||
166 | if (s->regs[R_CR] & CR_CONT) { | |
167 | ptimer_set_count(s->ptimer, s->regs[R_PERIOD]); | |
168 | ptimer_run(s->ptimer, 1); | |
169 | } | |
170 | timer_update_irq(s); | |
171 | } | |
172 | ||
173 | static void timer_reset(DeviceState *d) | |
174 | { | |
fe54d857 | 175 | LM32TimerState *s = LM32_TIMER(d); |
ea7924dc MW |
176 | int i; |
177 | ||
178 | for (i = 0; i < R_MAX; i++) { | |
179 | s->regs[i] = 0; | |
180 | } | |
b360a65c | 181 | ptimer_transaction_begin(s->ptimer); |
ea7924dc | 182 | ptimer_stop(s->ptimer); |
b360a65c | 183 | ptimer_transaction_commit(s->ptimer); |
ea7924dc MW |
184 | } |
185 | ||
a18eac52 | 186 | static void lm32_timer_init(Object *obj) |
ea7924dc | 187 | { |
a18eac52 XZ |
188 | LM32TimerState *s = LM32_TIMER(obj); |
189 | SysBusDevice *dev = SYS_BUS_DEVICE(obj); | |
ea7924dc MW |
190 | |
191 | sysbus_init_irq(dev, &s->irq); | |
192 | ||
a18eac52 | 193 | memory_region_init_io(&s->iomem, obj, &timer_ops, s, |
853dca12 | 194 | "timer", R_MAX * 4); |
750ecd44 | 195 | sysbus_init_mmio(dev, &s->iomem); |
a18eac52 | 196 | } |
ea7924dc | 197 | |
a18eac52 XZ |
198 | static void lm32_timer_realize(DeviceState *dev, Error **errp) |
199 | { | |
200 | LM32TimerState *s = LM32_TIMER(dev); | |
201 | ||
b360a65c | 202 | s->ptimer = ptimer_init(timer_hit, s, PTIMER_POLICY_DEFAULT); |
e97dd6b2 | 203 | |
b360a65c | 204 | ptimer_transaction_begin(s->ptimer); |
a18eac52 | 205 | ptimer_set_freq(s->ptimer, s->freq_hz); |
b360a65c | 206 | ptimer_transaction_commit(s->ptimer); |
ea7924dc MW |
207 | } |
208 | ||
209 | static const VMStateDescription vmstate_lm32_timer = { | |
210 | .name = "lm32-timer", | |
211 | .version_id = 1, | |
212 | .minimum_version_id = 1, | |
35d08458 | 213 | .fields = (VMStateField[]) { |
ea7924dc MW |
214 | VMSTATE_PTIMER(ptimer, LM32TimerState), |
215 | VMSTATE_UINT32(freq_hz, LM32TimerState), | |
216 | VMSTATE_UINT32_ARRAY(regs, LM32TimerState, R_MAX), | |
217 | VMSTATE_END_OF_LIST() | |
218 | } | |
219 | }; | |
220 | ||
999e12bb AL |
221 | static Property lm32_timer_properties[] = { |
222 | DEFINE_PROP_UINT32("frequency", LM32TimerState, freq_hz, DEFAULT_FREQUENCY), | |
223 | DEFINE_PROP_END_OF_LIST(), | |
224 | }; | |
225 | ||
226 | static void lm32_timer_class_init(ObjectClass *klass, void *data) | |
227 | { | |
39bffca2 | 228 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 229 | |
a18eac52 | 230 | dc->realize = lm32_timer_realize; |
39bffca2 AL |
231 | dc->reset = timer_reset; |
232 | dc->vmsd = &vmstate_lm32_timer; | |
4f67d30b | 233 | device_class_set_props(dc, lm32_timer_properties); |
999e12bb AL |
234 | } |
235 | ||
8c43a6f0 | 236 | static const TypeInfo lm32_timer_info = { |
fe54d857 | 237 | .name = TYPE_LM32_TIMER, |
39bffca2 AL |
238 | .parent = TYPE_SYS_BUS_DEVICE, |
239 | .instance_size = sizeof(LM32TimerState), | |
a18eac52 | 240 | .instance_init = lm32_timer_init, |
39bffca2 | 241 | .class_init = lm32_timer_class_init, |
ea7924dc MW |
242 | }; |
243 | ||
83f7d43a | 244 | static void lm32_timer_register_types(void) |
ea7924dc | 245 | { |
39bffca2 | 246 | type_register_static(&lm32_timer_info); |
ea7924dc MW |
247 | } |
248 | ||
83f7d43a | 249 | type_init(lm32_timer_register_types) |