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Commit | Line | Data |
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a541f297 | 1 | /* |
819385c5 | 2 | * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms |
5fafdf24 | 3 | * |
3ccacc4a | 4 | * Copyright (c) 2003-2005, 2007 Jocelyn Mayer |
5fafdf24 | 5 | * |
a541f297 FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
83c9f4ca | 24 | #include "hw/hw.h" |
0d09e41a | 25 | #include "hw/timer/m48t59.h" |
1de7afc9 | 26 | #include "qemu/timer.h" |
9c17d615 | 27 | #include "sysemu/sysemu.h" |
83c9f4ca | 28 | #include "hw/sysbus.h" |
0d09e41a | 29 | #include "hw/isa/isa.h" |
022c62cb | 30 | #include "exec/address-spaces.h" |
a541f297 | 31 | |
13ab5daa | 32 | //#define DEBUG_NVRAM |
a541f297 | 33 | |
13ab5daa | 34 | #if defined(DEBUG_NVRAM) |
001faf32 | 35 | #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0) |
a541f297 | 36 | #else |
001faf32 | 37 | #define NVRAM_PRINTF(fmt, ...) do { } while (0) |
a541f297 FB |
38 | #endif |
39 | ||
819385c5 | 40 | /* |
4aed2c33 | 41 | * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has |
819385c5 FB |
42 | * alarm and a watchdog timer and related control registers. In the |
43 | * PPC platform there is also a nvram lock function. | |
44 | */ | |
930f3fe1 BS |
45 | |
46 | /* | |
47 | * Chipset docs: | |
48 | * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf | |
49 | * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf | |
50 | * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf | |
51 | */ | |
52 | ||
43a34704 | 53 | struct M48t59State { |
a541f297 | 54 | /* Hardware parameters */ |
d537cf6c | 55 | qemu_irq IRQ; |
5a31cd68 | 56 | MemoryRegion iomem; |
a541f297 | 57 | uint32_t io_base; |
ee6847d1 | 58 | uint32_t size; |
a541f297 FB |
59 | /* RTC management */ |
60 | time_t time_offset; | |
61 | time_t stop_time; | |
62 | /* Alarm & watchdog */ | |
f6503059 | 63 | struct tm alarm; |
a541f297 FB |
64 | struct QEMUTimer *alrm_timer; |
65 | struct QEMUTimer *wd_timer; | |
66 | /* NVRAM storage */ | |
a541f297 | 67 | uint8_t *buffer; |
42c812b9 | 68 | /* Model parameters */ |
7bc3018b | 69 | uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */ |
42c812b9 BS |
70 | /* NVRAM storage */ |
71 | uint16_t addr; | |
72 | uint8_t lock; | |
c5df018e | 73 | }; |
a541f297 | 74 | |
a2772c70 AF |
75 | #define TYPE_ISA_M48T59 "m48t59_isa" |
76 | #define ISA_M48T59(obj) \ | |
77 | OBJECT_CHECK(M48t59ISAState, (obj), TYPE_ISA_M48T59) | |
78 | ||
f80237d4 | 79 | typedef struct M48t59ISAState { |
a2772c70 AF |
80 | ISADevice parent_obj; |
81 | ||
43a34704 | 82 | M48t59State state; |
9936d6e4 | 83 | MemoryRegion io; |
f80237d4 BS |
84 | } M48t59ISAState; |
85 | ||
29d1ffc3 AF |
86 | #define SYSBUS_M48T59(obj) \ |
87 | OBJECT_CHECK(M48t59SysBusState, (obj), TYPE_SYSBUS_M48T59) | |
88 | ||
f80237d4 | 89 | typedef struct M48t59SysBusState { |
29d1ffc3 AF |
90 | SysBusDevice parent_obj; |
91 | ||
43a34704 | 92 | M48t59State state; |
087bd055 | 93 | MemoryRegion io; |
f80237d4 BS |
94 | } M48t59SysBusState; |
95 | ||
a541f297 | 96 | /* Fake timer functions */ |
a541f297 | 97 | |
a541f297 FB |
98 | /* Alarm management */ |
99 | static void alarm_cb (void *opaque) | |
100 | { | |
f6503059 | 101 | struct tm tm; |
a541f297 | 102 | uint64_t next_time; |
43a34704 | 103 | M48t59State *NVRAM = opaque; |
a541f297 | 104 | |
d537cf6c | 105 | qemu_set_irq(NVRAM->IRQ, 1); |
5fafdf24 | 106 | if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && |
a541f297 FB |
107 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && |
108 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
109 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
110 | /* Repeat once a month */ |
111 | qemu_get_timedate(&tm, NVRAM->time_offset); | |
112 | tm.tm_mon++; | |
113 | if (tm.tm_mon == 13) { | |
114 | tm.tm_mon = 1; | |
115 | tm.tm_year++; | |
116 | } | |
117 | next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset; | |
a541f297 FB |
118 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
119 | (NVRAM->buffer[0x1FF4] & 0x80) == 0 && | |
120 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
121 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
122 | /* Repeat once a day */ |
123 | next_time = 24 * 60 * 60; | |
a541f297 FB |
124 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
125 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
126 | (NVRAM->buffer[0x1FF3] & 0x80) == 0 && | |
127 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
128 | /* Repeat once an hour */ |
129 | next_time = 60 * 60; | |
a541f297 FB |
130 | } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 && |
131 | (NVRAM->buffer[0x1FF4] & 0x80) != 0 && | |
132 | (NVRAM->buffer[0x1FF3] & 0x80) != 0 && | |
133 | (NVRAM->buffer[0x1FF2] & 0x80) == 0) { | |
f6503059 AZ |
134 | /* Repeat once a minute */ |
135 | next_time = 60; | |
a541f297 | 136 | } else { |
f6503059 AZ |
137 | /* Repeat once a second */ |
138 | next_time = 1; | |
a541f297 | 139 | } |
bc72ad67 | 140 | timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) + |
f6503059 | 141 | next_time * 1000); |
d537cf6c | 142 | qemu_set_irq(NVRAM->IRQ, 0); |
a541f297 FB |
143 | } |
144 | ||
43a34704 | 145 | static void set_alarm(M48t59State *NVRAM) |
f6503059 AZ |
146 | { |
147 | int diff; | |
148 | if (NVRAM->alrm_timer != NULL) { | |
bc72ad67 | 149 | timer_del(NVRAM->alrm_timer); |
f6503059 AZ |
150 | diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset; |
151 | if (diff > 0) | |
bc72ad67 | 152 | timer_mod(NVRAM->alrm_timer, diff * 1000); |
f6503059 AZ |
153 | } |
154 | } | |
a541f297 | 155 | |
f6503059 | 156 | /* RTC management helpers */ |
43a34704 | 157 | static inline void get_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 158 | { |
f6503059 | 159 | qemu_get_timedate(tm, NVRAM->time_offset); |
a541f297 FB |
160 | } |
161 | ||
43a34704 | 162 | static void set_time(M48t59State *NVRAM, struct tm *tm) |
a541f297 | 163 | { |
f6503059 AZ |
164 | NVRAM->time_offset = qemu_timedate_diff(tm); |
165 | set_alarm(NVRAM); | |
a541f297 FB |
166 | } |
167 | ||
168 | /* Watchdog management */ | |
169 | static void watchdog_cb (void *opaque) | |
170 | { | |
43a34704 | 171 | M48t59State *NVRAM = opaque; |
a541f297 FB |
172 | |
173 | NVRAM->buffer[0x1FF0] |= 0x80; | |
174 | if (NVRAM->buffer[0x1FF7] & 0x80) { | |
175 | NVRAM->buffer[0x1FF7] = 0x00; | |
176 | NVRAM->buffer[0x1FFC] &= ~0x40; | |
13ab5daa | 177 | /* May it be a hw CPU Reset instead ? */ |
d7d02e3c | 178 | qemu_system_reset_request(); |
a541f297 | 179 | } else { |
d537cf6c PB |
180 | qemu_set_irq(NVRAM->IRQ, 1); |
181 | qemu_set_irq(NVRAM->IRQ, 0); | |
a541f297 FB |
182 | } |
183 | } | |
184 | ||
43a34704 | 185 | static void set_up_watchdog(M48t59State *NVRAM, uint8_t value) |
a541f297 FB |
186 | { |
187 | uint64_t interval; /* in 1/16 seconds */ | |
188 | ||
868d585a | 189 | NVRAM->buffer[0x1FF0] &= ~0x80; |
a541f297 | 190 | if (NVRAM->wd_timer != NULL) { |
bc72ad67 | 191 | timer_del(NVRAM->wd_timer); |
868d585a JM |
192 | if (value != 0) { |
193 | interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F); | |
bc72ad67 | 194 | timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) + |
868d585a JM |
195 | ((interval * 1000) >> 4)); |
196 | } | |
a541f297 FB |
197 | } |
198 | } | |
199 | ||
200 | /* Direct access to NVRAM */ | |
897b4c6c | 201 | void m48t59_write (void *opaque, uint32_t addr, uint32_t val) |
a541f297 | 202 | { |
43a34704 | 203 | M48t59State *NVRAM = opaque; |
a541f297 FB |
204 | struct tm tm; |
205 | int tmp; | |
206 | ||
819385c5 FB |
207 | if (addr > 0x1FF8 && addr < 0x2000) |
208 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); | |
4aed2c33 BS |
209 | |
210 | /* check for NVRAM access */ | |
7bc3018b PB |
211 | if ((NVRAM->model == 2 && addr < 0x7f8) || |
212 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
213 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
819385c5 | 214 | goto do_write; |
7bc3018b | 215 | } |
4aed2c33 BS |
216 | |
217 | /* TOD access */ | |
819385c5 | 218 | switch (addr) { |
a541f297 FB |
219 | case 0x1FF0: |
220 | /* flags register : read-only */ | |
221 | break; | |
222 | case 0x1FF1: | |
223 | /* unused */ | |
224 | break; | |
225 | case 0x1FF2: | |
226 | /* alarm seconds */ | |
abd0c6bd | 227 | tmp = from_bcd(val & 0x7F); |
819385c5 | 228 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 229 | NVRAM->alarm.tm_sec = tmp; |
819385c5 | 230 | NVRAM->buffer[0x1FF2] = val; |
f6503059 | 231 | set_alarm(NVRAM); |
819385c5 | 232 | } |
a541f297 FB |
233 | break; |
234 | case 0x1FF3: | |
235 | /* alarm minutes */ | |
abd0c6bd | 236 | tmp = from_bcd(val & 0x7F); |
819385c5 | 237 | if (tmp >= 0 && tmp <= 59) { |
f6503059 | 238 | NVRAM->alarm.tm_min = tmp; |
819385c5 | 239 | NVRAM->buffer[0x1FF3] = val; |
f6503059 | 240 | set_alarm(NVRAM); |
819385c5 | 241 | } |
a541f297 FB |
242 | break; |
243 | case 0x1FF4: | |
244 | /* alarm hours */ | |
abd0c6bd | 245 | tmp = from_bcd(val & 0x3F); |
819385c5 | 246 | if (tmp >= 0 && tmp <= 23) { |
f6503059 | 247 | NVRAM->alarm.tm_hour = tmp; |
819385c5 | 248 | NVRAM->buffer[0x1FF4] = val; |
f6503059 | 249 | set_alarm(NVRAM); |
819385c5 | 250 | } |
a541f297 FB |
251 | break; |
252 | case 0x1FF5: | |
253 | /* alarm date */ | |
02f5da11 | 254 | tmp = from_bcd(val & 0x3F); |
819385c5 | 255 | if (tmp != 0) { |
f6503059 | 256 | NVRAM->alarm.tm_mday = tmp; |
819385c5 | 257 | NVRAM->buffer[0x1FF5] = val; |
f6503059 | 258 | set_alarm(NVRAM); |
819385c5 | 259 | } |
a541f297 FB |
260 | break; |
261 | case 0x1FF6: | |
262 | /* interrupts */ | |
819385c5 | 263 | NVRAM->buffer[0x1FF6] = val; |
a541f297 FB |
264 | break; |
265 | case 0x1FF7: | |
266 | /* watchdog */ | |
819385c5 FB |
267 | NVRAM->buffer[0x1FF7] = val; |
268 | set_up_watchdog(NVRAM, val); | |
a541f297 FB |
269 | break; |
270 | case 0x1FF8: | |
4aed2c33 | 271 | case 0x07F8: |
a541f297 | 272 | /* control */ |
4aed2c33 | 273 | NVRAM->buffer[addr] = (val & ~0xA0) | 0x90; |
a541f297 FB |
274 | break; |
275 | case 0x1FF9: | |
4aed2c33 | 276 | case 0x07F9: |
a541f297 | 277 | /* seconds (BCD) */ |
abd0c6bd | 278 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
279 | if (tmp >= 0 && tmp <= 59) { |
280 | get_time(NVRAM, &tm); | |
281 | tm.tm_sec = tmp; | |
282 | set_time(NVRAM, &tm); | |
283 | } | |
f6503059 | 284 | if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) { |
a541f297 FB |
285 | if (val & 0x80) { |
286 | NVRAM->stop_time = time(NULL); | |
287 | } else { | |
288 | NVRAM->time_offset += NVRAM->stop_time - time(NULL); | |
289 | NVRAM->stop_time = 0; | |
290 | } | |
291 | } | |
f6503059 | 292 | NVRAM->buffer[addr] = val & 0x80; |
a541f297 FB |
293 | break; |
294 | case 0x1FFA: | |
4aed2c33 | 295 | case 0x07FA: |
a541f297 | 296 | /* minutes (BCD) */ |
abd0c6bd | 297 | tmp = from_bcd(val & 0x7F); |
a541f297 FB |
298 | if (tmp >= 0 && tmp <= 59) { |
299 | get_time(NVRAM, &tm); | |
300 | tm.tm_min = tmp; | |
301 | set_time(NVRAM, &tm); | |
302 | } | |
303 | break; | |
304 | case 0x1FFB: | |
4aed2c33 | 305 | case 0x07FB: |
a541f297 | 306 | /* hours (BCD) */ |
abd0c6bd | 307 | tmp = from_bcd(val & 0x3F); |
a541f297 FB |
308 | if (tmp >= 0 && tmp <= 23) { |
309 | get_time(NVRAM, &tm); | |
310 | tm.tm_hour = tmp; | |
311 | set_time(NVRAM, &tm); | |
312 | } | |
313 | break; | |
314 | case 0x1FFC: | |
4aed2c33 | 315 | case 0x07FC: |
a541f297 | 316 | /* day of the week / century */ |
abd0c6bd | 317 | tmp = from_bcd(val & 0x07); |
a541f297 FB |
318 | get_time(NVRAM, &tm); |
319 | tm.tm_wday = tmp; | |
320 | set_time(NVRAM, &tm); | |
4aed2c33 | 321 | NVRAM->buffer[addr] = val & 0x40; |
a541f297 FB |
322 | break; |
323 | case 0x1FFD: | |
4aed2c33 | 324 | case 0x07FD: |
02f5da11 AT |
325 | /* date (BCD) */ |
326 | tmp = from_bcd(val & 0x3F); | |
a541f297 FB |
327 | if (tmp != 0) { |
328 | get_time(NVRAM, &tm); | |
329 | tm.tm_mday = tmp; | |
330 | set_time(NVRAM, &tm); | |
331 | } | |
332 | break; | |
333 | case 0x1FFE: | |
4aed2c33 | 334 | case 0x07FE: |
a541f297 | 335 | /* month */ |
abd0c6bd | 336 | tmp = from_bcd(val & 0x1F); |
a541f297 FB |
337 | if (tmp >= 1 && tmp <= 12) { |
338 | get_time(NVRAM, &tm); | |
339 | tm.tm_mon = tmp - 1; | |
340 | set_time(NVRAM, &tm); | |
341 | } | |
342 | break; | |
343 | case 0x1FFF: | |
4aed2c33 | 344 | case 0x07FF: |
a541f297 | 345 | /* year */ |
abd0c6bd | 346 | tmp = from_bcd(val); |
a541f297 FB |
347 | if (tmp >= 0 && tmp <= 99) { |
348 | get_time(NVRAM, &tm); | |
7bc3018b | 349 | if (NVRAM->model == 8) { |
abd0c6bd | 350 | tm.tm_year = from_bcd(val) + 68; // Base year is 1968 |
7bc3018b | 351 | } else { |
abd0c6bd | 352 | tm.tm_year = from_bcd(val); |
7bc3018b | 353 | } |
a541f297 FB |
354 | set_time(NVRAM, &tm); |
355 | } | |
356 | break; | |
357 | default: | |
13ab5daa | 358 | /* Check lock registers state */ |
819385c5 | 359 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 360 | break; |
819385c5 | 361 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 362 | break; |
819385c5 FB |
363 | do_write: |
364 | if (addr < NVRAM->size) { | |
365 | NVRAM->buffer[addr] = val & 0xFF; | |
a541f297 FB |
366 | } |
367 | break; | |
368 | } | |
369 | } | |
370 | ||
897b4c6c | 371 | uint32_t m48t59_read (void *opaque, uint32_t addr) |
a541f297 | 372 | { |
43a34704 | 373 | M48t59State *NVRAM = opaque; |
a541f297 FB |
374 | struct tm tm; |
375 | uint32_t retval = 0xFF; | |
376 | ||
4aed2c33 | 377 | /* check for NVRAM access */ |
7bc3018b PB |
378 | if ((NVRAM->model == 2 && addr < 0x078f) || |
379 | (NVRAM->model == 8 && addr < 0x1ff8) || | |
380 | (NVRAM->model == 59 && addr < 0x1ff0)) { | |
819385c5 | 381 | goto do_read; |
7bc3018b | 382 | } |
4aed2c33 BS |
383 | |
384 | /* TOD access */ | |
819385c5 | 385 | switch (addr) { |
a541f297 FB |
386 | case 0x1FF0: |
387 | /* flags register */ | |
388 | goto do_read; | |
389 | case 0x1FF1: | |
390 | /* unused */ | |
391 | retval = 0; | |
392 | break; | |
393 | case 0x1FF2: | |
394 | /* alarm seconds */ | |
395 | goto do_read; | |
396 | case 0x1FF3: | |
397 | /* alarm minutes */ | |
398 | goto do_read; | |
399 | case 0x1FF4: | |
400 | /* alarm hours */ | |
401 | goto do_read; | |
402 | case 0x1FF5: | |
403 | /* alarm date */ | |
404 | goto do_read; | |
405 | case 0x1FF6: | |
406 | /* interrupts */ | |
407 | goto do_read; | |
408 | case 0x1FF7: | |
409 | /* A read resets the watchdog */ | |
410 | set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]); | |
411 | goto do_read; | |
412 | case 0x1FF8: | |
4aed2c33 | 413 | case 0x07F8: |
a541f297 FB |
414 | /* control */ |
415 | goto do_read; | |
416 | case 0x1FF9: | |
4aed2c33 | 417 | case 0x07F9: |
a541f297 FB |
418 | /* seconds (BCD) */ |
419 | get_time(NVRAM, &tm); | |
abd0c6bd | 420 | retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec); |
a541f297 FB |
421 | break; |
422 | case 0x1FFA: | |
4aed2c33 | 423 | case 0x07FA: |
a541f297 FB |
424 | /* minutes (BCD) */ |
425 | get_time(NVRAM, &tm); | |
abd0c6bd | 426 | retval = to_bcd(tm.tm_min); |
a541f297 FB |
427 | break; |
428 | case 0x1FFB: | |
4aed2c33 | 429 | case 0x07FB: |
a541f297 FB |
430 | /* hours (BCD) */ |
431 | get_time(NVRAM, &tm); | |
abd0c6bd | 432 | retval = to_bcd(tm.tm_hour); |
a541f297 FB |
433 | break; |
434 | case 0x1FFC: | |
4aed2c33 | 435 | case 0x07FC: |
a541f297 FB |
436 | /* day of the week / century */ |
437 | get_time(NVRAM, &tm); | |
4aed2c33 | 438 | retval = NVRAM->buffer[addr] | tm.tm_wday; |
a541f297 FB |
439 | break; |
440 | case 0x1FFD: | |
4aed2c33 | 441 | case 0x07FD: |
a541f297 FB |
442 | /* date */ |
443 | get_time(NVRAM, &tm); | |
abd0c6bd | 444 | retval = to_bcd(tm.tm_mday); |
a541f297 FB |
445 | break; |
446 | case 0x1FFE: | |
4aed2c33 | 447 | case 0x07FE: |
a541f297 FB |
448 | /* month */ |
449 | get_time(NVRAM, &tm); | |
abd0c6bd | 450 | retval = to_bcd(tm.tm_mon + 1); |
a541f297 FB |
451 | break; |
452 | case 0x1FFF: | |
4aed2c33 | 453 | case 0x07FF: |
a541f297 FB |
454 | /* year */ |
455 | get_time(NVRAM, &tm); | |
7bc3018b | 456 | if (NVRAM->model == 8) { |
abd0c6bd | 457 | retval = to_bcd(tm.tm_year - 68); // Base year is 1968 |
7bc3018b | 458 | } else { |
abd0c6bd | 459 | retval = to_bcd(tm.tm_year); |
7bc3018b | 460 | } |
a541f297 FB |
461 | break; |
462 | default: | |
13ab5daa | 463 | /* Check lock registers state */ |
819385c5 | 464 | if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1)) |
13ab5daa | 465 | break; |
819385c5 | 466 | if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2)) |
13ab5daa | 467 | break; |
819385c5 FB |
468 | do_read: |
469 | if (addr < NVRAM->size) { | |
470 | retval = NVRAM->buffer[addr]; | |
a541f297 FB |
471 | } |
472 | break; | |
473 | } | |
819385c5 | 474 | if (addr > 0x1FF9 && addr < 0x2000) |
9ed1e667 | 475 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 FB |
476 | |
477 | return retval; | |
478 | } | |
479 | ||
897b4c6c | 480 | void m48t59_toggle_lock (void *opaque, int lock) |
13ab5daa | 481 | { |
43a34704 | 482 | M48t59State *NVRAM = opaque; |
897b4c6c | 483 | |
13ab5daa FB |
484 | NVRAM->lock ^= 1 << lock; |
485 | } | |
486 | ||
a541f297 | 487 | /* IO access to NVRAM */ |
087bd055 AG |
488 | static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val, |
489 | unsigned size) | |
a541f297 | 490 | { |
43a34704 | 491 | M48t59State *NVRAM = opaque; |
a541f297 | 492 | |
9ed1e667 | 493 | NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); |
a541f297 FB |
494 | switch (addr) { |
495 | case 0: | |
496 | NVRAM->addr &= ~0x00FF; | |
497 | NVRAM->addr |= val; | |
498 | break; | |
499 | case 1: | |
500 | NVRAM->addr &= ~0xFF00; | |
501 | NVRAM->addr |= val << 8; | |
502 | break; | |
503 | case 3: | |
b1f88301 | 504 | m48t59_write(NVRAM, NVRAM->addr, val); |
a541f297 FB |
505 | NVRAM->addr = 0x0000; |
506 | break; | |
507 | default: | |
508 | break; | |
509 | } | |
510 | } | |
511 | ||
087bd055 | 512 | static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size) |
a541f297 | 513 | { |
43a34704 | 514 | M48t59State *NVRAM = opaque; |
13ab5daa | 515 | uint32_t retval; |
a541f297 | 516 | |
13ab5daa FB |
517 | switch (addr) { |
518 | case 3: | |
819385c5 | 519 | retval = m48t59_read(NVRAM, NVRAM->addr); |
13ab5daa FB |
520 | break; |
521 | default: | |
522 | retval = -1; | |
523 | break; | |
524 | } | |
9ed1e667 | 525 | NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval); |
a541f297 | 526 | |
13ab5daa | 527 | return retval; |
a541f297 FB |
528 | } |
529 | ||
a8170e5e | 530 | static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value) |
e1bb04f7 | 531 | { |
43a34704 | 532 | M48t59State *NVRAM = opaque; |
3b46e624 | 533 | |
819385c5 | 534 | m48t59_write(NVRAM, addr, value & 0xff); |
e1bb04f7 FB |
535 | } |
536 | ||
a8170e5e | 537 | static void nvram_writew (void *opaque, hwaddr addr, uint32_t value) |
e1bb04f7 | 538 | { |
43a34704 | 539 | M48t59State *NVRAM = opaque; |
3b46e624 | 540 | |
819385c5 FB |
541 | m48t59_write(NVRAM, addr, (value >> 8) & 0xff); |
542 | m48t59_write(NVRAM, addr + 1, value & 0xff); | |
e1bb04f7 FB |
543 | } |
544 | ||
a8170e5e | 545 | static void nvram_writel (void *opaque, hwaddr addr, uint32_t value) |
e1bb04f7 | 546 | { |
43a34704 | 547 | M48t59State *NVRAM = opaque; |
3b46e624 | 548 | |
819385c5 FB |
549 | m48t59_write(NVRAM, addr, (value >> 24) & 0xff); |
550 | m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); | |
551 | m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff); | |
552 | m48t59_write(NVRAM, addr + 3, value & 0xff); | |
e1bb04f7 FB |
553 | } |
554 | ||
a8170e5e | 555 | static uint32_t nvram_readb (void *opaque, hwaddr addr) |
e1bb04f7 | 556 | { |
43a34704 | 557 | M48t59State *NVRAM = opaque; |
819385c5 | 558 | uint32_t retval; |
3b46e624 | 559 | |
819385c5 | 560 | retval = m48t59_read(NVRAM, addr); |
e1bb04f7 FB |
561 | return retval; |
562 | } | |
563 | ||
a8170e5e | 564 | static uint32_t nvram_readw (void *opaque, hwaddr addr) |
e1bb04f7 | 565 | { |
43a34704 | 566 | M48t59State *NVRAM = opaque; |
819385c5 | 567 | uint32_t retval; |
3b46e624 | 568 | |
819385c5 FB |
569 | retval = m48t59_read(NVRAM, addr) << 8; |
570 | retval |= m48t59_read(NVRAM, addr + 1); | |
e1bb04f7 FB |
571 | return retval; |
572 | } | |
573 | ||
a8170e5e | 574 | static uint32_t nvram_readl (void *opaque, hwaddr addr) |
e1bb04f7 | 575 | { |
43a34704 | 576 | M48t59State *NVRAM = opaque; |
819385c5 | 577 | uint32_t retval; |
e1bb04f7 | 578 | |
819385c5 FB |
579 | retval = m48t59_read(NVRAM, addr) << 24; |
580 | retval |= m48t59_read(NVRAM, addr + 1) << 16; | |
581 | retval |= m48t59_read(NVRAM, addr + 2) << 8; | |
582 | retval |= m48t59_read(NVRAM, addr + 3); | |
e1bb04f7 FB |
583 | return retval; |
584 | } | |
585 | ||
5a31cd68 AK |
586 | static const MemoryRegionOps nvram_ops = { |
587 | .old_mmio = { | |
588 | .read = { nvram_readb, nvram_readw, nvram_readl, }, | |
589 | .write = { nvram_writeb, nvram_writew, nvram_writel, }, | |
590 | }, | |
591 | .endianness = DEVICE_NATIVE_ENDIAN, | |
e1bb04f7 | 592 | }; |
819385c5 | 593 | |
fd484ae4 JQ |
594 | static const VMStateDescription vmstate_m48t59 = { |
595 | .name = "m48t59", | |
596 | .version_id = 1, | |
597 | .minimum_version_id = 1, | |
598 | .minimum_version_id_old = 1, | |
599 | .fields = (VMStateField[]) { | |
600 | VMSTATE_UINT8(lock, M48t59State), | |
601 | VMSTATE_UINT16(addr, M48t59State), | |
602 | VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size), | |
603 | VMSTATE_END_OF_LIST() | |
604 | } | |
605 | }; | |
3ccacc4a | 606 | |
43a34704 | 607 | static void m48t59_reset_common(M48t59State *NVRAM) |
3ccacc4a | 608 | { |
6e6b7363 BS |
609 | NVRAM->addr = 0; |
610 | NVRAM->lock = 0; | |
3ccacc4a | 611 | if (NVRAM->alrm_timer != NULL) |
bc72ad67 | 612 | timer_del(NVRAM->alrm_timer); |
3ccacc4a BS |
613 | |
614 | if (NVRAM->wd_timer != NULL) | |
bc72ad67 | 615 | timer_del(NVRAM->wd_timer); |
3ccacc4a BS |
616 | } |
617 | ||
285e468d BS |
618 | static void m48t59_reset_isa(DeviceState *d) |
619 | { | |
a2772c70 | 620 | M48t59ISAState *isa = ISA_M48T59(d); |
43a34704 | 621 | M48t59State *NVRAM = &isa->state; |
285e468d BS |
622 | |
623 | m48t59_reset_common(NVRAM); | |
624 | } | |
625 | ||
626 | static void m48t59_reset_sysbus(DeviceState *d) | |
627 | { | |
29d1ffc3 | 628 | M48t59SysBusState *sys = SYSBUS_M48T59(d); |
43a34704 | 629 | M48t59State *NVRAM = &sys->state; |
285e468d BS |
630 | |
631 | m48t59_reset_common(NVRAM); | |
632 | } | |
633 | ||
9936d6e4 | 634 | static const MemoryRegionOps m48t59_io_ops = { |
087bd055 AG |
635 | .read = NVRAM_readb, |
636 | .write = NVRAM_writeb, | |
637 | .impl = { | |
638 | .min_access_size = 1, | |
639 | .max_access_size = 1, | |
640 | }, | |
641 | .endianness = DEVICE_LITTLE_ENDIAN, | |
9936d6e4 RH |
642 | }; |
643 | ||
a541f297 | 644 | /* Initialisation routine */ |
a8170e5e | 645 | M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base, |
7bc3018b | 646 | uint32_t io_base, uint16_t size, int model) |
a541f297 | 647 | { |
d27cf0ae BS |
648 | DeviceState *dev; |
649 | SysBusDevice *s; | |
f80237d4 | 650 | M48t59SysBusState *d; |
51f9b84e | 651 | M48t59State *state; |
d27cf0ae | 652 | |
29d1ffc3 | 653 | dev = qdev_create(NULL, TYPE_SYSBUS_M48T59); |
7bc3018b | 654 | qdev_prop_set_uint32(dev, "model", model); |
ee6847d1 GH |
655 | qdev_prop_set_uint32(dev, "size", size); |
656 | qdev_prop_set_uint32(dev, "io_base", io_base); | |
e23a1b33 | 657 | qdev_init_nofail(dev); |
1356b98d | 658 | s = SYS_BUS_DEVICE(dev); |
29d1ffc3 | 659 | d = SYSBUS_M48T59(dev); |
51f9b84e | 660 | state = &d->state; |
d27cf0ae | 661 | sysbus_connect_irq(s, 0, IRQ); |
853dca12 PB |
662 | memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, state, |
663 | "m48t59", 4); | |
819385c5 | 664 | if (io_base != 0) { |
087bd055 | 665 | memory_region_add_subregion(get_system_io(), io_base, &d->io); |
819385c5 | 666 | } |
e1bb04f7 | 667 | if (mem_base != 0) { |
d27cf0ae | 668 | sysbus_mmio_map(s, 0, mem_base); |
e1bb04f7 | 669 | } |
d27cf0ae | 670 | |
51f9b84e | 671 | return state; |
d27cf0ae BS |
672 | } |
673 | ||
48a18b3c | 674 | M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size, |
7bc3018b | 675 | int model) |
d27cf0ae | 676 | { |
f80237d4 | 677 | M48t59ISAState *d; |
a2772c70 AF |
678 | ISADevice *isadev; |
679 | DeviceState *dev; | |
43a34704 | 680 | M48t59State *s; |
f80237d4 | 681 | |
a2772c70 AF |
682 | isadev = isa_create(bus, TYPE_ISA_M48T59); |
683 | dev = DEVICE(isadev); | |
684 | qdev_prop_set_uint32(dev, "model", model); | |
685 | qdev_prop_set_uint32(dev, "size", size); | |
686 | qdev_prop_set_uint32(dev, "io_base", io_base); | |
687 | qdev_init_nofail(dev); | |
688 | d = ISA_M48T59(isadev); | |
f80237d4 | 689 | s = &d->state; |
d27cf0ae | 690 | |
853dca12 | 691 | memory_region_init_io(&d->io, OBJECT(d), &m48t59_io_ops, s, "m48t59", 4); |
f80237d4 | 692 | if (io_base != 0) { |
a2772c70 | 693 | isa_register_ioport(isadev, &d->io, io_base); |
f80237d4 | 694 | } |
d27cf0ae | 695 | |
f80237d4 BS |
696 | return s; |
697 | } | |
d27cf0ae | 698 | |
db895a1e | 699 | static void m48t59_realize_common(M48t59State *s, Error **errp) |
f80237d4 | 700 | { |
7267c094 | 701 | s->buffer = g_malloc0(s->size); |
7bc3018b | 702 | if (s->model == 59) { |
884f17c2 | 703 | s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s); |
bc72ad67 | 704 | s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s); |
819385c5 | 705 | } |
f6503059 | 706 | qemu_get_timedate(&s->alarm, 0); |
13ab5daa | 707 | |
fd484ae4 | 708 | vmstate_register(NULL, -1, &vmstate_m48t59, s); |
f80237d4 BS |
709 | } |
710 | ||
db895a1e | 711 | static void m48t59_isa_realize(DeviceState *dev, Error **errp) |
f80237d4 | 712 | { |
db895a1e | 713 | ISADevice *isadev = ISA_DEVICE(dev); |
a2772c70 | 714 | M48t59ISAState *d = ISA_M48T59(dev); |
43a34704 | 715 | M48t59State *s = &d->state; |
f80237d4 | 716 | |
db895a1e AF |
717 | isa_init_irq(isadev, &s->IRQ, 8); |
718 | m48t59_realize_common(s, errp); | |
d27cf0ae | 719 | } |
3ccacc4a | 720 | |
f80237d4 BS |
721 | static int m48t59_init1(SysBusDevice *dev) |
722 | { | |
29d1ffc3 | 723 | M48t59SysBusState *d = SYSBUS_M48T59(dev); |
43a34704 | 724 | M48t59State *s = &d->state; |
db895a1e | 725 | Error *err = NULL; |
f80237d4 BS |
726 | |
727 | sysbus_init_irq(dev, &s->IRQ); | |
728 | ||
853dca12 PB |
729 | memory_region_init_io(&s->iomem, OBJECT(d), &nvram_ops, s, |
730 | "m48t59.nvram", s->size); | |
750ecd44 | 731 | sysbus_init_mmio(dev, &s->iomem); |
db895a1e AF |
732 | m48t59_realize_common(s, &err); |
733 | if (err != NULL) { | |
734 | error_free(err); | |
735 | return -1; | |
736 | } | |
f80237d4 BS |
737 | |
738 | return 0; | |
739 | } | |
740 | ||
39bffca2 AL |
741 | static Property m48t59_isa_properties[] = { |
742 | DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1), | |
7bc3018b | 743 | DEFINE_PROP_UINT32("model", M48t59ISAState, state.model, -1), |
39bffca2 AL |
744 | DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0), |
745 | DEFINE_PROP_END_OF_LIST(), | |
746 | }; | |
747 | ||
a2772c70 | 748 | static void m48t59_isa_class_init(ObjectClass *klass, void *data) |
8f04ee08 | 749 | { |
39bffca2 | 750 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
751 | |
752 | dc->realize = m48t59_isa_realize; | |
39bffca2 AL |
753 | dc->no_user = 1; |
754 | dc->reset = m48t59_reset_isa; | |
755 | dc->props = m48t59_isa_properties; | |
8f04ee08 AL |
756 | } |
757 | ||
8c43a6f0 | 758 | static const TypeInfo m48t59_isa_info = { |
a2772c70 | 759 | .name = TYPE_ISA_M48T59, |
39bffca2 AL |
760 | .parent = TYPE_ISA_DEVICE, |
761 | .instance_size = sizeof(M48t59ISAState), | |
a2772c70 | 762 | .class_init = m48t59_isa_class_init, |
f80237d4 BS |
763 | }; |
764 | ||
999e12bb AL |
765 | static Property m48t59_properties[] = { |
766 | DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1), | |
7bc3018b | 767 | DEFINE_PROP_UINT32("model", M48t59SysBusState, state.model, -1), |
999e12bb AL |
768 | DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0), |
769 | DEFINE_PROP_END_OF_LIST(), | |
770 | }; | |
771 | ||
772 | static void m48t59_class_init(ObjectClass *klass, void *data) | |
773 | { | |
39bffca2 | 774 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb AL |
775 | SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
776 | ||
777 | k->init = m48t59_init1; | |
39bffca2 AL |
778 | dc->reset = m48t59_reset_sysbus; |
779 | dc->props = m48t59_properties; | |
999e12bb AL |
780 | } |
781 | ||
8c43a6f0 | 782 | static const TypeInfo m48t59_info = { |
29d1ffc3 | 783 | .name = TYPE_SYSBUS_M48T59, |
39bffca2 AL |
784 | .parent = TYPE_SYS_BUS_DEVICE, |
785 | .instance_size = sizeof(M48t59SysBusState), | |
786 | .class_init = m48t59_class_init, | |
ee6847d1 GH |
787 | }; |
788 | ||
83f7d43a | 789 | static void m48t59_register_types(void) |
d27cf0ae | 790 | { |
39bffca2 AL |
791 | type_register_static(&m48t59_info); |
792 | type_register_static(&m48t59_isa_info); | |
a541f297 | 793 | } |
d27cf0ae | 794 | |
83f7d43a | 795 | type_init(m48t59_register_types) |