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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
b6a0aa05 | 24 | #include "qemu/osdep.h" |
f348b6d1 VB |
25 | #include "qemu/cutils.h" |
26 | #include "qemu/bcd.h" | |
83c9f4ca | 27 | #include "hw/hw.h" |
1de7afc9 | 28 | #include "qemu/timer.h" |
9c17d615 | 29 | #include "sysemu/sysemu.h" |
1dfb1b2d | 30 | #include "sysemu/replay.h" |
0d09e41a | 31 | #include "hw/timer/mc146818rtc.h" |
7b1b5d19 | 32 | #include "qapi/visitor.h" |
e010ad8f | 33 | #include "qapi-event.h" |
f2ae8abf | 34 | #include "qmp-commands.h" |
80cabfad | 35 | |
d362e757 | 36 | #ifdef TARGET_I386 |
0d09e41a | 37 | #include "hw/i386/apic.h" |
d362e757 JK |
38 | #endif |
39 | ||
80cabfad | 40 | //#define DEBUG_CMOS |
aa6f63ff | 41 | //#define DEBUG_COALESCED |
80cabfad | 42 | |
ec51e364 IY |
43 | #ifdef DEBUG_CMOS |
44 | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
45 | #else | |
46 | # define CMOS_DPRINTF(format, ...) do { } while (0) | |
47 | #endif | |
48 | ||
aa6f63ff BS |
49 | #ifdef DEBUG_COALESCED |
50 | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) | |
51 | #else | |
52 | # define DPRINTF_C(format, ...) do { } while (0) | |
53 | #endif | |
54 | ||
00cf5774 PB |
55 | #define SEC_PER_MIN 60 |
56 | #define MIN_PER_HOUR 60 | |
57 | #define SEC_PER_HOUR 3600 | |
58 | #define HOUR_PER_DAY 24 | |
59 | #define SEC_PER_DAY 86400 | |
56038ef6 | 60 | |
dd17765b | 61 | #define RTC_REINJECT_ON_ACK_COUNT 20 |
e46deaba | 62 | #define RTC_CLOCK_RATE 32768 |
13566fe3 | 63 | #define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768) |
ba32edab | 64 | |
0e41271e AF |
65 | #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC) |
66 | ||
1d914fa0 | 67 | typedef struct RTCState { |
0e41271e AF |
68 | ISADevice parent_obj; |
69 | ||
b2c5009b | 70 | MemoryRegion io; |
dff38e7b FB |
71 | uint8_t cmos_data[128]; |
72 | uint8_t cmos_index; | |
32e0c826 | 73 | int32_t base_year; |
56038ef6 YZ |
74 | uint64_t base_rtc; |
75 | uint64_t last_update; | |
76 | int64_t offset; | |
d537cf6c | 77 | qemu_irq irq; |
18c6e2ff | 78 | int it_shift; |
dff38e7b FB |
79 | /* periodic timer */ |
80 | QEMUTimer *periodic_timer; | |
81 | int64_t next_periodic_time; | |
56038ef6 YZ |
82 | /* update-ended timer */ |
83 | QEMUTimer *update_timer; | |
00cf5774 | 84 | uint64_t next_alarm_time; |
ba32edab | 85 | uint16_t irq_reinject_on_ack_count; |
73822ec8 AL |
86 | uint32_t irq_coalesced; |
87 | uint32_t period; | |
93b66569 | 88 | QEMUTimer *coalesced_timer; |
17604dac | 89 | Notifier clock_reset_notifier; |
433acf0d | 90 | LostTickPolicy lost_tick_policy; |
da98c8eb | 91 | Notifier suspend_notifier; |
f2ae8abf | 92 | QLIST_ENTRY(RTCState) link; |
1d914fa0 | 93 | } RTCState; |
dff38e7b FB |
94 | |
95 | static void rtc_set_time(RTCState *s); | |
56038ef6 | 96 | static void rtc_update_time(RTCState *s); |
e2826cf4 | 97 | static void rtc_set_cmos(RTCState *s, const struct tm *tm); |
56038ef6 | 98 | static inline int rtc_from_bcd(RTCState *s, int a); |
00cf5774 | 99 | static uint64_t get_next_alarm(RTCState *s); |
56038ef6 | 100 | |
41a9b8b2 YZ |
101 | static inline bool rtc_running(RTCState *s) |
102 | { | |
103 | return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && | |
104 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); | |
105 | } | |
106 | ||
56038ef6 YZ |
107 | static uint64_t get_guest_rtc_ns(RTCState *s) |
108 | { | |
884f17c2 | 109 | uint64_t guest_clock = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 110 | |
9be38598 | 111 | return s->base_rtc * NANOSECONDS_PER_SECOND + |
73bcb24d | 112 | guest_clock - s->last_update + s->offset; |
56038ef6 | 113 | } |
dff38e7b | 114 | |
93b66569 AL |
115 | static void rtc_coalesced_timer_update(RTCState *s) |
116 | { | |
117 | if (s->irq_coalesced == 0) { | |
bc72ad67 | 118 | timer_del(s->coalesced_timer); |
93b66569 AL |
119 | } else { |
120 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
121 | int c = MIN(s->irq_coalesced, 7) + 1; | |
884f17c2 | 122 | int64_t next_clock = qemu_clock_get_ns(rtc_clock) + |
bd618eab | 123 | periodic_clock_to_ns(s->period / c); |
bc72ad67 | 124 | timer_mod(s->coalesced_timer, next_clock); |
93b66569 AL |
125 | } |
126 | } | |
127 | ||
e0c8b950 XG |
128 | static QLIST_HEAD(, RTCState) rtc_devices = |
129 | QLIST_HEAD_INITIALIZER(rtc_devices); | |
130 | ||
388ad5d2 | 131 | #ifdef TARGET_I386 |
e0c8b950 XG |
132 | void qmp_rtc_reset_reinjection(Error **errp) |
133 | { | |
134 | RTCState *s; | |
135 | ||
136 | QLIST_FOREACH(s, &rtc_devices, link) { | |
137 | s->irq_coalesced = 0; | |
138 | } | |
139 | } | |
140 | ||
141 | static bool rtc_policy_slew_deliver_irq(RTCState *s) | |
142 | { | |
143 | apic_reset_irq_delivered(); | |
144 | qemu_irq_raise(s->irq); | |
145 | return apic_get_irq_delivered(); | |
146 | } | |
147 | ||
93b66569 AL |
148 | static void rtc_coalesced_timer(void *opaque) |
149 | { | |
150 | RTCState *s = opaque; | |
151 | ||
152 | if (s->irq_coalesced != 0) { | |
93b66569 | 153 | s->cmos_data[RTC_REG_C] |= 0xc0; |
aa6f63ff | 154 | DPRINTF_C("cmos: injecting from timer\n"); |
e0c8b950 | 155 | if (rtc_policy_slew_deliver_irq(s)) { |
93b66569 | 156 | s->irq_coalesced--; |
aa6f63ff BS |
157 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
158 | s->irq_coalesced); | |
93b66569 AL |
159 | } |
160 | } | |
161 | ||
162 | rtc_coalesced_timer_update(s); | |
163 | } | |
e0c8b950 XG |
164 | #else |
165 | static bool rtc_policy_slew_deliver_irq(RTCState *s) | |
166 | { | |
167 | assert(0); | |
168 | return false; | |
169 | } | |
93b66569 AL |
170 | #endif |
171 | ||
369b4135 | 172 | static uint32_t rtc_periodic_clock_ticks(RTCState *s) |
dff38e7b | 173 | { |
369b4135 TY |
174 | int period_code; |
175 | ||
176 | if (!(s->cmos_data[RTC_REG_B] & REG_B_PIE)) { | |
177 | return 0; | |
178 | } | |
dff38e7b FB |
179 | |
180 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
369b4135 | 181 | |
bd618eab | 182 | return periodic_period_to_clock(period_code); |
369b4135 TY |
183 | } |
184 | ||
185 | /* | |
186 | * handle periodic timer. @old_period indicates the periodic timer update | |
187 | * is just due to period adjustment. | |
188 | */ | |
189 | static void | |
190 | periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period) | |
191 | { | |
192 | uint32_t period; | |
193 | int64_t cur_clock, next_irq_clock, lost_clock = 0; | |
194 | ||
195 | period = rtc_periodic_clock_ticks(s); | |
196 | ||
197 | if (period) { | |
dff38e7b | 198 | /* compute 32 khz clock */ |
73bcb24d RS |
199 | cur_clock = |
200 | muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); | |
201 | ||
369b4135 TY |
202 | /* |
203 | * if the periodic timer's update is due to period re-configuration, | |
204 | * we should count the clock since last interrupt. | |
205 | */ | |
206 | if (old_period) { | |
207 | int64_t last_periodic_clock, next_periodic_clock; | |
208 | ||
209 | next_periodic_clock = muldiv64(s->next_periodic_time, | |
210 | RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); | |
211 | last_periodic_clock = next_periodic_clock - old_period; | |
212 | lost_clock = cur_clock - last_periodic_clock; | |
213 | assert(lost_clock >= 0); | |
214 | } | |
215 | ||
369b4135 TY |
216 | /* |
217 | * s->irq_coalesced can change for two reasons: | |
218 | * | |
219 | * a) if one or more periodic timer interrupts have been lost, | |
220 | * lost_clock will be more that a period. | |
221 | * | |
222 | * b) when the period may be reconfigured, we expect the OS to | |
223 | * treat delayed tick as the new period. So, when switching | |
224 | * from a shorter to a longer period, scale down the missing, | |
225 | * because the OS will treat past delayed ticks as longer | |
226 | * (leftovers are put back into lost_clock). When switching | |
227 | * to a shorter period, scale up the missing ticks since the | |
228 | * OS handler will treat past delayed ticks as shorter. | |
229 | */ | |
230 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { | |
231 | uint32_t old_irq_coalesced = s->irq_coalesced; | |
232 | ||
233 | s->period = period; | |
234 | lost_clock += old_irq_coalesced * old_period; | |
235 | s->irq_coalesced = lost_clock / s->period; | |
236 | lost_clock %= s->period; | |
237 | if (old_irq_coalesced != s->irq_coalesced || | |
238 | old_period != s->period) { | |
239 | DPRINTF_C("cmos: coalesced irqs scaled from %d to %d, " | |
240 | "period scaled from %d to %d\n", old_irq_coalesced, | |
241 | s->irq_coalesced, old_period, s->period); | |
242 | rtc_coalesced_timer_update(s); | |
243 | } | |
388ad5d2 | 244 | } else { |
369b4135 TY |
245 | /* |
246 | * no way to compensate the interrupt if LOST_TICK_POLICY_SLEW | |
247 | * is not used, we should make the time progress anyway. | |
248 | */ | |
249 | lost_clock = MIN(lost_clock, period); | |
250 | } | |
251 | ||
252 | assert(lost_clock >= 0 && lost_clock <= period); | |
253 | ||
254 | next_irq_clock = cur_clock + period - lost_clock; | |
bd618eab | 255 | s->next_periodic_time = periodic_clock_to_ns(next_irq_clock) + 1; |
bc72ad67 | 256 | timer_mod(s->periodic_timer, s->next_periodic_time); |
dff38e7b | 257 | } else { |
73822ec8 | 258 | s->irq_coalesced = 0; |
bc72ad67 | 259 | timer_del(s->periodic_timer); |
dff38e7b FB |
260 | } |
261 | } | |
262 | ||
263 | static void rtc_periodic_timer(void *opaque) | |
264 | { | |
265 | RTCState *s = opaque; | |
266 | ||
369b4135 | 267 | periodic_timer_update(s, s->next_periodic_time, 0); |
663447d4 | 268 | s->cmos_data[RTC_REG_C] |= REG_C_PF; |
100d9891 | 269 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
663447d4 | 270 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
104059da | 271 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
ba32edab | 272 | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT) |
e0c8b950 XG |
273 | s->irq_reinject_on_ack_count = 0; |
274 | if (!rtc_policy_slew_deliver_irq(s)) { | |
93b66569 AL |
275 | s->irq_coalesced++; |
276 | rtc_coalesced_timer_update(s); | |
aa6f63ff BS |
277 | DPRINTF_C("cmos: coalesced irqs increased to %d\n", |
278 | s->irq_coalesced); | |
93b66569 AL |
279 | } |
280 | } else | |
e0c8b950 | 281 | qemu_irq_raise(s->irq); |
100d9891 | 282 | } |
dff38e7b | 283 | } |
80cabfad | 284 | |
56038ef6 YZ |
285 | /* handle update-ended timer */ |
286 | static void check_update_timer(RTCState *s) | |
287 | { | |
288 | uint64_t next_update_time; | |
289 | uint64_t guest_nsec; | |
00cf5774 | 290 | int next_alarm_sec; |
56038ef6 | 291 | |
41a9b8b2 YZ |
292 | /* From the data sheet: "Holding the dividers in reset prevents |
293 | * interrupts from operating, while setting the SET bit allows" | |
294 | * them to occur. However, it will prevent an alarm interrupt | |
295 | * from occurring, because the time of day is not updated. | |
56038ef6 | 296 | */ |
41a9b8b2 | 297 | if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { |
bc72ad67 | 298 | timer_del(s->update_timer); |
41a9b8b2 YZ |
299 | return; |
300 | } | |
56038ef6 YZ |
301 | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && |
302 | (s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
bc72ad67 | 303 | timer_del(s->update_timer); |
56038ef6 YZ |
304 | return; |
305 | } | |
306 | if ((s->cmos_data[RTC_REG_C] & REG_C_UF) && | |
307 | (s->cmos_data[RTC_REG_C] & REG_C_AF)) { | |
bc72ad67 | 308 | timer_del(s->update_timer); |
56038ef6 YZ |
309 | return; |
310 | } | |
311 | ||
13566fe3 | 312 | guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
00cf5774 | 313 | /* if UF is clear, reprogram to next second */ |
884f17c2 | 314 | next_update_time = qemu_clock_get_ns(rtc_clock) |
13566fe3 | 315 | + NANOSECONDS_PER_SECOND - guest_nsec; |
00cf5774 PB |
316 | |
317 | /* Compute time of next alarm. One second is already accounted | |
318 | * for in next_update_time. | |
319 | */ | |
320 | next_alarm_sec = get_next_alarm(s); | |
13566fe3 SH |
321 | s->next_alarm_time = next_update_time + |
322 | (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND; | |
00cf5774 PB |
323 | |
324 | if (s->cmos_data[RTC_REG_C] & REG_C_UF) { | |
325 | /* UF is set, but AF is clear. Program the timer to target | |
326 | * the alarm time. */ | |
327 | next_update_time = s->next_alarm_time; | |
328 | } | |
e93379b0 | 329 | if (next_update_time != timer_expire_time_ns(s->update_timer)) { |
bc72ad67 | 330 | timer_mod(s->update_timer, next_update_time); |
56038ef6 YZ |
331 | } |
332 | } | |
333 | ||
334 | static inline uint8_t convert_hour(RTCState *s, uint8_t hour) | |
335 | { | |
336 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { | |
337 | hour %= 12; | |
338 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
339 | hour += 12; | |
340 | } | |
341 | } | |
342 | return hour; | |
343 | } | |
344 | ||
00cf5774 | 345 | static uint64_t get_next_alarm(RTCState *s) |
56038ef6 | 346 | { |
00cf5774 PB |
347 | int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; |
348 | int32_t hour, min, sec; | |
349 | ||
350 | rtc_update_time(s); | |
56038ef6 YZ |
351 | |
352 | alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]); | |
353 | alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]); | |
354 | alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]); | |
00cf5774 | 355 | alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour); |
56038ef6 YZ |
356 | |
357 | cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); | |
358 | cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
359 | cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]); | |
360 | cur_hour = convert_hour(s, cur_hour); | |
361 | ||
00cf5774 PB |
362 | if (alarm_hour == -1) { |
363 | alarm_hour = cur_hour; | |
364 | if (alarm_min == -1) { | |
365 | alarm_min = cur_min; | |
366 | if (alarm_sec == -1) { | |
367 | alarm_sec = cur_sec + 1; | |
368 | } else if (cur_sec > alarm_sec) { | |
369 | alarm_min++; | |
370 | } | |
371 | } else if (cur_min == alarm_min) { | |
372 | if (alarm_sec == -1) { | |
373 | alarm_sec = cur_sec + 1; | |
374 | } else { | |
375 | if (cur_sec > alarm_sec) { | |
376 | alarm_hour++; | |
377 | } | |
378 | } | |
379 | if (alarm_sec == SEC_PER_MIN) { | |
380 | /* wrap to next hour, minutes is not in don't care mode */ | |
381 | alarm_sec = 0; | |
382 | alarm_hour++; | |
383 | } | |
384 | } else if (cur_min > alarm_min) { | |
385 | alarm_hour++; | |
386 | } | |
387 | } else if (cur_hour == alarm_hour) { | |
388 | if (alarm_min == -1) { | |
389 | alarm_min = cur_min; | |
390 | if (alarm_sec == -1) { | |
391 | alarm_sec = cur_sec + 1; | |
392 | } else if (cur_sec > alarm_sec) { | |
393 | alarm_min++; | |
394 | } | |
395 | ||
396 | if (alarm_sec == SEC_PER_MIN) { | |
397 | alarm_sec = 0; | |
398 | alarm_min++; | |
399 | } | |
400 | /* wrap to next day, hour is not in don't care mode */ | |
401 | alarm_min %= MIN_PER_HOUR; | |
402 | } else if (cur_min == alarm_min) { | |
403 | if (alarm_sec == -1) { | |
404 | alarm_sec = cur_sec + 1; | |
405 | } | |
406 | /* wrap to next day, hours+minutes not in don't care mode */ | |
407 | alarm_sec %= SEC_PER_MIN; | |
408 | } | |
56038ef6 | 409 | } |
56038ef6 | 410 | |
00cf5774 PB |
411 | /* values that are still don't care fire at the next min/sec */ |
412 | if (alarm_min == -1) { | |
413 | alarm_min = 0; | |
414 | } | |
415 | if (alarm_sec == -1) { | |
416 | alarm_sec = 0; | |
417 | } | |
418 | ||
419 | /* keep values in range */ | |
420 | if (alarm_sec == SEC_PER_MIN) { | |
421 | alarm_sec = 0; | |
422 | alarm_min++; | |
423 | } | |
424 | if (alarm_min == MIN_PER_HOUR) { | |
425 | alarm_min = 0; | |
426 | alarm_hour++; | |
427 | } | |
428 | alarm_hour %= HOUR_PER_DAY; | |
429 | ||
430 | hour = alarm_hour - cur_hour; | |
431 | min = hour * MIN_PER_HOUR + alarm_min - cur_min; | |
432 | sec = min * SEC_PER_MIN + alarm_sec - cur_sec; | |
433 | return sec <= 0 ? sec + SEC_PER_DAY : sec; | |
56038ef6 YZ |
434 | } |
435 | ||
436 | static void rtc_update_timer(void *opaque) | |
437 | { | |
438 | RTCState *s = opaque; | |
439 | int32_t irqs = REG_C_UF; | |
440 | int32_t new_irqs; | |
441 | ||
41a9b8b2 YZ |
442 | assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); |
443 | ||
56038ef6 YZ |
444 | /* UIP might have been latched, update time and clear it. */ |
445 | rtc_update_time(s); | |
446 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
447 | ||
884f17c2 | 448 | if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) { |
56038ef6 YZ |
449 | irqs |= REG_C_AF; |
450 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
451 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC); | |
452 | } | |
453 | } | |
00cf5774 | 454 | |
56038ef6 YZ |
455 | new_irqs = irqs & ~s->cmos_data[RTC_REG_C]; |
456 | s->cmos_data[RTC_REG_C] |= irqs; | |
457 | if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) { | |
458 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
459 | qemu_irq_raise(s->irq); | |
460 | } | |
461 | check_update_timer(s); | |
462 | } | |
463 | ||
0da8c842 AG |
464 | static void cmos_ioport_write(void *opaque, hwaddr addr, |
465 | uint64_t data, unsigned size) | |
80cabfad | 466 | { |
b41a2cd1 | 467 | RTCState *s = opaque; |
369b4135 | 468 | uint32_t old_period; |
9a6e2dcf | 469 | bool update_periodic_timer; |
80cabfad FB |
470 | |
471 | if ((addr & 1) == 0) { | |
472 | s->cmos_index = data & 0x7f; | |
473 | } else { | |
c5539cb4 | 474 | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n", |
ec51e364 | 475 | s->cmos_index, data); |
dff38e7b | 476 | switch(s->cmos_index) { |
80cabfad FB |
477 | case RTC_SECONDS_ALARM: |
478 | case RTC_MINUTES_ALARM: | |
479 | case RTC_HOURS_ALARM: | |
80cabfad | 480 | s->cmos_data[s->cmos_index] = data; |
56038ef6 | 481 | check_update_timer(s); |
80cabfad | 482 | break; |
e67edb94 PB |
483 | case RTC_IBM_PS2_CENTURY_BYTE: |
484 | s->cmos_index = RTC_CENTURY; | |
485 | /* fall through */ | |
486 | case RTC_CENTURY: | |
80cabfad FB |
487 | case RTC_SECONDS: |
488 | case RTC_MINUTES: | |
489 | case RTC_HOURS: | |
490 | case RTC_DAY_OF_WEEK: | |
491 | case RTC_DAY_OF_MONTH: | |
492 | case RTC_MONTH: | |
493 | case RTC_YEAR: | |
494 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b | 495 | /* if in set mode, do not update the time */ |
41a9b8b2 | 496 | if (rtc_running(s)) { |
dff38e7b | 497 | rtc_set_time(s); |
56038ef6 | 498 | check_update_timer(s); |
dff38e7b | 499 | } |
80cabfad FB |
500 | break; |
501 | case RTC_REG_A: | |
9a6e2dcf | 502 | update_periodic_timer = (s->cmos_data[RTC_REG_A] ^ data) & 0x0f; |
369b4135 | 503 | old_period = rtc_periodic_clock_ticks(s); |
9a6e2dcf | 504 | |
41a9b8b2 YZ |
505 | if ((data & 0x60) == 0x60) { |
506 | if (rtc_running(s)) { | |
507 | rtc_update_time(s); | |
508 | } | |
509 | /* What happens to UIP when divider reset is enabled is | |
510 | * unclear from the datasheet. Shouldn't matter much | |
511 | * though. | |
512 | */ | |
513 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
514 | } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && | |
515 | (data & 0x70) <= 0x20) { | |
516 | /* when the divider reset is removed, the first update cycle | |
517 | * begins one-half second later*/ | |
518 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
519 | s->offset = 500000000; | |
520 | rtc_set_time(s); | |
521 | } | |
522 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
523 | } | |
dff38e7b FB |
524 | /* UIP bit is read only */ |
525 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
526 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
9a6e2dcf XG |
527 | |
528 | if (update_periodic_timer) { | |
369b4135 TY |
529 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), |
530 | old_period); | |
9a6e2dcf XG |
531 | } |
532 | ||
56038ef6 | 533 | check_update_timer(s); |
dff38e7b | 534 | break; |
80cabfad | 535 | case RTC_REG_B: |
9a6e2dcf XG |
536 | update_periodic_timer = (s->cmos_data[RTC_REG_B] ^ data) |
537 | & REG_B_PIE; | |
369b4135 | 538 | old_period = rtc_periodic_clock_ticks(s); |
9a6e2dcf | 539 | |
dff38e7b | 540 | if (data & REG_B_SET) { |
56038ef6 | 541 | /* update cmos to when the rtc was stopping */ |
41a9b8b2 | 542 | if (rtc_running(s)) { |
56038ef6 YZ |
543 | rtc_update_time(s); |
544 | } | |
dff38e7b FB |
545 | /* set mode: reset UIP mode */ |
546 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
547 | data &= ~REG_B_UIE; | |
548 | } else { | |
549 | /* if disabling set mode, update the time */ | |
41a9b8b2 YZ |
550 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && |
551 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { | |
13566fe3 | 552 | s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
dff38e7b FB |
553 | rtc_set_time(s); |
554 | } | |
555 | } | |
9324cc50 YZ |
556 | /* if an interrupt flag is already set when the interrupt |
557 | * becomes enabled, raise an interrupt immediately. */ | |
558 | if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) { | |
559 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
560 | qemu_irq_raise(s->irq); | |
561 | } else { | |
562 | s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; | |
563 | qemu_irq_lower(s->irq); | |
564 | } | |
bedc572e | 565 | s->cmos_data[RTC_REG_B] = data; |
9a6e2dcf XG |
566 | |
567 | if (update_periodic_timer) { | |
369b4135 TY |
568 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), |
569 | old_period); | |
9a6e2dcf XG |
570 | } |
571 | ||
56038ef6 | 572 | check_update_timer(s); |
80cabfad FB |
573 | break; |
574 | case RTC_REG_C: | |
575 | case RTC_REG_D: | |
576 | /* cannot write to them */ | |
577 | break; | |
578 | default: | |
579 | s->cmos_data[s->cmos_index] = data; | |
580 | break; | |
581 | } | |
582 | } | |
583 | } | |
584 | ||
abd0c6bd | 585 | static inline int rtc_to_bcd(RTCState *s, int a) |
80cabfad | 586 | { |
6f1bf24d | 587 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
588 | return a; |
589 | } else { | |
590 | return ((a / 10) << 4) | (a % 10); | |
591 | } | |
80cabfad FB |
592 | } |
593 | ||
abd0c6bd | 594 | static inline int rtc_from_bcd(RTCState *s, int a) |
80cabfad | 595 | { |
00cf5774 PB |
596 | if ((a & 0xc0) == 0xc0) { |
597 | return -1; | |
598 | } | |
6f1bf24d | 599 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
600 | return a; |
601 | } else { | |
602 | return ((a >> 4) * 10) + (a & 0x0f); | |
603 | } | |
604 | } | |
605 | ||
e2826cf4 | 606 | static void rtc_get_time(RTCState *s, struct tm *tm) |
dff38e7b | 607 | { |
abd0c6bd PB |
608 | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
609 | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
610 | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); | |
3b89eb43 PB |
611 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { |
612 | tm->tm_hour %= 12; | |
613 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
614 | tm->tm_hour += 12; | |
615 | } | |
43f493af | 616 | } |
abd0c6bd PB |
617 | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
618 | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); | |
619 | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
b8994faf PB |
620 | tm->tm_year = |
621 | rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year + | |
622 | rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900; | |
e2826cf4 PB |
623 | } |
624 | ||
625 | static void rtc_set_time(RTCState *s) | |
626 | { | |
627 | struct tm tm; | |
80cd3478 | 628 | |
e2826cf4 | 629 | rtc_get_time(s, &tm); |
e2826cf4 | 630 | s->base_rtc = mktimegm(&tm); |
884f17c2 | 631 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 632 | |
e010ad8f | 633 | qapi_event_send_rtc_change(qemu_timedate_diff(&tm), &error_abort); |
43f493af FB |
634 | } |
635 | ||
e2826cf4 | 636 | static void rtc_set_cmos(RTCState *s, const struct tm *tm) |
43f493af | 637 | { |
42fc73a1 | 638 | int year; |
dff38e7b | 639 | |
abd0c6bd PB |
640 | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
641 | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); | |
c29cd656 | 642 | if (s->cmos_data[RTC_REG_B] & REG_B_24H) { |
43f493af | 643 | /* 24 hour format */ |
abd0c6bd | 644 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
43f493af FB |
645 | } else { |
646 | /* 12 hour format */ | |
3b89eb43 PB |
647 | int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
648 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); | |
43f493af FB |
649 | if (tm->tm_hour >= 12) |
650 | s->cmos_data[RTC_HOURS] |= 0x80; | |
651 | } | |
abd0c6bd PB |
652 | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1); |
653 | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); | |
654 | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1); | |
b8994faf PB |
655 | year = tm->tm_year + 1900 - s->base_year; |
656 | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100); | |
657 | s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100); | |
43f493af FB |
658 | } |
659 | ||
56038ef6 | 660 | static void rtc_update_time(RTCState *s) |
43f493af | 661 | { |
56038ef6 YZ |
662 | struct tm ret; |
663 | time_t guest_sec; | |
664 | int64_t guest_nsec; | |
665 | ||
666 | guest_nsec = get_guest_rtc_ns(s); | |
13566fe3 | 667 | guest_sec = guest_nsec / NANOSECONDS_PER_SECOND; |
56038ef6 | 668 | gmtime_r(&guest_sec, &ret); |
02c6ccc6 AH |
669 | |
670 | /* Is SET flag of Register B disabled? */ | |
671 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) { | |
672 | rtc_set_cmos(s, &ret); | |
673 | } | |
43f493af FB |
674 | } |
675 | ||
56038ef6 | 676 | static int update_in_progress(RTCState *s) |
43f493af | 677 | { |
56038ef6 | 678 | int64_t guest_nsec; |
3b46e624 | 679 | |
41a9b8b2 | 680 | if (!rtc_running(s)) { |
56038ef6 | 681 | return 0; |
dff38e7b | 682 | } |
e93379b0 AB |
683 | if (timer_pending(s->update_timer)) { |
684 | int64_t next_update_time = timer_expire_time_ns(s->update_timer); | |
56038ef6 | 685 | /* Latch UIP until the timer expires. */ |
884f17c2 AB |
686 | if (qemu_clock_get_ns(rtc_clock) >= |
687 | (next_update_time - UIP_HOLD_LENGTH)) { | |
56038ef6 YZ |
688 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
689 | return 1; | |
dff38e7b FB |
690 | } |
691 | } | |
692 | ||
56038ef6 YZ |
693 | guest_nsec = get_guest_rtc_ns(s); |
694 | /* UIP bit will be set at last 244us of every second. */ | |
13566fe3 SH |
695 | if ((guest_nsec % NANOSECONDS_PER_SECOND) >= |
696 | (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) { | |
56038ef6 | 697 | return 1; |
dff38e7b | 698 | } |
56038ef6 | 699 | return 0; |
80cabfad FB |
700 | } |
701 | ||
0da8c842 AG |
702 | static uint64_t cmos_ioport_read(void *opaque, hwaddr addr, |
703 | unsigned size) | |
80cabfad | 704 | { |
b41a2cd1 | 705 | RTCState *s = opaque; |
80cabfad FB |
706 | int ret; |
707 | if ((addr & 1) == 0) { | |
708 | return 0xff; | |
709 | } else { | |
710 | switch(s->cmos_index) { | |
e67edb94 PB |
711 | case RTC_IBM_PS2_CENTURY_BYTE: |
712 | s->cmos_index = RTC_CENTURY; | |
713 | /* fall through */ | |
714 | case RTC_CENTURY: | |
80cabfad FB |
715 | case RTC_SECONDS: |
716 | case RTC_MINUTES: | |
717 | case RTC_HOURS: | |
718 | case RTC_DAY_OF_WEEK: | |
719 | case RTC_DAY_OF_MONTH: | |
720 | case RTC_MONTH: | |
721 | case RTC_YEAR: | |
56038ef6 YZ |
722 | /* if not in set mode, calibrate cmos before |
723 | * reading*/ | |
41a9b8b2 | 724 | if (rtc_running(s)) { |
56038ef6 YZ |
725 | rtc_update_time(s); |
726 | } | |
80cabfad FB |
727 | ret = s->cmos_data[s->cmos_index]; |
728 | break; | |
729 | case RTC_REG_A: | |
56038ef6 YZ |
730 | if (update_in_progress(s)) { |
731 | s->cmos_data[s->cmos_index] |= REG_A_UIP; | |
732 | } else { | |
733 | s->cmos_data[s->cmos_index] &= ~REG_A_UIP; | |
734 | } | |
80cabfad | 735 | ret = s->cmos_data[s->cmos_index]; |
80cabfad FB |
736 | break; |
737 | case RTC_REG_C: | |
738 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 739 | qemu_irq_lower(s->irq); |
fbc15e27 | 740 | s->cmos_data[RTC_REG_C] = 0x00; |
56038ef6 YZ |
741 | if (ret & (REG_C_UF | REG_C_AF)) { |
742 | check_update_timer(s); | |
743 | } | |
e0c8b950 | 744 | |
ba32edab | 745 | if(s->irq_coalesced && |
fbc15e27 | 746 | (s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
ba32edab GN |
747 | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
748 | s->irq_reinject_on_ack_count++; | |
fbc15e27 | 749 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
aa6f63ff | 750 | DPRINTF_C("cmos: injecting on ack\n"); |
e0c8b950 | 751 | if (rtc_policy_slew_deliver_irq(s)) { |
ba32edab | 752 | s->irq_coalesced--; |
aa6f63ff BS |
753 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
754 | s->irq_coalesced); | |
755 | } | |
ba32edab | 756 | } |
80cabfad FB |
757 | break; |
758 | default: | |
759 | ret = s->cmos_data[s->cmos_index]; | |
760 | break; | |
761 | } | |
ec51e364 IY |
762 | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n", |
763 | s->cmos_index, ret); | |
80cabfad FB |
764 | return ret; |
765 | } | |
766 | } | |
767 | ||
1d914fa0 | 768 | void rtc_set_memory(ISADevice *dev, int addr, int val) |
dff38e7b | 769 | { |
0e41271e | 770 | RTCState *s = MC146818_RTC(dev); |
dff38e7b FB |
771 | if (addr >= 0 && addr <= 127) |
772 | s->cmos_data[addr] = val; | |
773 | } | |
774 | ||
b8b7456d IM |
775 | int rtc_get_memory(ISADevice *dev, int addr) |
776 | { | |
777 | RTCState *s = MC146818_RTC(dev); | |
778 | assert(addr >= 0 && addr <= 127); | |
779 | return s->cmos_data[addr]; | |
780 | } | |
781 | ||
1d914fa0 | 782 | static void rtc_set_date_from_host(ISADevice *dev) |
ea55ffb3 | 783 | { |
0e41271e | 784 | RTCState *s = MC146818_RTC(dev); |
f6503059 | 785 | struct tm tm; |
ea55ffb3 | 786 | |
f6503059 | 787 | qemu_get_timedate(&tm, 0); |
56038ef6 YZ |
788 | |
789 | s->base_rtc = mktimegm(&tm); | |
884f17c2 | 790 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 YZ |
791 | s->offset = 0; |
792 | ||
793 | /* set the CMOS date */ | |
e2826cf4 | 794 | rtc_set_cmos(s, &tm); |
ea55ffb3 TS |
795 | } |
796 | ||
3cf294ee JB |
797 | static void rtc_pre_save(void *opaque) |
798 | { | |
799 | RTCState *s = opaque; | |
800 | ||
801 | rtc_update_time(s); | |
802 | } | |
803 | ||
6b075b8a | 804 | static int rtc_post_load(void *opaque, int version_id) |
80cabfad | 805 | { |
dff38e7b FB |
806 | RTCState *s = opaque; |
807 | ||
3cf294ee | 808 | if (version_id <= 2 || rtc_clock == QEMU_CLOCK_REALTIME) { |
56038ef6 YZ |
809 | rtc_set_time(s); |
810 | s->offset = 0; | |
811 | check_update_timer(s); | |
812 | } | |
813 | ||
1dfb1b2d PD |
814 | /* The periodic timer is deterministic in record/replay mode, |
815 | * so there is no need to update it after loading the vmstate. | |
816 | * Reading RTC here would misalign record and replay. | |
817 | */ | |
818 | if (replay_mode == REPLAY_MODE_NONE) { | |
819 | uint64_t now = qemu_clock_get_ns(rtc_clock); | |
820 | if (now < s->next_periodic_time || | |
821 | now > (s->next_periodic_time + get_max_clock_jump())) { | |
369b4135 | 822 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), 0); |
1dfb1b2d | 823 | } |
ae46e239 PD |
824 | } |
825 | ||
048c74c4 | 826 | if (version_id >= 2) { |
104059da | 827 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
048c74c4 JQ |
828 | rtc_coalesced_timer_update(s); |
829 | } | |
048c74c4 | 830 | } |
73822ec8 AL |
831 | return 0; |
832 | } | |
73822ec8 | 833 | |
5cd8cada JQ |
834 | static bool rtc_irq_reinject_on_ack_count_needed(void *opaque) |
835 | { | |
836 | RTCState *s = (RTCState *)opaque; | |
837 | return s->irq_reinject_on_ack_count != 0; | |
838 | } | |
839 | ||
0b102153 | 840 | static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = { |
bb426311 | 841 | .name = "mc146818rtc/irq_reinject_on_ack_count", |
0b102153 PD |
842 | .version_id = 1, |
843 | .minimum_version_id = 1, | |
5cd8cada | 844 | .needed = rtc_irq_reinject_on_ack_count_needed, |
0b102153 PD |
845 | .fields = (VMStateField[]) { |
846 | VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState), | |
847 | VMSTATE_END_OF_LIST() | |
848 | } | |
849 | }; | |
850 | ||
6b075b8a JQ |
851 | static const VMStateDescription vmstate_rtc = { |
852 | .name = "mc146818rtc", | |
56038ef6 | 853 | .version_id = 3, |
6b075b8a | 854 | .minimum_version_id = 1, |
3cf294ee | 855 | .pre_save = rtc_pre_save, |
6b075b8a | 856 | .post_load = rtc_post_load, |
d49805ae | 857 | .fields = (VMStateField[]) { |
6b075b8a JQ |
858 | VMSTATE_BUFFER(cmos_data, RTCState), |
859 | VMSTATE_UINT8(cmos_index, RTCState), | |
89166459 | 860 | VMSTATE_UNUSED(7*4), |
e720677e | 861 | VMSTATE_TIMER_PTR(periodic_timer, RTCState), |
6b075b8a | 862 | VMSTATE_INT64(next_periodic_time, RTCState), |
56038ef6 | 863 | VMSTATE_UNUSED(3*8), |
6b075b8a JQ |
864 | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), |
865 | VMSTATE_UINT32_V(period, RTCState, 2), | |
56038ef6 YZ |
866 | VMSTATE_UINT64_V(base_rtc, RTCState, 3), |
867 | VMSTATE_UINT64_V(last_update, RTCState, 3), | |
868 | VMSTATE_INT64_V(offset, RTCState, 3), | |
e720677e | 869 | VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3), |
00cf5774 | 870 | VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), |
6b075b8a | 871 | VMSTATE_END_OF_LIST() |
0b102153 | 872 | }, |
5cd8cada JQ |
873 | .subsections = (const VMStateDescription*[]) { |
874 | &vmstate_rtc_irq_reinject_on_ack_count, | |
875 | NULL | |
6b075b8a JQ |
876 | } |
877 | }; | |
878 | ||
17604dac JK |
879 | static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
880 | { | |
881 | RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); | |
882 | int64_t now = *(int64_t *)data; | |
883 | ||
0e41271e | 884 | rtc_set_date_from_host(ISA_DEVICE(s)); |
369b4135 | 885 | periodic_timer_update(s, now, 0); |
56038ef6 | 886 | check_update_timer(s); |
388ad5d2 | 887 | |
104059da | 888 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
17604dac JK |
889 | rtc_coalesced_timer_update(s); |
890 | } | |
17604dac JK |
891 | } |
892 | ||
da98c8eb GH |
893 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
894 | BIOS will read it and start S3 resume at POST Entry */ | |
895 | static void rtc_notify_suspend(Notifier *notifier, void *data) | |
896 | { | |
897 | RTCState *s = container_of(notifier, RTCState, suspend_notifier); | |
0e41271e | 898 | rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE); |
da98c8eb GH |
899 | } |
900 | ||
eeb7c03c GN |
901 | static void rtc_reset(void *opaque) |
902 | { | |
903 | RTCState *s = opaque; | |
904 | ||
72716184 AL |
905 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
906 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
56038ef6 | 907 | check_update_timer(s); |
eeb7c03c | 908 | |
72716184 | 909 | qemu_irq_lower(s->irq); |
eeb7c03c | 910 | |
104059da | 911 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
433acf0d | 912 | s->irq_coalesced = 0; |
172dbc52 | 913 | s->irq_reinject_on_ack_count = 0; |
433acf0d | 914 | } |
eeb7c03c GN |
915 | } |
916 | ||
b2c5009b | 917 | static const MemoryRegionOps cmos_ops = { |
0da8c842 AG |
918 | .read = cmos_ioport_read, |
919 | .write = cmos_ioport_write, | |
920 | .impl = { | |
921 | .min_access_size = 1, | |
922 | .max_access_size = 1, | |
923 | }, | |
924 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b2c5009b RH |
925 | }; |
926 | ||
8e099d14 | 927 | static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp) |
18297050 | 928 | { |
0e41271e | 929 | RTCState *s = MC146818_RTC(obj); |
18297050 | 930 | |
56038ef6 | 931 | rtc_update_time(s); |
8e099d14 | 932 | rtc_get_time(s, current_tm); |
18297050 AL |
933 | } |
934 | ||
db895a1e | 935 | static void rtc_realizefn(DeviceState *dev, Error **errp) |
dff38e7b | 936 | { |
db895a1e | 937 | ISADevice *isadev = ISA_DEVICE(dev); |
0e41271e | 938 | RTCState *s = MC146818_RTC(dev); |
32e0c826 | 939 | int base = 0x70; |
80cabfad | 940 | |
80cabfad FB |
941 | s->cmos_data[RTC_REG_A] = 0x26; |
942 | s->cmos_data[RTC_REG_B] = 0x02; | |
943 | s->cmos_data[RTC_REG_C] = 0x00; | |
944 | s->cmos_data[RTC_REG_D] = 0x80; | |
945 | ||
b8994faf PB |
946 | /* This is for historical reasons. The default base year qdev property |
947 | * was set to 2000 for most machine types before the century byte was | |
948 | * implemented. | |
949 | * | |
950 | * This if statement means that the century byte will be always 0 | |
951 | * (at least until 2079...) for base_year = 1980, but will be set | |
952 | * correctly for base_year = 2000. | |
953 | */ | |
954 | if (s->base_year == 2000) { | |
955 | s->base_year = 0; | |
956 | } | |
957 | ||
db895a1e | 958 | rtc_set_date_from_host(isadev); |
ea55ffb3 | 959 | |
433acf0d | 960 | switch (s->lost_tick_policy) { |
4aa70a0e | 961 | #ifdef TARGET_I386 |
104059da | 962 | case LOST_TICK_POLICY_SLEW: |
6875204c | 963 | s->coalesced_timer = |
884f17c2 | 964 | timer_new_ns(rtc_clock, rtc_coalesced_timer, s); |
433acf0d | 965 | break; |
4aa70a0e | 966 | #endif |
104059da | 967 | case LOST_TICK_POLICY_DISCARD: |
433acf0d JK |
968 | break; |
969 | default: | |
db895a1e AF |
970 | error_setg(errp, "Invalid lost tick policy."); |
971 | return; | |
433acf0d | 972 | } |
433acf0d | 973 | |
884f17c2 AB |
974 | s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s); |
975 | s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s); | |
56038ef6 | 976 | check_update_timer(s); |
dff38e7b | 977 | |
17604dac | 978 | s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
13c0cbae | 979 | qemu_clock_register_reset_notifier(rtc_clock, |
884f17c2 | 980 | &s->clock_reset_notifier); |
17604dac | 981 | |
da98c8eb GH |
982 | s->suspend_notifier.notify = rtc_notify_suspend; |
983 | qemu_register_suspend_notifier(&s->suspend_notifier); | |
984 | ||
853dca12 | 985 | memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2); |
db895a1e | 986 | isa_register_ioport(isadev, &s->io, base); |
dff38e7b | 987 | |
db895a1e | 988 | qdev_set_legacy_instance_id(dev, base, 3); |
a08d4367 | 989 | qemu_register_reset(rtc_reset, s); |
18297050 | 990 | |
8e099d14 | 991 | object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL); |
654a36d8 MT |
992 | |
993 | object_property_add_alias(qdev_get_machine(), "rtc-time", | |
994 | OBJECT(s), "date", NULL); | |
3638439d EV |
995 | |
996 | qdev_init_gpio_out(dev, &s->irq, 1); | |
32e0c826 GH |
997 | } |
998 | ||
48a18b3c | 999 | ISADevice *rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) |
32e0c826 | 1000 | { |
0e41271e AF |
1001 | DeviceState *dev; |
1002 | ISADevice *isadev; | |
7d932dfd | 1003 | RTCState *s; |
eeb7c03c | 1004 | |
0e41271e AF |
1005 | isadev = isa_create(bus, TYPE_MC146818_RTC); |
1006 | dev = DEVICE(isadev); | |
1007 | s = MC146818_RTC(isadev); | |
1008 | qdev_prop_set_int32(dev, "base_year", base_year); | |
1009 | qdev_init_nofail(dev); | |
7d932dfd | 1010 | if (intercept_irq) { |
3638439d | 1011 | qdev_connect_gpio_out(dev, 0, intercept_irq); |
7d932dfd | 1012 | } else { |
3638439d | 1013 | isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ); |
7d932dfd | 1014 | } |
f2ae8abf MT |
1015 | QLIST_INSERT_HEAD(&rtc_devices, s, link); |
1016 | ||
0e41271e | 1017 | return isadev; |
80cabfad FB |
1018 | } |
1019 | ||
39bffca2 AL |
1020 | static Property mc146818rtc_properties[] = { |
1021 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
1022 | DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, | |
104059da | 1023 | lost_tick_policy, LOST_TICK_POLICY_DISCARD), |
39bffca2 AL |
1024 | DEFINE_PROP_END_OF_LIST(), |
1025 | }; | |
1026 | ||
bf7bb91e | 1027 | static void rtc_resetdev(DeviceState *d) |
1028 | { | |
1029 | RTCState *s = MC146818_RTC(d); | |
1030 | ||
1031 | /* Reason: VM do suspend self will set 0xfe | |
1032 | * Reset any values other than 0xfe(Guest suspend case) */ | |
1033 | if (s->cmos_data[0x0f] != 0xfe) { | |
1034 | s->cmos_data[0x0f] = 0x00; | |
1035 | } | |
1036 | } | |
1037 | ||
8f04ee08 AL |
1038 | static void rtc_class_initfn(ObjectClass *klass, void *data) |
1039 | { | |
39bffca2 | 1040 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
1041 | |
1042 | dc->realize = rtc_realizefn; | |
bf7bb91e | 1043 | dc->reset = rtc_resetdev; |
39bffca2 AL |
1044 | dc->vmsd = &vmstate_rtc; |
1045 | dc->props = mc146818rtc_properties; | |
f3b17640 | 1046 | /* Reason: needs to be wired up by rtc_init() */ |
e90f2a8c | 1047 | dc->user_creatable = false; |
8f04ee08 AL |
1048 | } |
1049 | ||
654a36d8 MT |
1050 | static void rtc_finalize(Object *obj) |
1051 | { | |
1052 | object_property_del(qdev_get_machine(), "rtc", NULL); | |
1053 | } | |
1054 | ||
8c43a6f0 | 1055 | static const TypeInfo mc146818rtc_info = { |
0e41271e | 1056 | .name = TYPE_MC146818_RTC, |
39bffca2 AL |
1057 | .parent = TYPE_ISA_DEVICE, |
1058 | .instance_size = sizeof(RTCState), | |
1059 | .class_init = rtc_class_initfn, | |
654a36d8 | 1060 | .instance_finalize = rtc_finalize, |
32e0c826 GH |
1061 | }; |
1062 | ||
83f7d43a | 1063 | static void mc146818rtc_register_types(void) |
100d9891 | 1064 | { |
39bffca2 | 1065 | type_register_static(&mc146818rtc_info); |
100d9891 | 1066 | } |
83f7d43a AF |
1067 | |
1068 | type_init(mc146818rtc_register_types) |