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Commit | Line | Data |
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80cabfad FB |
1 | /* |
2 | * QEMU MC146818 RTC emulation | |
5fafdf24 | 3 | * |
80cabfad | 4 | * Copyright (c) 2003-2004 Fabrice Bellard |
5fafdf24 | 5 | * |
80cabfad FB |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e688df6b | 24 | |
b6a0aa05 | 25 | #include "qemu/osdep.h" |
f348b6d1 VB |
26 | #include "qemu/cutils.h" |
27 | #include "qemu/bcd.h" | |
83c9f4ca | 28 | #include "hw/hw.h" |
1de7afc9 | 29 | #include "qemu/timer.h" |
9c17d615 | 30 | #include "sysemu/sysemu.h" |
1dfb1b2d | 31 | #include "sysemu/replay.h" |
0d09e41a | 32 | #include "hw/timer/mc146818rtc.h" |
e688df6b | 33 | #include "qapi/error.h" |
a6c7040f | 34 | #include "qapi/qapi-commands-target.h" |
183e4281 | 35 | #include "qapi/qapi-events-target.h" |
7b1b5d19 | 36 | #include "qapi/visitor.h" |
f98167ea | 37 | #include "exec/address-spaces.h" |
80cabfad | 38 | |
d362e757 | 39 | #ifdef TARGET_I386 |
0d09e41a | 40 | #include "hw/i386/apic.h" |
d362e757 JK |
41 | #endif |
42 | ||
80cabfad | 43 | //#define DEBUG_CMOS |
aa6f63ff | 44 | //#define DEBUG_COALESCED |
80cabfad | 45 | |
ec51e364 IY |
46 | #ifdef DEBUG_CMOS |
47 | # define CMOS_DPRINTF(format, ...) printf(format, ## __VA_ARGS__) | |
48 | #else | |
49 | # define CMOS_DPRINTF(format, ...) do { } while (0) | |
50 | #endif | |
51 | ||
aa6f63ff BS |
52 | #ifdef DEBUG_COALESCED |
53 | # define DPRINTF_C(format, ...) printf(format, ## __VA_ARGS__) | |
54 | #else | |
55 | # define DPRINTF_C(format, ...) do { } while (0) | |
56 | #endif | |
57 | ||
00cf5774 PB |
58 | #define SEC_PER_MIN 60 |
59 | #define MIN_PER_HOUR 60 | |
60 | #define SEC_PER_HOUR 3600 | |
61 | #define HOUR_PER_DAY 24 | |
62 | #define SEC_PER_DAY 86400 | |
56038ef6 | 63 | |
dd17765b | 64 | #define RTC_REINJECT_ON_ACK_COUNT 20 |
e46deaba | 65 | #define RTC_CLOCK_RATE 32768 |
13566fe3 | 66 | #define UIP_HOLD_LENGTH (8 * NANOSECONDS_PER_SECOND / 32768) |
ba32edab | 67 | |
0e41271e AF |
68 | #define MC146818_RTC(obj) OBJECT_CHECK(RTCState, (obj), TYPE_MC146818_RTC) |
69 | ||
1d914fa0 | 70 | typedef struct RTCState { |
0e41271e AF |
71 | ISADevice parent_obj; |
72 | ||
b2c5009b | 73 | MemoryRegion io; |
f98167ea | 74 | MemoryRegion coalesced_io; |
dff38e7b FB |
75 | uint8_t cmos_data[128]; |
76 | uint8_t cmos_index; | |
32e0c826 | 77 | int32_t base_year; |
56038ef6 YZ |
78 | uint64_t base_rtc; |
79 | uint64_t last_update; | |
80 | int64_t offset; | |
d537cf6c | 81 | qemu_irq irq; |
18c6e2ff | 82 | int it_shift; |
dff38e7b FB |
83 | /* periodic timer */ |
84 | QEMUTimer *periodic_timer; | |
85 | int64_t next_periodic_time; | |
56038ef6 YZ |
86 | /* update-ended timer */ |
87 | QEMUTimer *update_timer; | |
00cf5774 | 88 | uint64_t next_alarm_time; |
ba32edab | 89 | uint16_t irq_reinject_on_ack_count; |
73822ec8 AL |
90 | uint32_t irq_coalesced; |
91 | uint32_t period; | |
93b66569 | 92 | QEMUTimer *coalesced_timer; |
17604dac | 93 | Notifier clock_reset_notifier; |
433acf0d | 94 | LostTickPolicy lost_tick_policy; |
da98c8eb | 95 | Notifier suspend_notifier; |
f2ae8abf | 96 | QLIST_ENTRY(RTCState) link; |
1d914fa0 | 97 | } RTCState; |
dff38e7b FB |
98 | |
99 | static void rtc_set_time(RTCState *s); | |
56038ef6 | 100 | static void rtc_update_time(RTCState *s); |
e2826cf4 | 101 | static void rtc_set_cmos(RTCState *s, const struct tm *tm); |
56038ef6 | 102 | static inline int rtc_from_bcd(RTCState *s, int a); |
00cf5774 | 103 | static uint64_t get_next_alarm(RTCState *s); |
56038ef6 | 104 | |
41a9b8b2 YZ |
105 | static inline bool rtc_running(RTCState *s) |
106 | { | |
107 | return (!(s->cmos_data[RTC_REG_B] & REG_B_SET) && | |
108 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20); | |
109 | } | |
110 | ||
56038ef6 YZ |
111 | static uint64_t get_guest_rtc_ns(RTCState *s) |
112 | { | |
884f17c2 | 113 | uint64_t guest_clock = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 114 | |
9be38598 | 115 | return s->base_rtc * NANOSECONDS_PER_SECOND + |
73bcb24d | 116 | guest_clock - s->last_update + s->offset; |
56038ef6 | 117 | } |
dff38e7b | 118 | |
93b66569 AL |
119 | static void rtc_coalesced_timer_update(RTCState *s) |
120 | { | |
121 | if (s->irq_coalesced == 0) { | |
bc72ad67 | 122 | timer_del(s->coalesced_timer); |
93b66569 AL |
123 | } else { |
124 | /* divide each RTC interval to 2 - 8 smaller intervals */ | |
7cd9681b | 125 | int c = MIN(s->irq_coalesced, 7) + 1; |
884f17c2 | 126 | int64_t next_clock = qemu_clock_get_ns(rtc_clock) + |
bd618eab | 127 | periodic_clock_to_ns(s->period / c); |
bc72ad67 | 128 | timer_mod(s->coalesced_timer, next_clock); |
93b66569 AL |
129 | } |
130 | } | |
131 | ||
e0c8b950 XG |
132 | static QLIST_HEAD(, RTCState) rtc_devices = |
133 | QLIST_HEAD_INITIALIZER(rtc_devices); | |
134 | ||
388ad5d2 | 135 | #ifdef TARGET_I386 |
e0c8b950 XG |
136 | void qmp_rtc_reset_reinjection(Error **errp) |
137 | { | |
138 | RTCState *s; | |
139 | ||
140 | QLIST_FOREACH(s, &rtc_devices, link) { | |
141 | s->irq_coalesced = 0; | |
142 | } | |
143 | } | |
144 | ||
145 | static bool rtc_policy_slew_deliver_irq(RTCState *s) | |
146 | { | |
147 | apic_reset_irq_delivered(); | |
148 | qemu_irq_raise(s->irq); | |
149 | return apic_get_irq_delivered(); | |
150 | } | |
151 | ||
93b66569 AL |
152 | static void rtc_coalesced_timer(void *opaque) |
153 | { | |
154 | RTCState *s = opaque; | |
155 | ||
156 | if (s->irq_coalesced != 0) { | |
93b66569 | 157 | s->cmos_data[RTC_REG_C] |= 0xc0; |
aa6f63ff | 158 | DPRINTF_C("cmos: injecting from timer\n"); |
e0c8b950 | 159 | if (rtc_policy_slew_deliver_irq(s)) { |
93b66569 | 160 | s->irq_coalesced--; |
aa6f63ff BS |
161 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
162 | s->irq_coalesced); | |
93b66569 AL |
163 | } |
164 | } | |
165 | ||
166 | rtc_coalesced_timer_update(s); | |
167 | } | |
e0c8b950 XG |
168 | #else |
169 | static bool rtc_policy_slew_deliver_irq(RTCState *s) | |
170 | { | |
171 | assert(0); | |
172 | return false; | |
173 | } | |
93b66569 AL |
174 | #endif |
175 | ||
369b4135 | 176 | static uint32_t rtc_periodic_clock_ticks(RTCState *s) |
dff38e7b | 177 | { |
369b4135 TY |
178 | int period_code; |
179 | ||
180 | if (!(s->cmos_data[RTC_REG_B] & REG_B_PIE)) { | |
181 | return 0; | |
182 | } | |
dff38e7b FB |
183 | |
184 | period_code = s->cmos_data[RTC_REG_A] & 0x0f; | |
369b4135 | 185 | |
bd618eab | 186 | return periodic_period_to_clock(period_code); |
369b4135 TY |
187 | } |
188 | ||
189 | /* | |
190 | * handle periodic timer. @old_period indicates the periodic timer update | |
191 | * is just due to period adjustment. | |
192 | */ | |
193 | static void | |
194 | periodic_timer_update(RTCState *s, int64_t current_time, uint32_t old_period) | |
195 | { | |
196 | uint32_t period; | |
197 | int64_t cur_clock, next_irq_clock, lost_clock = 0; | |
198 | ||
199 | period = rtc_periodic_clock_ticks(s); | |
200 | ||
201 | if (period) { | |
dff38e7b | 202 | /* compute 32 khz clock */ |
73bcb24d RS |
203 | cur_clock = |
204 | muldiv64(current_time, RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); | |
205 | ||
369b4135 TY |
206 | /* |
207 | * if the periodic timer's update is due to period re-configuration, | |
208 | * we should count the clock since last interrupt. | |
209 | */ | |
210 | if (old_period) { | |
211 | int64_t last_periodic_clock, next_periodic_clock; | |
212 | ||
213 | next_periodic_clock = muldiv64(s->next_periodic_time, | |
214 | RTC_CLOCK_RATE, NANOSECONDS_PER_SECOND); | |
215 | last_periodic_clock = next_periodic_clock - old_period; | |
216 | lost_clock = cur_clock - last_periodic_clock; | |
217 | assert(lost_clock >= 0); | |
218 | } | |
219 | ||
369b4135 TY |
220 | /* |
221 | * s->irq_coalesced can change for two reasons: | |
222 | * | |
223 | * a) if one or more periodic timer interrupts have been lost, | |
224 | * lost_clock will be more that a period. | |
225 | * | |
226 | * b) when the period may be reconfigured, we expect the OS to | |
227 | * treat delayed tick as the new period. So, when switching | |
228 | * from a shorter to a longer period, scale down the missing, | |
229 | * because the OS will treat past delayed ticks as longer | |
230 | * (leftovers are put back into lost_clock). When switching | |
231 | * to a shorter period, scale up the missing ticks since the | |
232 | * OS handler will treat past delayed ticks as shorter. | |
233 | */ | |
234 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { | |
235 | uint32_t old_irq_coalesced = s->irq_coalesced; | |
236 | ||
237 | s->period = period; | |
238 | lost_clock += old_irq_coalesced * old_period; | |
239 | s->irq_coalesced = lost_clock / s->period; | |
240 | lost_clock %= s->period; | |
241 | if (old_irq_coalesced != s->irq_coalesced || | |
242 | old_period != s->period) { | |
243 | DPRINTF_C("cmos: coalesced irqs scaled from %d to %d, " | |
244 | "period scaled from %d to %d\n", old_irq_coalesced, | |
245 | s->irq_coalesced, old_period, s->period); | |
246 | rtc_coalesced_timer_update(s); | |
247 | } | |
388ad5d2 | 248 | } else { |
369b4135 TY |
249 | /* |
250 | * no way to compensate the interrupt if LOST_TICK_POLICY_SLEW | |
251 | * is not used, we should make the time progress anyway. | |
252 | */ | |
253 | lost_clock = MIN(lost_clock, period); | |
254 | } | |
255 | ||
256 | assert(lost_clock >= 0 && lost_clock <= period); | |
257 | ||
258 | next_irq_clock = cur_clock + period - lost_clock; | |
bd618eab | 259 | s->next_periodic_time = periodic_clock_to_ns(next_irq_clock) + 1; |
bc72ad67 | 260 | timer_mod(s->periodic_timer, s->next_periodic_time); |
dff38e7b | 261 | } else { |
73822ec8 | 262 | s->irq_coalesced = 0; |
bc72ad67 | 263 | timer_del(s->periodic_timer); |
dff38e7b FB |
264 | } |
265 | } | |
266 | ||
267 | static void rtc_periodic_timer(void *opaque) | |
268 | { | |
269 | RTCState *s = opaque; | |
270 | ||
369b4135 | 271 | periodic_timer_update(s, s->next_periodic_time, 0); |
663447d4 | 272 | s->cmos_data[RTC_REG_C] |= REG_C_PF; |
100d9891 | 273 | if (s->cmos_data[RTC_REG_B] & REG_B_PIE) { |
663447d4 | 274 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; |
104059da | 275 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
ba32edab | 276 | if (s->irq_reinject_on_ack_count >= RTC_REINJECT_ON_ACK_COUNT) |
e0c8b950 XG |
277 | s->irq_reinject_on_ack_count = 0; |
278 | if (!rtc_policy_slew_deliver_irq(s)) { | |
93b66569 AL |
279 | s->irq_coalesced++; |
280 | rtc_coalesced_timer_update(s); | |
aa6f63ff BS |
281 | DPRINTF_C("cmos: coalesced irqs increased to %d\n", |
282 | s->irq_coalesced); | |
93b66569 AL |
283 | } |
284 | } else | |
e0c8b950 | 285 | qemu_irq_raise(s->irq); |
100d9891 | 286 | } |
dff38e7b | 287 | } |
80cabfad | 288 | |
56038ef6 YZ |
289 | /* handle update-ended timer */ |
290 | static void check_update_timer(RTCState *s) | |
291 | { | |
292 | uint64_t next_update_time; | |
293 | uint64_t guest_nsec; | |
00cf5774 | 294 | int next_alarm_sec; |
56038ef6 | 295 | |
41a9b8b2 YZ |
296 | /* From the data sheet: "Holding the dividers in reset prevents |
297 | * interrupts from operating, while setting the SET bit allows" | |
6a51d83a | 298 | * them to occur. |
56038ef6 | 299 | */ |
41a9b8b2 | 300 | if ((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) { |
33f21e4f | 301 | assert((s->cmos_data[RTC_REG_A] & REG_A_UIP) == 0); |
bc72ad67 | 302 | timer_del(s->update_timer); |
41a9b8b2 YZ |
303 | return; |
304 | } | |
56038ef6 | 305 | |
13566fe3 | 306 | guest_nsec = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
884f17c2 | 307 | next_update_time = qemu_clock_get_ns(rtc_clock) |
13566fe3 | 308 | + NANOSECONDS_PER_SECOND - guest_nsec; |
00cf5774 PB |
309 | |
310 | /* Compute time of next alarm. One second is already accounted | |
311 | * for in next_update_time. | |
312 | */ | |
313 | next_alarm_sec = get_next_alarm(s); | |
13566fe3 SH |
314 | s->next_alarm_time = next_update_time + |
315 | (next_alarm_sec - 1) * NANOSECONDS_PER_SECOND; | |
00cf5774 | 316 | |
33f21e4f PB |
317 | /* If update_in_progress latched the UIP bit, we must keep the timer |
318 | * programmed to the next second, so that UIP is cleared. Otherwise, | |
319 | * if UF is already set, we might be able to optimize. | |
320 | */ | |
321 | if (!(s->cmos_data[RTC_REG_A] & REG_A_UIP) && | |
322 | (s->cmos_data[RTC_REG_C] & REG_C_UF)) { | |
6a51d83a PB |
323 | /* If AF cannot change (i.e. either it is set already, or |
324 | * SET=1 and then the time is not updated), nothing to do. | |
325 | */ | |
326 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) || | |
327 | (s->cmos_data[RTC_REG_C] & REG_C_AF)) { | |
328 | timer_del(s->update_timer); | |
329 | return; | |
330 | } | |
331 | ||
00cf5774 PB |
332 | /* UF is set, but AF is clear. Program the timer to target |
333 | * the alarm time. */ | |
334 | next_update_time = s->next_alarm_time; | |
335 | } | |
e93379b0 | 336 | if (next_update_time != timer_expire_time_ns(s->update_timer)) { |
bc72ad67 | 337 | timer_mod(s->update_timer, next_update_time); |
56038ef6 YZ |
338 | } |
339 | } | |
340 | ||
341 | static inline uint8_t convert_hour(RTCState *s, uint8_t hour) | |
342 | { | |
343 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { | |
344 | hour %= 12; | |
345 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
346 | hour += 12; | |
347 | } | |
348 | } | |
349 | return hour; | |
350 | } | |
351 | ||
00cf5774 | 352 | static uint64_t get_next_alarm(RTCState *s) |
56038ef6 | 353 | { |
00cf5774 PB |
354 | int32_t alarm_sec, alarm_min, alarm_hour, cur_hour, cur_min, cur_sec; |
355 | int32_t hour, min, sec; | |
356 | ||
357 | rtc_update_time(s); | |
56038ef6 YZ |
358 | |
359 | alarm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS_ALARM]); | |
360 | alarm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES_ALARM]); | |
361 | alarm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS_ALARM]); | |
00cf5774 | 362 | alarm_hour = alarm_hour == -1 ? -1 : convert_hour(s, alarm_hour); |
56038ef6 YZ |
363 | |
364 | cur_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); | |
365 | cur_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
366 | cur_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS]); | |
367 | cur_hour = convert_hour(s, cur_hour); | |
368 | ||
00cf5774 PB |
369 | if (alarm_hour == -1) { |
370 | alarm_hour = cur_hour; | |
371 | if (alarm_min == -1) { | |
372 | alarm_min = cur_min; | |
373 | if (alarm_sec == -1) { | |
374 | alarm_sec = cur_sec + 1; | |
375 | } else if (cur_sec > alarm_sec) { | |
376 | alarm_min++; | |
377 | } | |
378 | } else if (cur_min == alarm_min) { | |
379 | if (alarm_sec == -1) { | |
380 | alarm_sec = cur_sec + 1; | |
381 | } else { | |
382 | if (cur_sec > alarm_sec) { | |
383 | alarm_hour++; | |
384 | } | |
385 | } | |
386 | if (alarm_sec == SEC_PER_MIN) { | |
387 | /* wrap to next hour, minutes is not in don't care mode */ | |
388 | alarm_sec = 0; | |
389 | alarm_hour++; | |
390 | } | |
391 | } else if (cur_min > alarm_min) { | |
392 | alarm_hour++; | |
393 | } | |
394 | } else if (cur_hour == alarm_hour) { | |
395 | if (alarm_min == -1) { | |
396 | alarm_min = cur_min; | |
397 | if (alarm_sec == -1) { | |
398 | alarm_sec = cur_sec + 1; | |
399 | } else if (cur_sec > alarm_sec) { | |
400 | alarm_min++; | |
401 | } | |
402 | ||
403 | if (alarm_sec == SEC_PER_MIN) { | |
404 | alarm_sec = 0; | |
405 | alarm_min++; | |
406 | } | |
407 | /* wrap to next day, hour is not in don't care mode */ | |
408 | alarm_min %= MIN_PER_HOUR; | |
409 | } else if (cur_min == alarm_min) { | |
410 | if (alarm_sec == -1) { | |
411 | alarm_sec = cur_sec + 1; | |
412 | } | |
413 | /* wrap to next day, hours+minutes not in don't care mode */ | |
414 | alarm_sec %= SEC_PER_MIN; | |
415 | } | |
56038ef6 | 416 | } |
56038ef6 | 417 | |
00cf5774 PB |
418 | /* values that are still don't care fire at the next min/sec */ |
419 | if (alarm_min == -1) { | |
420 | alarm_min = 0; | |
421 | } | |
422 | if (alarm_sec == -1) { | |
423 | alarm_sec = 0; | |
424 | } | |
425 | ||
426 | /* keep values in range */ | |
427 | if (alarm_sec == SEC_PER_MIN) { | |
428 | alarm_sec = 0; | |
429 | alarm_min++; | |
430 | } | |
431 | if (alarm_min == MIN_PER_HOUR) { | |
432 | alarm_min = 0; | |
433 | alarm_hour++; | |
434 | } | |
435 | alarm_hour %= HOUR_PER_DAY; | |
436 | ||
437 | hour = alarm_hour - cur_hour; | |
438 | min = hour * MIN_PER_HOUR + alarm_min - cur_min; | |
439 | sec = min * SEC_PER_MIN + alarm_sec - cur_sec; | |
440 | return sec <= 0 ? sec + SEC_PER_DAY : sec; | |
56038ef6 YZ |
441 | } |
442 | ||
443 | static void rtc_update_timer(void *opaque) | |
444 | { | |
445 | RTCState *s = opaque; | |
446 | int32_t irqs = REG_C_UF; | |
447 | int32_t new_irqs; | |
448 | ||
41a9b8b2 YZ |
449 | assert((s->cmos_data[RTC_REG_A] & 0x60) != 0x60); |
450 | ||
56038ef6 YZ |
451 | /* UIP might have been latched, update time and clear it. */ |
452 | rtc_update_time(s); | |
453 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
454 | ||
884f17c2 | 455 | if (qemu_clock_get_ns(rtc_clock) >= s->next_alarm_time) { |
56038ef6 YZ |
456 | irqs |= REG_C_AF; |
457 | if (s->cmos_data[RTC_REG_B] & REG_B_AIE) { | |
fb064112 | 458 | qemu_system_wakeup_request(QEMU_WAKEUP_REASON_RTC, NULL); |
56038ef6 YZ |
459 | } |
460 | } | |
00cf5774 | 461 | |
56038ef6 YZ |
462 | new_irqs = irqs & ~s->cmos_data[RTC_REG_C]; |
463 | s->cmos_data[RTC_REG_C] |= irqs; | |
464 | if ((new_irqs & s->cmos_data[RTC_REG_B]) != 0) { | |
465 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
466 | qemu_irq_raise(s->irq); | |
467 | } | |
468 | check_update_timer(s); | |
469 | } | |
470 | ||
0da8c842 AG |
471 | static void cmos_ioport_write(void *opaque, hwaddr addr, |
472 | uint64_t data, unsigned size) | |
80cabfad | 473 | { |
b41a2cd1 | 474 | RTCState *s = opaque; |
369b4135 | 475 | uint32_t old_period; |
9a6e2dcf | 476 | bool update_periodic_timer; |
80cabfad FB |
477 | |
478 | if ((addr & 1) == 0) { | |
479 | s->cmos_index = data & 0x7f; | |
480 | } else { | |
c5539cb4 | 481 | CMOS_DPRINTF("cmos: write index=0x%02x val=0x%02" PRIx64 "\n", |
ec51e364 | 482 | s->cmos_index, data); |
dff38e7b | 483 | switch(s->cmos_index) { |
80cabfad FB |
484 | case RTC_SECONDS_ALARM: |
485 | case RTC_MINUTES_ALARM: | |
486 | case RTC_HOURS_ALARM: | |
80cabfad | 487 | s->cmos_data[s->cmos_index] = data; |
56038ef6 | 488 | check_update_timer(s); |
80cabfad | 489 | break; |
7cd9681b | 490 | case RTC_IBM_PS2_CENTURY_BYTE: |
e67edb94 PB |
491 | s->cmos_index = RTC_CENTURY; |
492 | /* fall through */ | |
493 | case RTC_CENTURY: | |
80cabfad FB |
494 | case RTC_SECONDS: |
495 | case RTC_MINUTES: | |
496 | case RTC_HOURS: | |
497 | case RTC_DAY_OF_WEEK: | |
498 | case RTC_DAY_OF_MONTH: | |
499 | case RTC_MONTH: | |
500 | case RTC_YEAR: | |
501 | s->cmos_data[s->cmos_index] = data; | |
dff38e7b | 502 | /* if in set mode, do not update the time */ |
41a9b8b2 | 503 | if (rtc_running(s)) { |
dff38e7b | 504 | rtc_set_time(s); |
56038ef6 | 505 | check_update_timer(s); |
dff38e7b | 506 | } |
80cabfad FB |
507 | break; |
508 | case RTC_REG_A: | |
9a6e2dcf | 509 | update_periodic_timer = (s->cmos_data[RTC_REG_A] ^ data) & 0x0f; |
369b4135 | 510 | old_period = rtc_periodic_clock_ticks(s); |
9a6e2dcf | 511 | |
41a9b8b2 YZ |
512 | if ((data & 0x60) == 0x60) { |
513 | if (rtc_running(s)) { | |
514 | rtc_update_time(s); | |
515 | } | |
516 | /* What happens to UIP when divider reset is enabled is | |
517 | * unclear from the datasheet. Shouldn't matter much | |
518 | * though. | |
519 | */ | |
520 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
521 | } else if (((s->cmos_data[RTC_REG_A] & 0x60) == 0x60) && | |
522 | (data & 0x70) <= 0x20) { | |
523 | /* when the divider reset is removed, the first update cycle | |
524 | * begins one-half second later*/ | |
525 | if (!(s->cmos_data[RTC_REG_B] & REG_B_SET)) { | |
526 | s->offset = 500000000; | |
527 | rtc_set_time(s); | |
528 | } | |
529 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
530 | } | |
dff38e7b FB |
531 | /* UIP bit is read only */ |
532 | s->cmos_data[RTC_REG_A] = (data & ~REG_A_UIP) | | |
533 | (s->cmos_data[RTC_REG_A] & REG_A_UIP); | |
9a6e2dcf XG |
534 | |
535 | if (update_periodic_timer) { | |
369b4135 TY |
536 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), |
537 | old_period); | |
9a6e2dcf XG |
538 | } |
539 | ||
56038ef6 | 540 | check_update_timer(s); |
dff38e7b | 541 | break; |
80cabfad | 542 | case RTC_REG_B: |
9a6e2dcf XG |
543 | update_periodic_timer = (s->cmos_data[RTC_REG_B] ^ data) |
544 | & REG_B_PIE; | |
369b4135 | 545 | old_period = rtc_periodic_clock_ticks(s); |
9a6e2dcf | 546 | |
dff38e7b | 547 | if (data & REG_B_SET) { |
56038ef6 | 548 | /* update cmos to when the rtc was stopping */ |
41a9b8b2 | 549 | if (rtc_running(s)) { |
56038ef6 YZ |
550 | rtc_update_time(s); |
551 | } | |
dff38e7b FB |
552 | /* set mode: reset UIP mode */ |
553 | s->cmos_data[RTC_REG_A] &= ~REG_A_UIP; | |
554 | data &= ~REG_B_UIE; | |
555 | } else { | |
556 | /* if disabling set mode, update the time */ | |
41a9b8b2 YZ |
557 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) && |
558 | (s->cmos_data[RTC_REG_A] & 0x70) <= 0x20) { | |
13566fe3 | 559 | s->offset = get_guest_rtc_ns(s) % NANOSECONDS_PER_SECOND; |
dff38e7b FB |
560 | rtc_set_time(s); |
561 | } | |
562 | } | |
9324cc50 YZ |
563 | /* if an interrupt flag is already set when the interrupt |
564 | * becomes enabled, raise an interrupt immediately. */ | |
565 | if (data & s->cmos_data[RTC_REG_C] & REG_C_MASK) { | |
566 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF; | |
567 | qemu_irq_raise(s->irq); | |
568 | } else { | |
569 | s->cmos_data[RTC_REG_C] &= ~REG_C_IRQF; | |
570 | qemu_irq_lower(s->irq); | |
571 | } | |
bedc572e | 572 | s->cmos_data[RTC_REG_B] = data; |
9a6e2dcf XG |
573 | |
574 | if (update_periodic_timer) { | |
369b4135 TY |
575 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), |
576 | old_period); | |
9a6e2dcf XG |
577 | } |
578 | ||
56038ef6 | 579 | check_update_timer(s); |
80cabfad FB |
580 | break; |
581 | case RTC_REG_C: | |
582 | case RTC_REG_D: | |
583 | /* cannot write to them */ | |
584 | break; | |
585 | default: | |
586 | s->cmos_data[s->cmos_index] = data; | |
587 | break; | |
588 | } | |
589 | } | |
590 | } | |
591 | ||
abd0c6bd | 592 | static inline int rtc_to_bcd(RTCState *s, int a) |
80cabfad | 593 | { |
6f1bf24d | 594 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
595 | return a; |
596 | } else { | |
597 | return ((a / 10) << 4) | (a % 10); | |
598 | } | |
80cabfad FB |
599 | } |
600 | ||
abd0c6bd | 601 | static inline int rtc_from_bcd(RTCState *s, int a) |
80cabfad | 602 | { |
00cf5774 PB |
603 | if ((a & 0xc0) == 0xc0) { |
604 | return -1; | |
605 | } | |
6f1bf24d | 606 | if (s->cmos_data[RTC_REG_B] & REG_B_DM) { |
dff38e7b FB |
607 | return a; |
608 | } else { | |
609 | return ((a >> 4) * 10) + (a & 0x0f); | |
610 | } | |
611 | } | |
612 | ||
e2826cf4 | 613 | static void rtc_get_time(RTCState *s, struct tm *tm) |
dff38e7b | 614 | { |
abd0c6bd PB |
615 | tm->tm_sec = rtc_from_bcd(s, s->cmos_data[RTC_SECONDS]); |
616 | tm->tm_min = rtc_from_bcd(s, s->cmos_data[RTC_MINUTES]); | |
617 | tm->tm_hour = rtc_from_bcd(s, s->cmos_data[RTC_HOURS] & 0x7f); | |
3b89eb43 PB |
618 | if (!(s->cmos_data[RTC_REG_B] & REG_B_24H)) { |
619 | tm->tm_hour %= 12; | |
620 | if (s->cmos_data[RTC_HOURS] & 0x80) { | |
621 | tm->tm_hour += 12; | |
622 | } | |
43f493af | 623 | } |
abd0c6bd PB |
624 | tm->tm_wday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_WEEK]) - 1; |
625 | tm->tm_mday = rtc_from_bcd(s, s->cmos_data[RTC_DAY_OF_MONTH]); | |
626 | tm->tm_mon = rtc_from_bcd(s, s->cmos_data[RTC_MONTH]) - 1; | |
b8994faf PB |
627 | tm->tm_year = |
628 | rtc_from_bcd(s, s->cmos_data[RTC_YEAR]) + s->base_year + | |
629 | rtc_from_bcd(s, s->cmos_data[RTC_CENTURY]) * 100 - 1900; | |
e2826cf4 PB |
630 | } |
631 | ||
632 | static void rtc_set_time(RTCState *s) | |
633 | { | |
634 | struct tm tm; | |
80cd3478 | 635 | |
e2826cf4 | 636 | rtc_get_time(s, &tm); |
e2826cf4 | 637 | s->base_rtc = mktimegm(&tm); |
884f17c2 | 638 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 | 639 | |
3ab72385 | 640 | qapi_event_send_rtc_change(qemu_timedate_diff(&tm)); |
43f493af FB |
641 | } |
642 | ||
e2826cf4 | 643 | static void rtc_set_cmos(RTCState *s, const struct tm *tm) |
43f493af | 644 | { |
42fc73a1 | 645 | int year; |
dff38e7b | 646 | |
abd0c6bd PB |
647 | s->cmos_data[RTC_SECONDS] = rtc_to_bcd(s, tm->tm_sec); |
648 | s->cmos_data[RTC_MINUTES] = rtc_to_bcd(s, tm->tm_min); | |
c29cd656 | 649 | if (s->cmos_data[RTC_REG_B] & REG_B_24H) { |
43f493af | 650 | /* 24 hour format */ |
abd0c6bd | 651 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, tm->tm_hour); |
43f493af FB |
652 | } else { |
653 | /* 12 hour format */ | |
3b89eb43 PB |
654 | int h = (tm->tm_hour % 12) ? tm->tm_hour % 12 : 12; |
655 | s->cmos_data[RTC_HOURS] = rtc_to_bcd(s, h); | |
43f493af FB |
656 | if (tm->tm_hour >= 12) |
657 | s->cmos_data[RTC_HOURS] |= 0x80; | |
658 | } | |
abd0c6bd PB |
659 | s->cmos_data[RTC_DAY_OF_WEEK] = rtc_to_bcd(s, tm->tm_wday + 1); |
660 | s->cmos_data[RTC_DAY_OF_MONTH] = rtc_to_bcd(s, tm->tm_mday); | |
661 | s->cmos_data[RTC_MONTH] = rtc_to_bcd(s, tm->tm_mon + 1); | |
b8994faf PB |
662 | year = tm->tm_year + 1900 - s->base_year; |
663 | s->cmos_data[RTC_YEAR] = rtc_to_bcd(s, year % 100); | |
664 | s->cmos_data[RTC_CENTURY] = rtc_to_bcd(s, year / 100); | |
43f493af FB |
665 | } |
666 | ||
56038ef6 | 667 | static void rtc_update_time(RTCState *s) |
43f493af | 668 | { |
56038ef6 YZ |
669 | struct tm ret; |
670 | time_t guest_sec; | |
671 | int64_t guest_nsec; | |
672 | ||
673 | guest_nsec = get_guest_rtc_ns(s); | |
13566fe3 | 674 | guest_sec = guest_nsec / NANOSECONDS_PER_SECOND; |
56038ef6 | 675 | gmtime_r(&guest_sec, &ret); |
02c6ccc6 AH |
676 | |
677 | /* Is SET flag of Register B disabled? */ | |
678 | if ((s->cmos_data[RTC_REG_B] & REG_B_SET) == 0) { | |
679 | rtc_set_cmos(s, &ret); | |
680 | } | |
43f493af FB |
681 | } |
682 | ||
56038ef6 | 683 | static int update_in_progress(RTCState *s) |
43f493af | 684 | { |
56038ef6 | 685 | int64_t guest_nsec; |
3b46e624 | 686 | |
41a9b8b2 | 687 | if (!rtc_running(s)) { |
56038ef6 | 688 | return 0; |
dff38e7b | 689 | } |
e93379b0 AB |
690 | if (timer_pending(s->update_timer)) { |
691 | int64_t next_update_time = timer_expire_time_ns(s->update_timer); | |
56038ef6 | 692 | /* Latch UIP until the timer expires. */ |
884f17c2 AB |
693 | if (qemu_clock_get_ns(rtc_clock) >= |
694 | (next_update_time - UIP_HOLD_LENGTH)) { | |
56038ef6 YZ |
695 | s->cmos_data[RTC_REG_A] |= REG_A_UIP; |
696 | return 1; | |
dff38e7b FB |
697 | } |
698 | } | |
699 | ||
56038ef6 YZ |
700 | guest_nsec = get_guest_rtc_ns(s); |
701 | /* UIP bit will be set at last 244us of every second. */ | |
13566fe3 SH |
702 | if ((guest_nsec % NANOSECONDS_PER_SECOND) >= |
703 | (NANOSECONDS_PER_SECOND - UIP_HOLD_LENGTH)) { | |
56038ef6 | 704 | return 1; |
dff38e7b | 705 | } |
56038ef6 | 706 | return 0; |
80cabfad FB |
707 | } |
708 | ||
0da8c842 AG |
709 | static uint64_t cmos_ioport_read(void *opaque, hwaddr addr, |
710 | unsigned size) | |
80cabfad | 711 | { |
b41a2cd1 | 712 | RTCState *s = opaque; |
80cabfad FB |
713 | int ret; |
714 | if ((addr & 1) == 0) { | |
715 | return 0xff; | |
716 | } else { | |
717 | switch(s->cmos_index) { | |
7cd9681b | 718 | case RTC_IBM_PS2_CENTURY_BYTE: |
e67edb94 PB |
719 | s->cmos_index = RTC_CENTURY; |
720 | /* fall through */ | |
721 | case RTC_CENTURY: | |
80cabfad FB |
722 | case RTC_SECONDS: |
723 | case RTC_MINUTES: | |
724 | case RTC_HOURS: | |
725 | case RTC_DAY_OF_WEEK: | |
726 | case RTC_DAY_OF_MONTH: | |
727 | case RTC_MONTH: | |
728 | case RTC_YEAR: | |
56038ef6 YZ |
729 | /* if not in set mode, calibrate cmos before |
730 | * reading*/ | |
41a9b8b2 | 731 | if (rtc_running(s)) { |
56038ef6 YZ |
732 | rtc_update_time(s); |
733 | } | |
80cabfad FB |
734 | ret = s->cmos_data[s->cmos_index]; |
735 | break; | |
736 | case RTC_REG_A: | |
33f21e4f | 737 | ret = s->cmos_data[s->cmos_index]; |
56038ef6 | 738 | if (update_in_progress(s)) { |
33f21e4f | 739 | ret |= REG_A_UIP; |
56038ef6 | 740 | } |
80cabfad FB |
741 | break; |
742 | case RTC_REG_C: | |
743 | ret = s->cmos_data[s->cmos_index]; | |
d537cf6c | 744 | qemu_irq_lower(s->irq); |
fbc15e27 | 745 | s->cmos_data[RTC_REG_C] = 0x00; |
56038ef6 YZ |
746 | if (ret & (REG_C_UF | REG_C_AF)) { |
747 | check_update_timer(s); | |
748 | } | |
e0c8b950 | 749 | |
ba32edab | 750 | if(s->irq_coalesced && |
fbc15e27 | 751 | (s->cmos_data[RTC_REG_B] & REG_B_PIE) && |
ba32edab GN |
752 | s->irq_reinject_on_ack_count < RTC_REINJECT_ON_ACK_COUNT) { |
753 | s->irq_reinject_on_ack_count++; | |
fbc15e27 | 754 | s->cmos_data[RTC_REG_C] |= REG_C_IRQF | REG_C_PF; |
aa6f63ff | 755 | DPRINTF_C("cmos: injecting on ack\n"); |
e0c8b950 | 756 | if (rtc_policy_slew_deliver_irq(s)) { |
ba32edab | 757 | s->irq_coalesced--; |
aa6f63ff BS |
758 | DPRINTF_C("cmos: coalesced irqs decreased to %d\n", |
759 | s->irq_coalesced); | |
760 | } | |
ba32edab | 761 | } |
80cabfad FB |
762 | break; |
763 | default: | |
764 | ret = s->cmos_data[s->cmos_index]; | |
765 | break; | |
766 | } | |
ec51e364 IY |
767 | CMOS_DPRINTF("cmos: read index=0x%02x val=0x%02x\n", |
768 | s->cmos_index, ret); | |
80cabfad FB |
769 | return ret; |
770 | } | |
771 | } | |
772 | ||
1d914fa0 | 773 | void rtc_set_memory(ISADevice *dev, int addr, int val) |
dff38e7b | 774 | { |
0e41271e | 775 | RTCState *s = MC146818_RTC(dev); |
dff38e7b FB |
776 | if (addr >= 0 && addr <= 127) |
777 | s->cmos_data[addr] = val; | |
778 | } | |
779 | ||
b8b7456d IM |
780 | int rtc_get_memory(ISADevice *dev, int addr) |
781 | { | |
782 | RTCState *s = MC146818_RTC(dev); | |
783 | assert(addr >= 0 && addr <= 127); | |
784 | return s->cmos_data[addr]; | |
785 | } | |
786 | ||
1d914fa0 | 787 | static void rtc_set_date_from_host(ISADevice *dev) |
ea55ffb3 | 788 | { |
0e41271e | 789 | RTCState *s = MC146818_RTC(dev); |
f6503059 | 790 | struct tm tm; |
ea55ffb3 | 791 | |
f6503059 | 792 | qemu_get_timedate(&tm, 0); |
56038ef6 YZ |
793 | |
794 | s->base_rtc = mktimegm(&tm); | |
884f17c2 | 795 | s->last_update = qemu_clock_get_ns(rtc_clock); |
56038ef6 YZ |
796 | s->offset = 0; |
797 | ||
798 | /* set the CMOS date */ | |
e2826cf4 | 799 | rtc_set_cmos(s, &tm); |
ea55ffb3 TS |
800 | } |
801 | ||
44b1ff31 | 802 | static int rtc_pre_save(void *opaque) |
3cf294ee JB |
803 | { |
804 | RTCState *s = opaque; | |
805 | ||
806 | rtc_update_time(s); | |
44b1ff31 DDAG |
807 | |
808 | return 0; | |
3cf294ee JB |
809 | } |
810 | ||
6b075b8a | 811 | static int rtc_post_load(void *opaque, int version_id) |
80cabfad | 812 | { |
dff38e7b FB |
813 | RTCState *s = opaque; |
814 | ||
3cf294ee | 815 | if (version_id <= 2 || rtc_clock == QEMU_CLOCK_REALTIME) { |
56038ef6 YZ |
816 | rtc_set_time(s); |
817 | s->offset = 0; | |
818 | check_update_timer(s); | |
819 | } | |
820 | ||
1dfb1b2d PD |
821 | /* The periodic timer is deterministic in record/replay mode, |
822 | * so there is no need to update it after loading the vmstate. | |
823 | * Reading RTC here would misalign record and replay. | |
824 | */ | |
825 | if (replay_mode == REPLAY_MODE_NONE) { | |
826 | uint64_t now = qemu_clock_get_ns(rtc_clock); | |
827 | if (now < s->next_periodic_time || | |
828 | now > (s->next_periodic_time + get_max_clock_jump())) { | |
369b4135 | 829 | periodic_timer_update(s, qemu_clock_get_ns(rtc_clock), 0); |
1dfb1b2d | 830 | } |
ae46e239 PD |
831 | } |
832 | ||
048c74c4 | 833 | if (version_id >= 2) { |
104059da | 834 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
048c74c4 JQ |
835 | rtc_coalesced_timer_update(s); |
836 | } | |
048c74c4 | 837 | } |
73822ec8 AL |
838 | return 0; |
839 | } | |
73822ec8 | 840 | |
5cd8cada JQ |
841 | static bool rtc_irq_reinject_on_ack_count_needed(void *opaque) |
842 | { | |
843 | RTCState *s = (RTCState *)opaque; | |
844 | return s->irq_reinject_on_ack_count != 0; | |
845 | } | |
846 | ||
0b102153 | 847 | static const VMStateDescription vmstate_rtc_irq_reinject_on_ack_count = { |
bb426311 | 848 | .name = "mc146818rtc/irq_reinject_on_ack_count", |
0b102153 PD |
849 | .version_id = 1, |
850 | .minimum_version_id = 1, | |
5cd8cada | 851 | .needed = rtc_irq_reinject_on_ack_count_needed, |
0b102153 PD |
852 | .fields = (VMStateField[]) { |
853 | VMSTATE_UINT16(irq_reinject_on_ack_count, RTCState), | |
854 | VMSTATE_END_OF_LIST() | |
855 | } | |
856 | }; | |
857 | ||
6b075b8a JQ |
858 | static const VMStateDescription vmstate_rtc = { |
859 | .name = "mc146818rtc", | |
56038ef6 | 860 | .version_id = 3, |
6b075b8a | 861 | .minimum_version_id = 1, |
3cf294ee | 862 | .pre_save = rtc_pre_save, |
6b075b8a | 863 | .post_load = rtc_post_load, |
d49805ae | 864 | .fields = (VMStateField[]) { |
6b075b8a JQ |
865 | VMSTATE_BUFFER(cmos_data, RTCState), |
866 | VMSTATE_UINT8(cmos_index, RTCState), | |
89166459 | 867 | VMSTATE_UNUSED(7*4), |
e720677e | 868 | VMSTATE_TIMER_PTR(periodic_timer, RTCState), |
6b075b8a | 869 | VMSTATE_INT64(next_periodic_time, RTCState), |
56038ef6 | 870 | VMSTATE_UNUSED(3*8), |
6b075b8a JQ |
871 | VMSTATE_UINT32_V(irq_coalesced, RTCState, 2), |
872 | VMSTATE_UINT32_V(period, RTCState, 2), | |
56038ef6 YZ |
873 | VMSTATE_UINT64_V(base_rtc, RTCState, 3), |
874 | VMSTATE_UINT64_V(last_update, RTCState, 3), | |
875 | VMSTATE_INT64_V(offset, RTCState, 3), | |
e720677e | 876 | VMSTATE_TIMER_PTR_V(update_timer, RTCState, 3), |
00cf5774 | 877 | VMSTATE_UINT64_V(next_alarm_time, RTCState, 3), |
6b075b8a | 878 | VMSTATE_END_OF_LIST() |
0b102153 | 879 | }, |
5cd8cada JQ |
880 | .subsections = (const VMStateDescription*[]) { |
881 | &vmstate_rtc_irq_reinject_on_ack_count, | |
882 | NULL | |
6b075b8a JQ |
883 | } |
884 | }; | |
885 | ||
17604dac JK |
886 | static void rtc_notify_clock_reset(Notifier *notifier, void *data) |
887 | { | |
888 | RTCState *s = container_of(notifier, RTCState, clock_reset_notifier); | |
889 | int64_t now = *(int64_t *)data; | |
890 | ||
0e41271e | 891 | rtc_set_date_from_host(ISA_DEVICE(s)); |
369b4135 | 892 | periodic_timer_update(s, now, 0); |
56038ef6 | 893 | check_update_timer(s); |
388ad5d2 | 894 | |
104059da | 895 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
17604dac JK |
896 | rtc_coalesced_timer_update(s); |
897 | } | |
17604dac JK |
898 | } |
899 | ||
da98c8eb GH |
900 | /* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) |
901 | BIOS will read it and start S3 resume at POST Entry */ | |
902 | static void rtc_notify_suspend(Notifier *notifier, void *data) | |
903 | { | |
904 | RTCState *s = container_of(notifier, RTCState, suspend_notifier); | |
0e41271e | 905 | rtc_set_memory(ISA_DEVICE(s), 0xF, 0xFE); |
da98c8eb GH |
906 | } |
907 | ||
eeb7c03c GN |
908 | static void rtc_reset(void *opaque) |
909 | { | |
910 | RTCState *s = opaque; | |
911 | ||
72716184 AL |
912 | s->cmos_data[RTC_REG_B] &= ~(REG_B_PIE | REG_B_AIE | REG_B_SQWE); |
913 | s->cmos_data[RTC_REG_C] &= ~(REG_C_UF | REG_C_IRQF | REG_C_PF | REG_C_AF); | |
56038ef6 | 914 | check_update_timer(s); |
eeb7c03c | 915 | |
72716184 | 916 | qemu_irq_lower(s->irq); |
eeb7c03c | 917 | |
104059da | 918 | if (s->lost_tick_policy == LOST_TICK_POLICY_SLEW) { |
433acf0d | 919 | s->irq_coalesced = 0; |
7cd9681b | 920 | s->irq_reinject_on_ack_count = 0; |
433acf0d | 921 | } |
eeb7c03c GN |
922 | } |
923 | ||
b2c5009b | 924 | static const MemoryRegionOps cmos_ops = { |
0da8c842 AG |
925 | .read = cmos_ioport_read, |
926 | .write = cmos_ioport_write, | |
927 | .impl = { | |
928 | .min_access_size = 1, | |
929 | .max_access_size = 1, | |
930 | }, | |
931 | .endianness = DEVICE_LITTLE_ENDIAN, | |
b2c5009b RH |
932 | }; |
933 | ||
8e099d14 | 934 | static void rtc_get_date(Object *obj, struct tm *current_tm, Error **errp) |
18297050 | 935 | { |
0e41271e | 936 | RTCState *s = MC146818_RTC(obj); |
18297050 | 937 | |
56038ef6 | 938 | rtc_update_time(s); |
8e099d14 | 939 | rtc_get_time(s, current_tm); |
18297050 AL |
940 | } |
941 | ||
db895a1e | 942 | static void rtc_realizefn(DeviceState *dev, Error **errp) |
dff38e7b | 943 | { |
db895a1e | 944 | ISADevice *isadev = ISA_DEVICE(dev); |
0e41271e | 945 | RTCState *s = MC146818_RTC(dev); |
32e0c826 | 946 | int base = 0x70; |
80cabfad | 947 | |
80cabfad FB |
948 | s->cmos_data[RTC_REG_A] = 0x26; |
949 | s->cmos_data[RTC_REG_B] = 0x02; | |
950 | s->cmos_data[RTC_REG_C] = 0x00; | |
951 | s->cmos_data[RTC_REG_D] = 0x80; | |
952 | ||
b8994faf PB |
953 | /* This is for historical reasons. The default base year qdev property |
954 | * was set to 2000 for most machine types before the century byte was | |
955 | * implemented. | |
956 | * | |
957 | * This if statement means that the century byte will be always 0 | |
958 | * (at least until 2079...) for base_year = 1980, but will be set | |
959 | * correctly for base_year = 2000. | |
960 | */ | |
961 | if (s->base_year == 2000) { | |
962 | s->base_year = 0; | |
963 | } | |
964 | ||
db895a1e | 965 | rtc_set_date_from_host(isadev); |
ea55ffb3 | 966 | |
433acf0d | 967 | switch (s->lost_tick_policy) { |
4aa70a0e | 968 | #ifdef TARGET_I386 |
104059da | 969 | case LOST_TICK_POLICY_SLEW: |
6875204c | 970 | s->coalesced_timer = |
884f17c2 | 971 | timer_new_ns(rtc_clock, rtc_coalesced_timer, s); |
433acf0d | 972 | break; |
4aa70a0e | 973 | #endif |
104059da | 974 | case LOST_TICK_POLICY_DISCARD: |
433acf0d JK |
975 | break; |
976 | default: | |
db895a1e AF |
977 | error_setg(errp, "Invalid lost tick policy."); |
978 | return; | |
433acf0d | 979 | } |
433acf0d | 980 | |
884f17c2 AB |
981 | s->periodic_timer = timer_new_ns(rtc_clock, rtc_periodic_timer, s); |
982 | s->update_timer = timer_new_ns(rtc_clock, rtc_update_timer, s); | |
56038ef6 | 983 | check_update_timer(s); |
dff38e7b | 984 | |
17604dac | 985 | s->clock_reset_notifier.notify = rtc_notify_clock_reset; |
13c0cbae | 986 | qemu_clock_register_reset_notifier(rtc_clock, |
884f17c2 | 987 | &s->clock_reset_notifier); |
17604dac | 988 | |
da98c8eb GH |
989 | s->suspend_notifier.notify = rtc_notify_suspend; |
990 | qemu_register_suspend_notifier(&s->suspend_notifier); | |
991 | ||
853dca12 | 992 | memory_region_init_io(&s->io, OBJECT(s), &cmos_ops, s, "rtc", 2); |
db895a1e | 993 | isa_register_ioport(isadev, &s->io, base); |
dff38e7b | 994 | |
f98167ea PH |
995 | /* register rtc 0x70 port for coalesced_pio */ |
996 | memory_region_set_flush_coalesced(&s->io); | |
997 | memory_region_init_io(&s->coalesced_io, OBJECT(s), &cmos_ops, | |
998 | s, "rtc-index", 1); | |
999 | memory_region_add_subregion(&s->io, 0, &s->coalesced_io); | |
1000 | memory_region_add_coalescing(&s->coalesced_io, 0, 1); | |
1001 | ||
db895a1e | 1002 | qdev_set_legacy_instance_id(dev, base, 3); |
a08d4367 | 1003 | qemu_register_reset(rtc_reset, s); |
18297050 | 1004 | |
8e099d14 | 1005 | object_property_add_tm(OBJECT(s), "date", rtc_get_date, NULL); |
654a36d8 | 1006 | |
3638439d | 1007 | qdev_init_gpio_out(dev, &s->irq, 1); |
32e0c826 GH |
1008 | } |
1009 | ||
6c646a11 | 1010 | ISADevice *mc146818_rtc_init(ISABus *bus, int base_year, qemu_irq intercept_irq) |
32e0c826 | 1011 | { |
0e41271e AF |
1012 | DeviceState *dev; |
1013 | ISADevice *isadev; | |
7d932dfd | 1014 | RTCState *s; |
eeb7c03c | 1015 | |
0e41271e AF |
1016 | isadev = isa_create(bus, TYPE_MC146818_RTC); |
1017 | dev = DEVICE(isadev); | |
1018 | s = MC146818_RTC(isadev); | |
1019 | qdev_prop_set_int32(dev, "base_year", base_year); | |
1020 | qdev_init_nofail(dev); | |
7d932dfd | 1021 | if (intercept_irq) { |
3638439d | 1022 | qdev_connect_gpio_out(dev, 0, intercept_irq); |
7d932dfd | 1023 | } else { |
3638439d | 1024 | isa_connect_gpio_out(isadev, 0, RTC_ISA_IRQ); |
7d932dfd | 1025 | } |
f2ae8abf MT |
1026 | QLIST_INSERT_HEAD(&rtc_devices, s, link); |
1027 | ||
29551fdc TH |
1028 | object_property_add_alias(qdev_get_machine(), "rtc-time", OBJECT(s), |
1029 | "date", NULL); | |
1030 | ||
0e41271e | 1031 | return isadev; |
80cabfad FB |
1032 | } |
1033 | ||
39bffca2 AL |
1034 | static Property mc146818rtc_properties[] = { |
1035 | DEFINE_PROP_INT32("base_year", RTCState, base_year, 1980), | |
1036 | DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", RTCState, | |
104059da | 1037 | lost_tick_policy, LOST_TICK_POLICY_DISCARD), |
39bffca2 AL |
1038 | DEFINE_PROP_END_OF_LIST(), |
1039 | }; | |
1040 | ||
bf7bb91e | 1041 | static void rtc_resetdev(DeviceState *d) |
1042 | { | |
1043 | RTCState *s = MC146818_RTC(d); | |
1044 | ||
1045 | /* Reason: VM do suspend self will set 0xfe | |
1046 | * Reset any values other than 0xfe(Guest suspend case) */ | |
1047 | if (s->cmos_data[0x0f] != 0xfe) { | |
1048 | s->cmos_data[0x0f] = 0x00; | |
1049 | } | |
1050 | } | |
1051 | ||
8f04ee08 AL |
1052 | static void rtc_class_initfn(ObjectClass *klass, void *data) |
1053 | { | |
39bffca2 | 1054 | DeviceClass *dc = DEVICE_CLASS(klass); |
db895a1e AF |
1055 | |
1056 | dc->realize = rtc_realizefn; | |
bf7bb91e | 1057 | dc->reset = rtc_resetdev; |
39bffca2 AL |
1058 | dc->vmsd = &vmstate_rtc; |
1059 | dc->props = mc146818rtc_properties; | |
f3b17640 | 1060 | /* Reason: needs to be wired up by rtc_init() */ |
e90f2a8c | 1061 | dc->user_creatable = false; |
8f04ee08 AL |
1062 | } |
1063 | ||
8c43a6f0 | 1064 | static const TypeInfo mc146818rtc_info = { |
0e41271e | 1065 | .name = TYPE_MC146818_RTC, |
39bffca2 AL |
1066 | .parent = TYPE_ISA_DEVICE, |
1067 | .instance_size = sizeof(RTCState), | |
1068 | .class_init = rtc_class_initfn, | |
32e0c826 GH |
1069 | }; |
1070 | ||
83f7d43a | 1071 | static void mc146818rtc_register_types(void) |
100d9891 | 1072 | { |
39bffca2 | 1073 | type_register_static(&mc146818rtc_info); |
100d9891 | 1074 | } |
83f7d43a AF |
1075 | |
1076 | type_init(mc146818rtc_register_types) |