[mirror_qemu.git] / hw / timer / milkymist-sysctl.c

/*
 *  QEMU model of the Milkymist System Controller.
 *
 *  Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 *
 *
 * Specification available at:
 *   http://milkymist.walle.cc/socdoc/sysctl.pdf
 */

#include "qemu/osdep.h"
#include "hw/irq.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
#include "trace.h"
#include "qemu/timer.h"
#include "sysemu/runstate.h"
#include "hw/ptimer.h"
#include "hw/qdev-properties.h"
#include "qemu/error-report.h"
#include "qemu/module.h"
#include "qom/object.h"

enum {
    CTRL_ENABLE      = (1<<0),
    CTRL_AUTORESTART = (1<<1),
};

enum {
    ICAP_READY       = (1<<0),
};

enum {
    R_GPIO_IN         = 0,
    R_GPIO_OUT,
    R_GPIO_INTEN,
    R_TIMER0_CONTROL  = 4,
    R_TIMER0_COMPARE,
    R_TIMER0_COUNTER,
    R_TIMER1_CONTROL  = 8,
    R_TIMER1_COMPARE,
    R_TIMER1_COUNTER,
    R_ICAP = 16,
    R_DBG_SCRATCHPAD  = 20,
    R_DBG_WRITE_LOCK,
    R_CLK_FREQUENCY   = 29,
    R_CAPABILITIES,
    R_SYSTEM_ID,
    R_MAX
};

#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
typedef struct MilkymistSysctlState MilkymistSysctlState;
#define MILKYMIST_SYSCTL(obj) \
    OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)

struct MilkymistSysctlState {
    SysBusDevice parent_obj;

    MemoryRegion regs_region;

    ptimer_state *ptimer0;
    ptimer_state *ptimer1;

    uint32_t freq_hz;
    uint32_t capabilities;
    uint32_t systemid;
    uint32_t strappings;

    uint32_t regs[R_MAX];

    qemu_irq gpio_irq;
    qemu_irq timer0_irq;
    qemu_irq timer1_irq;
};

static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
{
    trace_milkymist_sysctl_icap_write(value);
    switch (value & 0xffff) {
    case 0x000e:
        qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
        break;
    }
}

static uint64_t sysctl_read(void *opaque, hwaddr addr,
                            unsigned size)
{
    MilkymistSysctlState *s = opaque;
    uint32_t r = 0;

    addr >>= 2;
    switch (addr) {
    case R_TIMER0_COUNTER:
        r = (uint32_t)ptimer_get_count(s->ptimer0);
        /* milkymist timer counts up */
        r = s->regs[R_TIMER0_COMPARE] - r;
        break;
    case R_TIMER1_COUNTER:
        r = (uint32_t)ptimer_get_count(s->ptimer1);
        /* milkymist timer counts up */
        r = s->regs[R_TIMER1_COMPARE] - r;
        break;
    case R_GPIO_IN:
    case R_GPIO_OUT:
    case R_GPIO_INTEN:
    case R_TIMER0_CONTROL:
    case R_TIMER0_COMPARE:
    case R_TIMER1_CONTROL:
    case R_TIMER1_COMPARE:
    case R_ICAP:
    case R_DBG_SCRATCHPAD:
    case R_DBG_WRITE_LOCK:
    case R_CLK_FREQUENCY:
    case R_CAPABILITIES:
    case R_SYSTEM_ID:
        r = s->regs[addr];
        break;

    default:
        error_report("milkymist_sysctl: read access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }

    trace_milkymist_sysctl_memory_read(addr << 2, r);

    return r;
}

static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
                         unsigned size)
{
    MilkymistSysctlState *s = opaque;

    trace_milkymist_sysctl_memory_write(addr, value);

    addr >>= 2;
    switch (addr) {
    case R_GPIO_OUT:
    case R_GPIO_INTEN:
    case R_TIMER0_COUNTER:
    case R_TIMER1_COUNTER:
    case R_DBG_SCRATCHPAD:
        s->regs[addr] = value;
        break;
    case R_TIMER0_COMPARE:
        ptimer_transaction_begin(s->ptimer0);
        ptimer_set_limit(s->ptimer0, value, 0);
        s->regs[addr] = value;
        ptimer_transaction_commit(s->ptimer0);
        break;
    case R_TIMER1_COMPARE:
        ptimer_transaction_begin(s->ptimer1);
        ptimer_set_limit(s->ptimer1, value, 0);
        s->regs[addr] = value;
        ptimer_transaction_commit(s->ptimer1);
        break;
    case R_TIMER0_CONTROL:
        ptimer_transaction_begin(s->ptimer0);
        s->regs[addr] = value;
        if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
            trace_milkymist_sysctl_start_timer0();
            ptimer_set_count(s->ptimer0,
                    s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
            ptimer_run(s->ptimer0, 0);
        } else {
            trace_milkymist_sysctl_stop_timer0();
            ptimer_stop(s->ptimer0);
        }
        ptimer_transaction_commit(s->ptimer0);
        break;
    case R_TIMER1_CONTROL:
        ptimer_transaction_begin(s->ptimer1);
        s->regs[addr] = value;
        if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
            trace_milkymist_sysctl_start_timer1();
            ptimer_set_count(s->ptimer1,
                    s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
            ptimer_run(s->ptimer1, 0);
        } else {
            trace_milkymist_sysctl_stop_timer1();
            ptimer_stop(s->ptimer1);
        }
        ptimer_transaction_commit(s->ptimer1);
        break;
    case R_ICAP:
        sysctl_icap_write(s, value);
        break;
    case R_DBG_WRITE_LOCK:
        s->regs[addr] = 1;
        break;
    case R_SYSTEM_ID:
        qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
        break;

    case R_GPIO_IN:
    case R_CLK_FREQUENCY:
    case R_CAPABILITIES:
        error_report("milkymist_sysctl: write to read-only register 0x"
                TARGET_FMT_plx, addr << 2);
        break;

    default:
        error_report("milkymist_sysctl: write access to unknown register 0x"
                TARGET_FMT_plx, addr << 2);
        break;
    }
}

static const MemoryRegionOps sysctl_mmio_ops = {
    .read = sysctl_read,
    .write = sysctl_write,
    .valid = {
        .min_access_size = 4,
        .max_access_size = 4,
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static void timer0_hit(void *opaque)
{
    MilkymistSysctlState *s = opaque;

    if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
        s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
        trace_milkymist_sysctl_stop_timer0();
        ptimer_stop(s->ptimer0);
    }

    trace_milkymist_sysctl_pulse_irq_timer0();
    qemu_irq_pulse(s->timer0_irq);
}

static void timer1_hit(void *opaque)
{
    MilkymistSysctlState *s = opaque;

    if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
        s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
        trace_milkymist_sysctl_stop_timer1();
        ptimer_stop(s->ptimer1);
    }

    trace_milkymist_sysctl_pulse_irq_timer1();
    qemu_irq_pulse(s->timer1_irq);
}

static void milkymist_sysctl_reset(DeviceState *d)
{
    MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
    int i;

    for (i = 0; i < R_MAX; i++) {
        s->regs[i] = 0;
    }

    ptimer_transaction_begin(s->ptimer0);
    ptimer_stop(s->ptimer0);
    ptimer_transaction_commit(s->ptimer0);
    ptimer_transaction_begin(s->ptimer1);
    ptimer_stop(s->ptimer1);
    ptimer_transaction_commit(s->ptimer1);

    /* defaults */
    s->regs[R_ICAP] = ICAP_READY;
    s->regs[R_SYSTEM_ID] = s->systemid;
    s->regs[R_CLK_FREQUENCY] = s->freq_hz;
    s->regs[R_CAPABILITIES] = s->capabilities;
    s->regs[R_GPIO_IN] = s->strappings;
}

static void milkymist_sysctl_init(Object *obj)
{
    MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
    SysBusDevice *dev = SYS_BUS_DEVICE(obj);

    sysbus_init_irq(dev, &s->gpio_irq);
    sysbus_init_irq(dev, &s->timer0_irq);
    sysbus_init_irq(dev, &s->timer1_irq);

    memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
            "milkymist-sysctl", R_MAX * 4);
    sysbus_init_mmio(dev, &s->regs_region);
}

static void milkymist_sysctl_realize(DeviceState *dev, Error **errp)
{
    MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);

    s->ptimer0 = ptimer_init(timer0_hit, s, PTIMER_POLICY_DEFAULT);
    s->ptimer1 = ptimer_init(timer1_hit, s, PTIMER_POLICY_DEFAULT);

    ptimer_transaction_begin(s->ptimer0);
    ptimer_set_freq(s->ptimer0, s->freq_hz);
    ptimer_transaction_commit(s->ptimer0);
    ptimer_transaction_begin(s->ptimer1);
    ptimer_set_freq(s->ptimer1, s->freq_hz);
    ptimer_transaction_commit(s->ptimer1);
}

static const VMStateDescription vmstate_milkymist_sysctl = {
    .name = "milkymist-sysctl",
    .version_id = 1,
    .minimum_version_id = 1,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
        VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
        VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
        VMSTATE_END_OF_LIST()
    }
};

static Property milkymist_sysctl_properties[] = {
    DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
    freq_hz, 80000000),
    DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
    capabilities, 0x00000000),
    DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
    systemid, 0x10014d31),
    DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
    strappings, 0x00000001),
    DEFINE_PROP_END_OF_LIST(),
};

static void milkymist_sysctl_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = milkymist_sysctl_realize;
    dc->reset = milkymist_sysctl_reset;
    dc->vmsd = &vmstate_milkymist_sysctl;
    device_class_set_props(dc, milkymist_sysctl_properties);
}

static const TypeInfo milkymist_sysctl_info = {
    .name          = TYPE_MILKYMIST_SYSCTL,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(MilkymistSysctlState),
    .instance_init = milkymist_sysctl_init,
    .class_init    = milkymist_sysctl_class_init,
};

static void milkymist_sysctl_register_types(void)
{
    type_register_static(&milkymist_sysctl_info);
}

type_init(milkymist_sysctl_register_types)
Commit	Line	Data
96832424 MW	1	/*
	2	* QEMU model of the Milkymist System Controller.
	3	*
060544d3	4	* Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
96832424 MW	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*
	19	*
	20	* Specification available at:
6dbbe243	21	* http://milkymist.walle.cc/socdoc/sysctl.pdf
96832424 MW	22	*/
96832424 MW	23
ea99dde1	24	#include "qemu/osdep.h"
64552b6b	25	#include "hw/irq.h"
83c9f4ca	26	#include "hw/sysbus.h"
d6454270	27	#include "migration/vmstate.h"
96832424	28	#include "trace.h"
1de7afc9	29	#include "qemu/timer.h"
54d31236	30	#include "sysemu/runstate.h"
83c9f4ca	31	#include "hw/ptimer.h"
a27bd6c7	32	#include "hw/qdev-properties.h"
1de7afc9	33	#include "qemu/error-report.h"
0b8fa32f	34	#include "qemu/module.h"
db1015e9	35	#include "qom/object.h"
96832424 MW	36
	37	enum {
	38	CTRL_ENABLE = (1<<0),
	39	CTRL_AUTORESTART = (1<<1),
	40	};
	41
	42	enum {
	43	ICAP_READY = (1<<0),
	44	};
	45
	46	enum {
060544d3	47	R_GPIO_IN = 0,
96832424 MW	48	R_GPIO_OUT,
96832424 MW	49	R_GPIO_INTEN,
060544d3	50	R_TIMER0_CONTROL = 4,
96832424 MW	51	R_TIMER0_COMPARE,
96832424 MW	52	R_TIMER0_COUNTER,
060544d3	53	R_TIMER1_CONTROL = 8,
96832424 MW	54	R_TIMER1_COMPARE,
96832424 MW	55	R_TIMER1_COUNTER,
060544d3 MW	56	R_ICAP = 16,
	57	R_DBG_SCRATCHPAD = 20,
	58	R_DBG_WRITE_LOCK,
	59	R_CLK_FREQUENCY = 29,
96832424 MW	60	R_CAPABILITIES,
	61	R_SYSTEM_ID,
	62	R_MAX
	63	};
	64
b564b137	65	#define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
db1015e9	66	typedef struct MilkymistSysctlState MilkymistSysctlState;
b564b137 AF	67	#define MILKYMIST_SYSCTL(obj) \
	68	OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
	69
96832424	70	struct MilkymistSysctlState {
b564b137 AF	71	SysBusDevice parent_obj;
b564b137 AF	72
dfa87ccf	73	MemoryRegion regs_region;
96832424	74
96832424 MW	75	ptimer_state *ptimer0;
	76	ptimer_state *ptimer1;
	77
	78	uint32_t freq_hz;
	79	uint32_t capabilities;
	80	uint32_t systemid;
	81	uint32_t strappings;
	82
	83	uint32_t regs[R_MAX];
	84
	85	qemu_irq gpio_irq;
	86	qemu_irq timer0_irq;
	87	qemu_irq timer1_irq;
	88	};
96832424 MW	89
	90	static void sysctl_icap_write(MilkymistSysctlState *s, uint32_t value)
	91	{
	92	trace_milkymist_sysctl_icap_write(value);
	93	switch (value & 0xffff) {
	94	case 0x000e:
cf83f140	95	qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
96832424 MW	96	break;
	97	}
	98	}
	99
a8170e5e	100	static uint64_t sysctl_read(void *opaque, hwaddr addr,
dfa87ccf	101	unsigned size)
96832424 MW	102	{
	103	MilkymistSysctlState *s = opaque;
	104	uint32_t r = 0;
	105
	106	addr >>= 2;
	107	switch (addr) {
	108	case R_TIMER0_COUNTER:
	109	r = (uint32_t)ptimer_get_count(s->ptimer0);
	110	/* milkymist timer counts up */
	111	r = s->regs[R_TIMER0_COMPARE] - r;
	112	break;
	113	case R_TIMER1_COUNTER:
	114	r = (uint32_t)ptimer_get_count(s->ptimer1);
	115	/* milkymist timer counts up */
	116	r = s->regs[R_TIMER1_COMPARE] - r;
	117	break;
	118	case R_GPIO_IN:
	119	case R_GPIO_OUT:
	120	case R_GPIO_INTEN:
	121	case R_TIMER0_CONTROL:
	122	case R_TIMER0_COMPARE:
	123	case R_TIMER1_CONTROL:
	124	case R_TIMER1_COMPARE:
	125	case R_ICAP:
060544d3 MW	126	case R_DBG_SCRATCHPAD:
	127	case R_DBG_WRITE_LOCK:
	128	case R_CLK_FREQUENCY:
96832424 MW	129	case R_CAPABILITIES:
	130	case R_SYSTEM_ID:
	131	r = s->regs[addr];
	132	break;
	133
	134	default:
dd3d6775	135	error_report("milkymist_sysctl: read access to unknown register 0x"
96832424 MW	136	TARGET_FMT_plx, addr << 2);
	137	break;
	138	}
	139
	140	trace_milkymist_sysctl_memory_read(addr << 2, r);
	141
	142	return r;
	143	}
	144
a8170e5e	145	static void sysctl_write(void *opaque, hwaddr addr, uint64_t value,
dfa87ccf	146	unsigned size)
96832424 MW	147	{
	148	MilkymistSysctlState *s = opaque;
	149
	150	trace_milkymist_sysctl_memory_write(addr, value);
	151
	152	addr >>= 2;
	153	switch (addr) {
	154	case R_GPIO_OUT:
	155	case R_GPIO_INTEN:
	156	case R_TIMER0_COUNTER:
96832424	157	case R_TIMER1_COUNTER:
060544d3	158	case R_DBG_SCRATCHPAD:
f3172a0e	159	s->regs[addr] = value;
96832424 MW	160	break;
96832424 MW	161	case R_TIMER0_COMPARE:
98a44c16	162	ptimer_transaction_begin(s->ptimer0);
96832424 MW	163	ptimer_set_limit(s->ptimer0, value, 0);
96832424 MW	164	s->regs[addr] = value;
98a44c16	165	ptimer_transaction_commit(s->ptimer0);
96832424 MW	166	break;
96832424 MW	167	case R_TIMER1_COMPARE:
98a44c16	168	ptimer_transaction_begin(s->ptimer1);
96832424 MW	169	ptimer_set_limit(s->ptimer1, value, 0);
96832424 MW	170	s->regs[addr] = value;
98a44c16	171	ptimer_transaction_commit(s->ptimer1);
96832424 MW	172	break;
96832424 MW	173	case R_TIMER0_CONTROL:
98a44c16	174	ptimer_transaction_begin(s->ptimer0);
96832424 MW	175	s->regs[addr] = value;
96832424 MW	176	if (s->regs[R_TIMER0_CONTROL] & CTRL_ENABLE) {
f3172a0e MW	177	trace_milkymist_sysctl_start_timer0();
	178	ptimer_set_count(s->ptimer0,
	179	s->regs[R_TIMER0_COMPARE] - s->regs[R_TIMER0_COUNTER]);
96832424 MW	180	ptimer_run(s->ptimer0, 0);
96832424 MW	181	} else {
f3172a0e	182	trace_milkymist_sysctl_stop_timer0();
96832424 MW	183	ptimer_stop(s->ptimer0);
96832424 MW	184	}
98a44c16	185	ptimer_transaction_commit(s->ptimer0);
96832424 MW	186	break;
96832424 MW	187	case R_TIMER1_CONTROL:
98a44c16	188	ptimer_transaction_begin(s->ptimer1);
96832424 MW	189	s->regs[addr] = value;
	190	if (s->regs[R_TIMER1_CONTROL] & CTRL_ENABLE) {
	191	trace_milkymist_sysctl_start_timer1();
f3172a0e MW	192	ptimer_set_count(s->ptimer1,
f3172a0e MW	193	s->regs[R_TIMER1_COMPARE] - s->regs[R_TIMER1_COUNTER]);
96832424 MW	194	ptimer_run(s->ptimer1, 0);
	195	} else {
	196	trace_milkymist_sysctl_stop_timer1();
	197	ptimer_stop(s->ptimer1);
	198	}
98a44c16	199	ptimer_transaction_commit(s->ptimer1);
96832424 MW	200	break;
	201	case R_ICAP:
	202	sysctl_icap_write(s, value);
	203	break;
060544d3 MW	204	case R_DBG_WRITE_LOCK:
	205	s->regs[addr] = 1;
	206	break;
96832424	207	case R_SYSTEM_ID:
cf83f140	208	qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
96832424 MW	209	break;
	210
	211	case R_GPIO_IN:
060544d3	212	case R_CLK_FREQUENCY:
96832424 MW	213	case R_CAPABILITIES:
	214	error_report("milkymist_sysctl: write to read-only register 0x"
	215	TARGET_FMT_plx, addr << 2);
	216	break;
	217
	218	default:
dd3d6775	219	error_report("milkymist_sysctl: write access to unknown register 0x"
96832424 MW	220	TARGET_FMT_plx, addr << 2);
	221	break;
	222	}
	223	}
	224
dfa87ccf MW	225	static const MemoryRegionOps sysctl_mmio_ops = {
	226	.read = sysctl_read,
	227	.write = sysctl_write,
	228	.valid = {
	229	.min_access_size = 4,
	230	.max_access_size = 4,
	231	},
	232	.endianness = DEVICE_NATIVE_ENDIAN,
96832424 MW	233	};
	234
	235	static void timer0_hit(void *opaque)
	236	{
	237	MilkymistSysctlState *s = opaque;
	238
	239	if (!(s->regs[R_TIMER0_CONTROL] & CTRL_AUTORESTART)) {
	240	s->regs[R_TIMER0_CONTROL] &= ~CTRL_ENABLE;
	241	trace_milkymist_sysctl_stop_timer0();
	242	ptimer_stop(s->ptimer0);
	243	}
	244
	245	trace_milkymist_sysctl_pulse_irq_timer0();
	246	qemu_irq_pulse(s->timer0_irq);
	247	}
	248
	249	static void timer1_hit(void *opaque)
	250	{
	251	MilkymistSysctlState *s = opaque;
	252
	253	if (!(s->regs[R_TIMER1_CONTROL] & CTRL_AUTORESTART)) {
	254	s->regs[R_TIMER1_CONTROL] &= ~CTRL_ENABLE;
	255	trace_milkymist_sysctl_stop_timer1();
	256	ptimer_stop(s->ptimer1);
	257	}
	258
	259	trace_milkymist_sysctl_pulse_irq_timer1();
	260	qemu_irq_pulse(s->timer1_irq);
	261	}
	262
	263	static void milkymist_sysctl_reset(DeviceState *d)
	264	{
b564b137	265	MilkymistSysctlState *s = MILKYMIST_SYSCTL(d);
96832424 MW	266	int i;
	267
	268	for (i = 0; i < R_MAX; i++) {
	269	s->regs[i] = 0;
	270	}
	271
98a44c16	272	ptimer_transaction_begin(s->ptimer0);
96832424	273	ptimer_stop(s->ptimer0);
98a44c16 PM	274	ptimer_transaction_commit(s->ptimer0);
98a44c16 PM	275	ptimer_transaction_begin(s->ptimer1);
96832424	276	ptimer_stop(s->ptimer1);
98a44c16	277	ptimer_transaction_commit(s->ptimer1);
96832424 MW	278
	279	/* defaults */
	280	s->regs[R_ICAP] = ICAP_READY;
	281	s->regs[R_SYSTEM_ID] = s->systemid;
060544d3	282	s->regs[R_CLK_FREQUENCY] = s->freq_hz;
96832424 MW	283	s->regs[R_CAPABILITIES] = s->capabilities;
	284	s->regs[R_GPIO_IN] = s->strappings;
	285	}
	286
596ca933	287	static void milkymist_sysctl_init(Object *obj)
96832424	288	{
596ca933 XZ	289	MilkymistSysctlState *s = MILKYMIST_SYSCTL(obj);
596ca933 XZ	290	SysBusDevice *dev = SYS_BUS_DEVICE(obj);
96832424 MW	291
	292	sysbus_init_irq(dev, &s->gpio_irq);
	293	sysbus_init_irq(dev, &s->timer0_irq);
	294	sysbus_init_irq(dev, &s->timer1_irq);
	295
596ca933	296	memory_region_init_io(&s->regs_region, obj, &sysctl_mmio_ops, s,
dfa87ccf	297	"milkymist-sysctl", R_MAX * 4);
750ecd44	298	sysbus_init_mmio(dev, &s->regs_region);
596ca933	299	}
96832424	300
596ca933 XZ	301	static void milkymist_sysctl_realize(DeviceState dev, Error *errp)
	302	{
	303	MilkymistSysctlState *s = MILKYMIST_SYSCTL(dev);
	304
98a44c16 PM	305	s->ptimer0 = ptimer_init(timer0_hit, s, PTIMER_POLICY_DEFAULT);
98a44c16 PM	306	s->ptimer1 = ptimer_init(timer1_hit, s, PTIMER_POLICY_DEFAULT);
e97dd6b2	307
98a44c16	308	ptimer_transaction_begin(s->ptimer0);
596ca933	309	ptimer_set_freq(s->ptimer0, s->freq_hz);
98a44c16 PM	310	ptimer_transaction_commit(s->ptimer0);
98a44c16 PM	311	ptimer_transaction_begin(s->ptimer1);
596ca933	312	ptimer_set_freq(s->ptimer1, s->freq_hz);
98a44c16	313	ptimer_transaction_commit(s->ptimer1);
96832424 MW	314	}
	315
	316	static const VMStateDescription vmstate_milkymist_sysctl = {
	317	.name = "milkymist-sysctl",
	318	.version_id = 1,
	319	.minimum_version_id = 1,
35d08458	320	.fields = (VMStateField[]) {
96832424 MW	321	VMSTATE_UINT32_ARRAY(regs, MilkymistSysctlState, R_MAX),
	322	VMSTATE_PTIMER(ptimer0, MilkymistSysctlState),
	323	VMSTATE_PTIMER(ptimer1, MilkymistSysctlState),
	324	VMSTATE_END_OF_LIST()
	325	}
	326	};
	327
999e12bb AL	328	static Property milkymist_sysctl_properties[] = {
	329	DEFINE_PROP_UINT32("frequency", MilkymistSysctlState,
	330	freq_hz, 80000000),
	331	DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState,
	332	capabilities, 0x00000000),
	333	DEFINE_PROP_UINT32("systemid", MilkymistSysctlState,
	334	systemid, 0x10014d31),
	335	DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState,
	336	strappings, 0x00000001),
	337	DEFINE_PROP_END_OF_LIST(),
	338	};
	339
	340	static void milkymist_sysctl_class_init(ObjectClass klass, void data)
	341	{
39bffca2	342	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	343
596ca933	344	dc->realize = milkymist_sysctl_realize;
39bffca2 AL	345	dc->reset = milkymist_sysctl_reset;
39bffca2 AL	346	dc->vmsd = &vmstate_milkymist_sysctl;
4f67d30b	347	device_class_set_props(dc, milkymist_sysctl_properties);
999e12bb AL	348	}
999e12bb AL	349
8c43a6f0	350	static const TypeInfo milkymist_sysctl_info = {
b564b137	351	.name = TYPE_MILKYMIST_SYSCTL,
39bffca2 AL	352	.parent = TYPE_SYS_BUS_DEVICE,
39bffca2 AL	353	.instance_size = sizeof(MilkymistSysctlState),
596ca933	354	.instance_init = milkymist_sysctl_init,
39bffca2	355	.class_init = milkymist_sysctl_class_init,
96832424 MW	356	};
96832424 MW	357
83f7d43a	358	static void milkymist_sysctl_register_types(void)
96832424	359	{
39bffca2	360	type_register_static(&milkymist_sysctl_info);
96832424 MW	361	}
96832424 MW	362
83f7d43a	363	type_init(milkymist_sysctl_register_types)