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96401bad SS |
1 | /* |
2 | * Block model of System timer present in | |
3 | * Microsemi's SmartFusion2 and SmartFusion SoCs. | |
4 | * | |
5 | * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include "qemu/osdep.h" | |
0b8fa32f | 27 | #include "qemu/module.h" |
96401bad | 28 | #include "qemu/log.h" |
64552b6b | 29 | #include "hw/irq.h" |
a27bd6c7 | 30 | #include "hw/qdev-properties.h" |
96401bad | 31 | #include "hw/timer/mss-timer.h" |
d6454270 | 32 | #include "migration/vmstate.h" |
96401bad SS |
33 | |
34 | #ifndef MSS_TIMER_ERR_DEBUG | |
35 | #define MSS_TIMER_ERR_DEBUG 0 | |
36 | #endif | |
37 | ||
38 | #define DB_PRINT_L(lvl, fmt, args...) do { \ | |
39 | if (MSS_TIMER_ERR_DEBUG >= lvl) { \ | |
40 | qemu_log("%s: " fmt "\n", __func__, ## args); \ | |
41 | } \ | |
2562755e | 42 | } while (0) |
96401bad SS |
43 | |
44 | #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) | |
45 | ||
46 | #define R_TIM_VAL 0 | |
47 | #define R_TIM_LOADVAL 1 | |
48 | #define R_TIM_BGLOADVAL 2 | |
49 | #define R_TIM_CTRL 3 | |
50 | #define R_TIM_RIS 4 | |
51 | #define R_TIM_MIS 5 | |
52 | ||
53 | #define TIMER_CTRL_ENBL (1 << 0) | |
54 | #define TIMER_CTRL_ONESHOT (1 << 1) | |
55 | #define TIMER_CTRL_INTR (1 << 2) | |
56 | #define TIMER_RIS_ACK (1 << 0) | |
57 | #define TIMER_RST_CLR (1 << 6) | |
58 | #define TIMER_MODE (1 << 0) | |
59 | ||
60 | static void timer_update_irq(struct Msf2Timer *st) | |
61 | { | |
62 | bool isr, ier; | |
63 | ||
64 | isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); | |
65 | ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); | |
66 | qemu_set_irq(st->irq, (ier && isr)); | |
67 | } | |
68 | ||
00ee4b0f | 69 | /* Must be called from within a ptimer_transaction_begin/commit block */ |
96401bad SS |
70 | static void timer_update(struct Msf2Timer *st) |
71 | { | |
72 | uint64_t count; | |
73 | ||
74 | if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { | |
75 | ptimer_stop(st->ptimer); | |
76 | return; | |
77 | } | |
78 | ||
79 | count = st->regs[R_TIM_LOADVAL]; | |
80 | ptimer_set_limit(st->ptimer, count, 1); | |
81 | ptimer_run(st->ptimer, 1); | |
82 | } | |
83 | ||
84 | static uint64_t | |
85 | timer_read(void *opaque, hwaddr offset, unsigned int size) | |
86 | { | |
87 | MSSTimerState *t = opaque; | |
88 | hwaddr addr; | |
89 | struct Msf2Timer *st; | |
90 | uint32_t ret = 0; | |
91 | int timer = 0; | |
92 | int isr; | |
93 | int ier; | |
94 | ||
95 | addr = offset >> 2; | |
96 | /* | |
97 | * Two independent timers has same base address. | |
98 | * Based on address passed figure out which timer is being used. | |
99 | */ | |
100 | if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { | |
101 | timer = 1; | |
102 | addr -= R_TIM1_MAX; | |
103 | } | |
104 | ||
105 | st = &t->timers[timer]; | |
106 | ||
107 | switch (addr) { | |
108 | case R_TIM_VAL: | |
109 | ret = ptimer_get_count(st->ptimer); | |
110 | break; | |
111 | ||
112 | case R_TIM_MIS: | |
113 | isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); | |
114 | ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); | |
115 | ret = ier & isr; | |
116 | break; | |
117 | ||
118 | default: | |
119 | if (addr < R_TIM1_MAX) { | |
120 | ret = st->regs[addr]; | |
121 | } else { | |
122 | qemu_log_mask(LOG_GUEST_ERROR, | |
123 | TYPE_MSS_TIMER": 64-bit mode not supported\n"); | |
124 | return ret; | |
125 | } | |
126 | break; | |
127 | } | |
128 | ||
129 | DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, | |
130 | ret); | |
131 | return ret; | |
132 | } | |
133 | ||
134 | static void | |
135 | timer_write(void *opaque, hwaddr offset, | |
136 | uint64_t val64, unsigned int size) | |
137 | { | |
138 | MSSTimerState *t = opaque; | |
139 | hwaddr addr; | |
140 | struct Msf2Timer *st; | |
141 | int timer = 0; | |
142 | uint32_t value = val64; | |
143 | ||
144 | addr = offset >> 2; | |
145 | /* | |
146 | * Two independent timers has same base address. | |
147 | * Based on addr passed figure out which timer is being used. | |
148 | */ | |
149 | if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { | |
150 | timer = 1; | |
151 | addr -= R_TIM1_MAX; | |
152 | } | |
153 | ||
154 | st = &t->timers[timer]; | |
155 | ||
156 | DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset, | |
157 | value, timer); | |
158 | ||
159 | switch (addr) { | |
160 | case R_TIM_CTRL: | |
161 | st->regs[R_TIM_CTRL] = value; | |
00ee4b0f | 162 | ptimer_transaction_begin(st->ptimer); |
96401bad | 163 | timer_update(st); |
00ee4b0f | 164 | ptimer_transaction_commit(st->ptimer); |
96401bad SS |
165 | break; |
166 | ||
167 | case R_TIM_RIS: | |
168 | if (value & TIMER_RIS_ACK) { | |
169 | st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; | |
170 | } | |
171 | break; | |
172 | ||
173 | case R_TIM_LOADVAL: | |
174 | st->regs[R_TIM_LOADVAL] = value; | |
175 | if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { | |
00ee4b0f | 176 | ptimer_transaction_begin(st->ptimer); |
96401bad | 177 | timer_update(st); |
00ee4b0f | 178 | ptimer_transaction_commit(st->ptimer); |
96401bad SS |
179 | } |
180 | break; | |
181 | ||
182 | case R_TIM_BGLOADVAL: | |
183 | st->regs[R_TIM_BGLOADVAL] = value; | |
184 | st->regs[R_TIM_LOADVAL] = value; | |
185 | break; | |
186 | ||
187 | case R_TIM_VAL: | |
188 | case R_TIM_MIS: | |
189 | break; | |
190 | ||
191 | default: | |
192 | if (addr < R_TIM1_MAX) { | |
193 | st->regs[addr] = value; | |
194 | } else { | |
195 | qemu_log_mask(LOG_GUEST_ERROR, | |
196 | TYPE_MSS_TIMER": 64-bit mode not supported\n"); | |
197 | return; | |
198 | } | |
199 | break; | |
200 | } | |
201 | timer_update_irq(st); | |
202 | } | |
203 | ||
204 | static const MemoryRegionOps timer_ops = { | |
205 | .read = timer_read, | |
206 | .write = timer_write, | |
207 | .endianness = DEVICE_NATIVE_ENDIAN, | |
208 | .valid = { | |
209 | .min_access_size = 1, | |
210 | .max_access_size = 4 | |
211 | } | |
212 | }; | |
213 | ||
214 | static void timer_hit(void *opaque) | |
215 | { | |
216 | struct Msf2Timer *st = opaque; | |
217 | ||
218 | st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; | |
219 | ||
220 | if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { | |
221 | timer_update(st); | |
222 | } | |
223 | timer_update_irq(st); | |
224 | } | |
225 | ||
226 | static void mss_timer_init(Object *obj) | |
227 | { | |
228 | MSSTimerState *t = MSS_TIMER(obj); | |
229 | int i; | |
230 | ||
231 | /* Init all the ptimers. */ | |
232 | for (i = 0; i < NUM_TIMERS; i++) { | |
233 | struct Msf2Timer *st = &t->timers[i]; | |
234 | ||
00ee4b0f PM |
235 | st->ptimer = ptimer_init(timer_hit, st, PTIMER_POLICY_DEFAULT); |
236 | ptimer_transaction_begin(st->ptimer); | |
96401bad | 237 | ptimer_set_freq(st->ptimer, t->freq_hz); |
00ee4b0f | 238 | ptimer_transaction_commit(st->ptimer); |
96401bad SS |
239 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); |
240 | } | |
241 | ||
242 | memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER, | |
243 | NUM_TIMERS * R_TIM1_MAX * 4); | |
244 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); | |
245 | } | |
246 | ||
247 | static const VMStateDescription vmstate_timers = { | |
248 | .name = "mss-timer-block", | |
249 | .version_id = 1, | |
250 | .minimum_version_id = 1, | |
251 | .fields = (VMStateField[]) { | |
252 | VMSTATE_PTIMER(ptimer, struct Msf2Timer), | |
253 | VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), | |
254 | VMSTATE_END_OF_LIST() | |
255 | } | |
256 | }; | |
257 | ||
258 | static const VMStateDescription vmstate_mss_timer = { | |
259 | .name = TYPE_MSS_TIMER, | |
260 | .version_id = 1, | |
261 | .minimum_version_id = 1, | |
262 | .fields = (VMStateField[]) { | |
263 | VMSTATE_UINT32(freq_hz, MSSTimerState), | |
264 | VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, | |
265 | vmstate_timers, struct Msf2Timer), | |
266 | VMSTATE_END_OF_LIST() | |
267 | } | |
268 | }; | |
269 | ||
270 | static Property mss_timer_properties[] = { | |
271 | /* Libero GUI shows 100Mhz as default for clocks */ | |
272 | DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, | |
273 | 100 * 1000000), | |
274 | DEFINE_PROP_END_OF_LIST(), | |
275 | }; | |
276 | ||
277 | static void mss_timer_class_init(ObjectClass *klass, void *data) | |
278 | { | |
279 | DeviceClass *dc = DEVICE_CLASS(klass); | |
280 | ||
4f67d30b | 281 | device_class_set_props(dc, mss_timer_properties); |
96401bad SS |
282 | dc->vmsd = &vmstate_mss_timer; |
283 | } | |
284 | ||
285 | static const TypeInfo mss_timer_info = { | |
286 | .name = TYPE_MSS_TIMER, | |
287 | .parent = TYPE_SYS_BUS_DEVICE, | |
288 | .instance_size = sizeof(MSSTimerState), | |
289 | .instance_init = mss_timer_init, | |
290 | .class_init = mss_timer_class_init, | |
291 | }; | |
292 | ||
293 | static void mss_timer_register_types(void) | |
294 | { | |
295 | type_register_static(&mss_timer_info); | |
296 | } | |
297 | ||
298 | type_init(mss_timer_register_types) |