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96401bad SS |
1 | /* |
2 | * Block model of System timer present in | |
3 | * Microsemi's SmartFusion2 and SmartFusion SoCs. | |
4 | * | |
5 | * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
25 | ||
26 | #include "qemu/osdep.h" | |
27 | #include "qemu/main-loop.h" | |
0b8fa32f | 28 | #include "qemu/module.h" |
96401bad SS |
29 | #include "qemu/log.h" |
30 | #include "hw/timer/mss-timer.h" | |
31 | ||
32 | #ifndef MSS_TIMER_ERR_DEBUG | |
33 | #define MSS_TIMER_ERR_DEBUG 0 | |
34 | #endif | |
35 | ||
36 | #define DB_PRINT_L(lvl, fmt, args...) do { \ | |
37 | if (MSS_TIMER_ERR_DEBUG >= lvl) { \ | |
38 | qemu_log("%s: " fmt "\n", __func__, ## args); \ | |
39 | } \ | |
2562755e | 40 | } while (0) |
96401bad SS |
41 | |
42 | #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) | |
43 | ||
44 | #define R_TIM_VAL 0 | |
45 | #define R_TIM_LOADVAL 1 | |
46 | #define R_TIM_BGLOADVAL 2 | |
47 | #define R_TIM_CTRL 3 | |
48 | #define R_TIM_RIS 4 | |
49 | #define R_TIM_MIS 5 | |
50 | ||
51 | #define TIMER_CTRL_ENBL (1 << 0) | |
52 | #define TIMER_CTRL_ONESHOT (1 << 1) | |
53 | #define TIMER_CTRL_INTR (1 << 2) | |
54 | #define TIMER_RIS_ACK (1 << 0) | |
55 | #define TIMER_RST_CLR (1 << 6) | |
56 | #define TIMER_MODE (1 << 0) | |
57 | ||
58 | static void timer_update_irq(struct Msf2Timer *st) | |
59 | { | |
60 | bool isr, ier; | |
61 | ||
62 | isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); | |
63 | ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); | |
64 | qemu_set_irq(st->irq, (ier && isr)); | |
65 | } | |
66 | ||
67 | static void timer_update(struct Msf2Timer *st) | |
68 | { | |
69 | uint64_t count; | |
70 | ||
71 | if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL)) { | |
72 | ptimer_stop(st->ptimer); | |
73 | return; | |
74 | } | |
75 | ||
76 | count = st->regs[R_TIM_LOADVAL]; | |
77 | ptimer_set_limit(st->ptimer, count, 1); | |
78 | ptimer_run(st->ptimer, 1); | |
79 | } | |
80 | ||
81 | static uint64_t | |
82 | timer_read(void *opaque, hwaddr offset, unsigned int size) | |
83 | { | |
84 | MSSTimerState *t = opaque; | |
85 | hwaddr addr; | |
86 | struct Msf2Timer *st; | |
87 | uint32_t ret = 0; | |
88 | int timer = 0; | |
89 | int isr; | |
90 | int ier; | |
91 | ||
92 | addr = offset >> 2; | |
93 | /* | |
94 | * Two independent timers has same base address. | |
95 | * Based on address passed figure out which timer is being used. | |
96 | */ | |
97 | if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { | |
98 | timer = 1; | |
99 | addr -= R_TIM1_MAX; | |
100 | } | |
101 | ||
102 | st = &t->timers[timer]; | |
103 | ||
104 | switch (addr) { | |
105 | case R_TIM_VAL: | |
106 | ret = ptimer_get_count(st->ptimer); | |
107 | break; | |
108 | ||
109 | case R_TIM_MIS: | |
110 | isr = !!(st->regs[R_TIM_RIS] & TIMER_RIS_ACK); | |
111 | ier = !!(st->regs[R_TIM_CTRL] & TIMER_CTRL_INTR); | |
112 | ret = ier & isr; | |
113 | break; | |
114 | ||
115 | default: | |
116 | if (addr < R_TIM1_MAX) { | |
117 | ret = st->regs[addr]; | |
118 | } else { | |
119 | qemu_log_mask(LOG_GUEST_ERROR, | |
120 | TYPE_MSS_TIMER": 64-bit mode not supported\n"); | |
121 | return ret; | |
122 | } | |
123 | break; | |
124 | } | |
125 | ||
126 | DB_PRINT("timer=%d 0x%" HWADDR_PRIx "=0x%" PRIx32, timer, offset, | |
127 | ret); | |
128 | return ret; | |
129 | } | |
130 | ||
131 | static void | |
132 | timer_write(void *opaque, hwaddr offset, | |
133 | uint64_t val64, unsigned int size) | |
134 | { | |
135 | MSSTimerState *t = opaque; | |
136 | hwaddr addr; | |
137 | struct Msf2Timer *st; | |
138 | int timer = 0; | |
139 | uint32_t value = val64; | |
140 | ||
141 | addr = offset >> 2; | |
142 | /* | |
143 | * Two independent timers has same base address. | |
144 | * Based on addr passed figure out which timer is being used. | |
145 | */ | |
146 | if ((addr >= R_TIM1_MAX) && (addr < NUM_TIMERS * R_TIM1_MAX)) { | |
147 | timer = 1; | |
148 | addr -= R_TIM1_MAX; | |
149 | } | |
150 | ||
151 | st = &t->timers[timer]; | |
152 | ||
153 | DB_PRINT("addr=0x%" HWADDR_PRIx " val=0x%" PRIx32 " (timer=%d)", offset, | |
154 | value, timer); | |
155 | ||
156 | switch (addr) { | |
157 | case R_TIM_CTRL: | |
158 | st->regs[R_TIM_CTRL] = value; | |
159 | timer_update(st); | |
160 | break; | |
161 | ||
162 | case R_TIM_RIS: | |
163 | if (value & TIMER_RIS_ACK) { | |
164 | st->regs[R_TIM_RIS] &= ~TIMER_RIS_ACK; | |
165 | } | |
166 | break; | |
167 | ||
168 | case R_TIM_LOADVAL: | |
169 | st->regs[R_TIM_LOADVAL] = value; | |
170 | if (st->regs[R_TIM_CTRL] & TIMER_CTRL_ENBL) { | |
171 | timer_update(st); | |
172 | } | |
173 | break; | |
174 | ||
175 | case R_TIM_BGLOADVAL: | |
176 | st->regs[R_TIM_BGLOADVAL] = value; | |
177 | st->regs[R_TIM_LOADVAL] = value; | |
178 | break; | |
179 | ||
180 | case R_TIM_VAL: | |
181 | case R_TIM_MIS: | |
182 | break; | |
183 | ||
184 | default: | |
185 | if (addr < R_TIM1_MAX) { | |
186 | st->regs[addr] = value; | |
187 | } else { | |
188 | qemu_log_mask(LOG_GUEST_ERROR, | |
189 | TYPE_MSS_TIMER": 64-bit mode not supported\n"); | |
190 | return; | |
191 | } | |
192 | break; | |
193 | } | |
194 | timer_update_irq(st); | |
195 | } | |
196 | ||
197 | static const MemoryRegionOps timer_ops = { | |
198 | .read = timer_read, | |
199 | .write = timer_write, | |
200 | .endianness = DEVICE_NATIVE_ENDIAN, | |
201 | .valid = { | |
202 | .min_access_size = 1, | |
203 | .max_access_size = 4 | |
204 | } | |
205 | }; | |
206 | ||
207 | static void timer_hit(void *opaque) | |
208 | { | |
209 | struct Msf2Timer *st = opaque; | |
210 | ||
211 | st->regs[R_TIM_RIS] |= TIMER_RIS_ACK; | |
212 | ||
213 | if (!(st->regs[R_TIM_CTRL] & TIMER_CTRL_ONESHOT)) { | |
214 | timer_update(st); | |
215 | } | |
216 | timer_update_irq(st); | |
217 | } | |
218 | ||
219 | static void mss_timer_init(Object *obj) | |
220 | { | |
221 | MSSTimerState *t = MSS_TIMER(obj); | |
222 | int i; | |
223 | ||
224 | /* Init all the ptimers. */ | |
225 | for (i = 0; i < NUM_TIMERS; i++) { | |
226 | struct Msf2Timer *st = &t->timers[i]; | |
227 | ||
228 | st->bh = qemu_bh_new(timer_hit, st); | |
229 | st->ptimer = ptimer_init(st->bh, PTIMER_POLICY_DEFAULT); | |
230 | ptimer_set_freq(st->ptimer, t->freq_hz); | |
231 | sysbus_init_irq(SYS_BUS_DEVICE(obj), &st->irq); | |
232 | } | |
233 | ||
234 | memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, TYPE_MSS_TIMER, | |
235 | NUM_TIMERS * R_TIM1_MAX * 4); | |
236 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &t->mmio); | |
237 | } | |
238 | ||
239 | static const VMStateDescription vmstate_timers = { | |
240 | .name = "mss-timer-block", | |
241 | .version_id = 1, | |
242 | .minimum_version_id = 1, | |
243 | .fields = (VMStateField[]) { | |
244 | VMSTATE_PTIMER(ptimer, struct Msf2Timer), | |
245 | VMSTATE_UINT32_ARRAY(regs, struct Msf2Timer, R_TIM1_MAX), | |
246 | VMSTATE_END_OF_LIST() | |
247 | } | |
248 | }; | |
249 | ||
250 | static const VMStateDescription vmstate_mss_timer = { | |
251 | .name = TYPE_MSS_TIMER, | |
252 | .version_id = 1, | |
253 | .minimum_version_id = 1, | |
254 | .fields = (VMStateField[]) { | |
255 | VMSTATE_UINT32(freq_hz, MSSTimerState), | |
256 | VMSTATE_STRUCT_ARRAY(timers, MSSTimerState, NUM_TIMERS, 0, | |
257 | vmstate_timers, struct Msf2Timer), | |
258 | VMSTATE_END_OF_LIST() | |
259 | } | |
260 | }; | |
261 | ||
262 | static Property mss_timer_properties[] = { | |
263 | /* Libero GUI shows 100Mhz as default for clocks */ | |
264 | DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, | |
265 | 100 * 1000000), | |
266 | DEFINE_PROP_END_OF_LIST(), | |
267 | }; | |
268 | ||
269 | static void mss_timer_class_init(ObjectClass *klass, void *data) | |
270 | { | |
271 | DeviceClass *dc = DEVICE_CLASS(klass); | |
272 | ||
273 | dc->props = mss_timer_properties; | |
274 | dc->vmsd = &vmstate_mss_timer; | |
275 | } | |
276 | ||
277 | static const TypeInfo mss_timer_info = { | |
278 | .name = TYPE_MSS_TIMER, | |
279 | .parent = TYPE_SYS_BUS_DEVICE, | |
280 | .instance_size = sizeof(MSSTimerState), | |
281 | .instance_init = mss_timer_init, | |
282 | .class_init = mss_timer_class_init, | |
283 | }; | |
284 | ||
285 | static void mss_timer_register_types(void) | |
286 | { | |
287 | type_register_static(&mss_timer_info); | |
288 | } | |
289 | ||
290 | type_init(mss_timer_register_types) |