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011d87d0 | 1 | /* |
2 | * TI OMAP2 32kHz sync timer emulation. | |
3 | * | |
4 | * Copyright (C) 2007-2008 Nokia Corporation | |
5 | * Written by Andrzej Zaborowski <andrew@openedhand.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 or | |
10 | * (at your option) any later version of the License. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License along | |
18 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
19 | */ | |
282bc81e | 20 | #include "qemu/osdep.h" |
83c9f4ca | 21 | #include "hw/hw.h" |
1de7afc9 | 22 | #include "qemu/timer.h" |
0d09e41a | 23 | #include "hw/arm/omap.h" |
011d87d0 | 24 | struct omap_synctimer_s { |
fcb40162 | 25 | MemoryRegion iomem; |
011d87d0 | 26 | uint32_t val; |
27 | uint16_t readh; | |
28 | }; | |
29 | ||
30 | /* 32-kHz Sync Timer of the OMAP2 */ | |
31 | static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) { | |
bc72ad67 | 32 | return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 0x8000, get_ticks_per_sec()); |
011d87d0 | 33 | } |
34 | ||
35 | void omap_synctimer_reset(struct omap_synctimer_s *s) | |
36 | { | |
37 | s->val = omap_synctimer_read(s); | |
38 | } | |
39 | ||
a8170e5e | 40 | static uint32_t omap_synctimer_readw(void *opaque, hwaddr addr) |
011d87d0 | 41 | { |
42 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | |
43 | ||
44 | switch (addr) { | |
45 | case 0x00: /* 32KSYNCNT_REV */ | |
46 | return 0x21; | |
47 | ||
48 | case 0x10: /* CR */ | |
49 | return omap_synctimer_read(s) - s->val; | |
50 | } | |
51 | ||
52 | OMAP_BAD_REG(addr); | |
53 | return 0; | |
54 | } | |
55 | ||
a8170e5e | 56 | static uint32_t omap_synctimer_readh(void *opaque, hwaddr addr) |
011d87d0 | 57 | { |
58 | struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque; | |
59 | uint32_t ret; | |
60 | ||
61 | if (addr & 2) | |
62 | return s->readh; | |
63 | else { | |
64 | ret = omap_synctimer_readw(opaque, addr); | |
65 | s->readh = ret >> 16; | |
66 | return ret & 0xffff; | |
67 | } | |
68 | } | |
69 | ||
a8170e5e | 70 | static void omap_synctimer_write(void *opaque, hwaddr addr, |
011d87d0 | 71 | uint32_t value) |
72 | { | |
73 | OMAP_BAD_REG(addr); | |
74 | } | |
75 | ||
fcb40162 AK |
76 | static const MemoryRegionOps omap_synctimer_ops = { |
77 | .old_mmio = { | |
78 | .read = { | |
79 | omap_badwidth_read32, | |
80 | omap_synctimer_readh, | |
81 | omap_synctimer_readw, | |
82 | }, | |
83 | .write = { | |
84 | omap_badwidth_write32, | |
85 | omap_synctimer_write, | |
86 | omap_synctimer_write, | |
87 | }, | |
88 | }, | |
89 | .endianness = DEVICE_NATIVE_ENDIAN, | |
011d87d0 | 90 | }; |
91 | ||
92 | struct omap_synctimer_s *omap_synctimer_init(struct omap_target_agent_s *ta, | |
93 | struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk) | |
94 | { | |
7267c094 | 95 | struct omap_synctimer_s *s = g_malloc0(sizeof(*s)); |
011d87d0 | 96 | |
97 | omap_synctimer_reset(s); | |
2c9b15ca | 98 | memory_region_init_io(&s->iomem, NULL, &omap_synctimer_ops, s, "omap.synctimer", |
fcb40162 | 99 | omap_l4_region_size(ta, 0)); |
f44336c5 | 100 | omap_l4_attach(ta, 0, &s->iomem); |
011d87d0 | 101 | |
102 | return s; | |
103 | } |